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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Auvitek AU8522 QAM/8VSB demodulator driver and video decoder
0004  *
0005  * Copyright (C) 2009 Devin Heitmueller <dheitmueller@linuxtv.org>
0006  * Copyright (C) 2005-2008 Auvitek International, Ltd.
0007  */
0008 
0009 /* Developer notes:
0010  *
0011  * Enough is implemented here for CVBS and S-Video inputs, but the actual
0012  *  analog demodulator code isn't implemented (not needed for xc5000 since it
0013  *  has its own demodulator and outputs CVBS)
0014  *
0015  */
0016 
0017 #include <linux/kernel.h>
0018 #include <linux/slab.h>
0019 #include <linux/videodev2.h>
0020 #include <linux/i2c.h>
0021 #include <linux/delay.h>
0022 #include <media/v4l2-common.h>
0023 #include <media/v4l2-device.h>
0024 #include "au8522.h"
0025 #include "au8522_priv.h"
0026 
0027 MODULE_AUTHOR("Devin Heitmueller");
0028 MODULE_LICENSE("GPL");
0029 
0030 static int au8522_analog_debug;
0031 
0032 
0033 module_param_named(analog_debug, au8522_analog_debug, int, 0644);
0034 
0035 MODULE_PARM_DESC(analog_debug,
0036          "Analog debugging messages [0=Off (default) 1=On]");
0037 
0038 struct au8522_register_config {
0039     u16 reg_name;
0040     u8 reg_val[8];
0041 };
0042 
0043 
0044 /* Video Decoder Filter Coefficients
0045    The values are as follows from left to right
0046    0="ATV RF" 1="ATV RF13" 2="CVBS" 3="S-Video" 4="PAL" 5=CVBS13" 6="SVideo13"
0047 */
0048 static const struct au8522_register_config filter_coef[] = {
0049     {AU8522_FILTER_COEF_R410, {0x25, 0x00, 0x25, 0x25, 0x00, 0x00, 0x00} },
0050     {AU8522_FILTER_COEF_R411, {0x20, 0x00, 0x20, 0x20, 0x00, 0x00, 0x00} },
0051     {AU8522_FILTER_COEF_R412, {0x03, 0x00, 0x03, 0x03, 0x00, 0x00, 0x00} },
0052     {AU8522_FILTER_COEF_R413, {0xe6, 0x00, 0xe6, 0xe6, 0x00, 0x00, 0x00} },
0053     {AU8522_FILTER_COEF_R414, {0x40, 0x00, 0x40, 0x40, 0x00, 0x00, 0x00} },
0054     {AU8522_FILTER_COEF_R415, {0x1b, 0x00, 0x1b, 0x1b, 0x00, 0x00, 0x00} },
0055     {AU8522_FILTER_COEF_R416, {0xc0, 0x00, 0xc0, 0x04, 0x00, 0x00, 0x00} },
0056     {AU8522_FILTER_COEF_R417, {0x04, 0x00, 0x04, 0x04, 0x00, 0x00, 0x00} },
0057     {AU8522_FILTER_COEF_R418, {0x8c, 0x00, 0x8c, 0x8c, 0x00, 0x00, 0x00} },
0058     {AU8522_FILTER_COEF_R419, {0xa0, 0x40, 0xa0, 0xa0, 0x40, 0x40, 0x40} },
0059     {AU8522_FILTER_COEF_R41A, {0x21, 0x09, 0x21, 0x21, 0x09, 0x09, 0x09} },
0060     {AU8522_FILTER_COEF_R41B, {0x6c, 0x38, 0x6c, 0x6c, 0x38, 0x38, 0x38} },
0061     {AU8522_FILTER_COEF_R41C, {0x03, 0xff, 0x03, 0x03, 0xff, 0xff, 0xff} },
0062     {AU8522_FILTER_COEF_R41D, {0xbf, 0xc7, 0xbf, 0xbf, 0xc7, 0xc7, 0xc7} },
0063     {AU8522_FILTER_COEF_R41E, {0xa0, 0xdf, 0xa0, 0xa0, 0xdf, 0xdf, 0xdf} },
0064     {AU8522_FILTER_COEF_R41F, {0x10, 0x06, 0x10, 0x10, 0x06, 0x06, 0x06} },
0065     {AU8522_FILTER_COEF_R420, {0xae, 0x30, 0xae, 0xae, 0x30, 0x30, 0x30} },
0066     {AU8522_FILTER_COEF_R421, {0xc4, 0x01, 0xc4, 0xc4, 0x01, 0x01, 0x01} },
0067     {AU8522_FILTER_COEF_R422, {0x54, 0xdd, 0x54, 0x54, 0xdd, 0xdd, 0xdd} },
0068     {AU8522_FILTER_COEF_R423, {0xd0, 0xaf, 0xd0, 0xd0, 0xaf, 0xaf, 0xaf} },
0069     {AU8522_FILTER_COEF_R424, {0x1c, 0xf7, 0x1c, 0x1c, 0xf7, 0xf7, 0xf7} },
0070     {AU8522_FILTER_COEF_R425, {0x76, 0xdb, 0x76, 0x76, 0xdb, 0xdb, 0xdb} },
0071     {AU8522_FILTER_COEF_R426, {0x61, 0xc0, 0x61, 0x61, 0xc0, 0xc0, 0xc0} },
0072     {AU8522_FILTER_COEF_R427, {0xd1, 0x2f, 0xd1, 0xd1, 0x2f, 0x2f, 0x2f} },
0073     {AU8522_FILTER_COEF_R428, {0x84, 0xd8, 0x84, 0x84, 0xd8, 0xd8, 0xd8} },
0074     {AU8522_FILTER_COEF_R429, {0x06, 0xfb, 0x06, 0x06, 0xfb, 0xfb, 0xfb} },
0075     {AU8522_FILTER_COEF_R42A, {0x21, 0xd5, 0x21, 0x21, 0xd5, 0xd5, 0xd5} },
0076     {AU8522_FILTER_COEF_R42B, {0x0a, 0x3e, 0x0a, 0x0a, 0x3e, 0x3e, 0x3e} },
0077     {AU8522_FILTER_COEF_R42C, {0xe6, 0x15, 0xe6, 0xe6, 0x15, 0x15, 0x15} },
0078     {AU8522_FILTER_COEF_R42D, {0x01, 0x34, 0x01, 0x01, 0x34, 0x34, 0x34} },
0079 
0080 };
0081 #define NUM_FILTER_COEF (sizeof(filter_coef)\
0082              / sizeof(struct au8522_register_config))
0083 
0084 
0085 /* Registers 0x060b through 0x0652 are the LP Filter coefficients
0086    The values are as follows from left to right
0087    0="SIF" 1="ATVRF/ATVRF13"
0088    Note: the "ATVRF/ATVRF13" mode has never been tested
0089 */
0090 static const struct au8522_register_config lpfilter_coef[] = {
0091     {0x060b, {0x21, 0x0b} },
0092     {0x060c, {0xad, 0xad} },
0093     {0x060d, {0x70, 0xf0} },
0094     {0x060e, {0xea, 0xe9} },
0095     {0x060f, {0xdd, 0xdd} },
0096     {0x0610, {0x08, 0x64} },
0097     {0x0611, {0x60, 0x60} },
0098     {0x0612, {0xf8, 0xb2} },
0099     {0x0613, {0x01, 0x02} },
0100     {0x0614, {0xe4, 0xb4} },
0101     {0x0615, {0x19, 0x02} },
0102     {0x0616, {0xae, 0x2e} },
0103     {0x0617, {0xee, 0xc5} },
0104     {0x0618, {0x56, 0x56} },
0105     {0x0619, {0x30, 0x58} },
0106     {0x061a, {0xf9, 0xf8} },
0107     {0x061b, {0x24, 0x64} },
0108     {0x061c, {0x07, 0x07} },
0109     {0x061d, {0x30, 0x30} },
0110     {0x061e, {0xa9, 0xed} },
0111     {0x061f, {0x09, 0x0b} },
0112     {0x0620, {0x42, 0xc2} },
0113     {0x0621, {0x1d, 0x2a} },
0114     {0x0622, {0xd6, 0x56} },
0115     {0x0623, {0x95, 0x8b} },
0116     {0x0624, {0x2b, 0x2b} },
0117     {0x0625, {0x30, 0x24} },
0118     {0x0626, {0x3e, 0x3e} },
0119     {0x0627, {0x62, 0xe2} },
0120     {0x0628, {0xe9, 0xf5} },
0121     {0x0629, {0x99, 0x19} },
0122     {0x062a, {0xd4, 0x11} },
0123     {0x062b, {0x03, 0x04} },
0124     {0x062c, {0xb5, 0x85} },
0125     {0x062d, {0x1e, 0x20} },
0126     {0x062e, {0x2a, 0xea} },
0127     {0x062f, {0xd7, 0xd2} },
0128     {0x0630, {0x15, 0x15} },
0129     {0x0631, {0xa3, 0xa9} },
0130     {0x0632, {0x1f, 0x1f} },
0131     {0x0633, {0xf9, 0xd1} },
0132     {0x0634, {0xc0, 0xc3} },
0133     {0x0635, {0x4d, 0x8d} },
0134     {0x0636, {0x21, 0x31} },
0135     {0x0637, {0x83, 0x83} },
0136     {0x0638, {0x08, 0x8c} },
0137     {0x0639, {0x19, 0x19} },
0138     {0x063a, {0x45, 0xa5} },
0139     {0x063b, {0xef, 0xec} },
0140     {0x063c, {0x8a, 0x8a} },
0141     {0x063d, {0xf4, 0xf6} },
0142     {0x063e, {0x8f, 0x8f} },
0143     {0x063f, {0x44, 0x0c} },
0144     {0x0640, {0xef, 0xf0} },
0145     {0x0641, {0x66, 0x66} },
0146     {0x0642, {0xcc, 0xd2} },
0147     {0x0643, {0x41, 0x41} },
0148     {0x0644, {0x63, 0x93} },
0149     {0x0645, {0x8e, 0x8e} },
0150     {0x0646, {0xa2, 0x42} },
0151     {0x0647, {0x7b, 0x7b} },
0152     {0x0648, {0x04, 0x04} },
0153     {0x0649, {0x00, 0x00} },
0154     {0x064a, {0x40, 0x40} },
0155     {0x064b, {0x8c, 0x98} },
0156     {0x064c, {0x00, 0x00} },
0157     {0x064d, {0x63, 0xc3} },
0158     {0x064e, {0x04, 0x04} },
0159     {0x064f, {0x20, 0x20} },
0160     {0x0650, {0x00, 0x00} },
0161     {0x0651, {0x40, 0x40} },
0162     {0x0652, {0x01, 0x01} },
0163 };
0164 #define NUM_LPFILTER_COEF (sizeof(lpfilter_coef)\
0165                / sizeof(struct au8522_register_config))
0166 
0167 static inline struct au8522_state *to_state(struct v4l2_subdev *sd)
0168 {
0169     return container_of(sd, struct au8522_state, sd);
0170 }
0171 
0172 static void setup_decoder_defaults(struct au8522_state *state, bool is_svideo)
0173 {
0174     int i;
0175     int filter_coef_type;
0176 
0177     /* Provide reasonable defaults for picture tuning values */
0178     au8522_writereg(state, AU8522_TVDEC_SHARPNESSREG009H, 0x07);
0179     au8522_writereg(state, AU8522_TVDEC_BRIGHTNESS_REG00AH, 0xed);
0180     au8522_writereg(state, AU8522_TVDEC_CONTRAST_REG00BH, 0x79);
0181     au8522_writereg(state, AU8522_TVDEC_SATURATION_CB_REG00CH, 0x80);
0182     au8522_writereg(state, AU8522_TVDEC_SATURATION_CR_REG00DH, 0x80);
0183     au8522_writereg(state, AU8522_TVDEC_HUE_H_REG00EH, 0x00);
0184     au8522_writereg(state, AU8522_TVDEC_HUE_L_REG00FH, 0x00);
0185 
0186     /* Other decoder registers */
0187     au8522_writereg(state, AU8522_TVDEC_INT_MASK_REG010H, 0x00);
0188 
0189     if (is_svideo)
0190         au8522_writereg(state, AU8522_VIDEO_MODE_REG011H, 0x04);
0191     else
0192         au8522_writereg(state, AU8522_VIDEO_MODE_REG011H, 0x00);
0193 
0194     au8522_writereg(state, AU8522_TVDEC_PGA_REG012H,
0195             AU8522_TVDEC_PGA_REG012H_CVBS);
0196     au8522_writereg(state, AU8522_TVDEC_COMB_MODE_REG015H,
0197             AU8522_TVDEC_COMB_MODE_REG015H_CVBS);
0198     au8522_writereg(state, AU8522_TVDED_DBG_MODE_REG060H,
0199             AU8522_TVDED_DBG_MODE_REG060H_CVBS);
0200 
0201     if (state->std == V4L2_STD_PAL_M) {
0202         au8522_writereg(state, AU8522_TVDEC_FORMAT_CTRL1_REG061H,
0203                 AU8522_TVDEC_FORMAT_CTRL1_REG061H_FIELD_LEN_525 |
0204                 AU8522_TVDEC_FORMAT_CTRL1_REG061H_LINE_LEN_63_492 |
0205                 AU8522_TVDEC_FORMAT_CTRL1_REG061H_SUBCARRIER_NTSC_AUTO);
0206         au8522_writereg(state, AU8522_TVDEC_FORMAT_CTRL2_REG062H,
0207                 AU8522_TVDEC_FORMAT_CTRL2_REG062H_STD_PAL_M);
0208     } else {
0209         /* NTSC */
0210         au8522_writereg(state, AU8522_TVDEC_FORMAT_CTRL1_REG061H,
0211                 AU8522_TVDEC_FORMAT_CTRL1_REG061H_FIELD_LEN_525 |
0212                 AU8522_TVDEC_FORMAT_CTRL1_REG061H_LINE_LEN_63_492 |
0213                 AU8522_TVDEC_FORMAT_CTRL1_REG061H_SUBCARRIER_NTSC_MN);
0214         au8522_writereg(state, AU8522_TVDEC_FORMAT_CTRL2_REG062H,
0215                 AU8522_TVDEC_FORMAT_CTRL2_REG062H_STD_NTSC);
0216     }
0217     au8522_writereg(state, AU8522_TVDEC_VCR_DET_LLIM_REG063H,
0218             AU8522_TVDEC_VCR_DET_LLIM_REG063H_CVBS);
0219     au8522_writereg(state, AU8522_TVDEC_VCR_DET_HLIM_REG064H,
0220             AU8522_TVDEC_VCR_DET_HLIM_REG064H_CVBS);
0221     au8522_writereg(state, AU8522_TVDEC_COMB_VDIF_THR1_REG065H,
0222             AU8522_TVDEC_COMB_VDIF_THR1_REG065H_CVBS);
0223     au8522_writereg(state, AU8522_TVDEC_COMB_VDIF_THR2_REG066H,
0224             AU8522_TVDEC_COMB_VDIF_THR2_REG066H_CVBS);
0225     au8522_writereg(state, AU8522_TVDEC_COMB_VDIF_THR3_REG067H,
0226             AU8522_TVDEC_COMB_VDIF_THR3_REG067H_CVBS);
0227     au8522_writereg(state, AU8522_TVDEC_COMB_NOTCH_THR_REG068H,
0228             AU8522_TVDEC_COMB_NOTCH_THR_REG068H_CVBS);
0229     au8522_writereg(state, AU8522_TVDEC_COMB_HDIF_THR1_REG069H,
0230             AU8522_TVDEC_COMB_HDIF_THR1_REG069H_CVBS);
0231     au8522_writereg(state, AU8522_TVDEC_COMB_HDIF_THR2_REG06AH,
0232             AU8522_TVDEC_COMB_HDIF_THR2_REG06AH_CVBS);
0233     au8522_writereg(state, AU8522_TVDEC_COMB_HDIF_THR3_REG06BH,
0234             AU8522_TVDEC_COMB_HDIF_THR3_REG06BH_CVBS);
0235     if (is_svideo) {
0236         au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH,
0237                 AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH_SVIDEO);
0238         au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH,
0239                 AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH_SVIDEO);
0240     } else {
0241         au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH,
0242                 AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH_CVBS);
0243         au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH,
0244                 AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH_CVBS);
0245     }
0246     au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR3_REG06EH,
0247             AU8522_TVDEC_COMB_DCDIF_THR3_REG06EH_CVBS);
0248     au8522_writereg(state, AU8522_TVDEC_UV_SEP_THR_REG06FH,
0249             AU8522_TVDEC_UV_SEP_THR_REG06FH_CVBS);
0250     au8522_writereg(state, AU8522_TVDEC_COMB_DC_THR1_NTSC_REG070H,
0251             AU8522_TVDEC_COMB_DC_THR1_NTSC_REG070H_CVBS);
0252     au8522_writereg(state, AU8522_REG071H, AU8522_REG071H_CVBS);
0253     au8522_writereg(state, AU8522_REG072H, AU8522_REG072H_CVBS);
0254     au8522_writereg(state, AU8522_TVDEC_COMB_DC_THR2_NTSC_REG073H,
0255             AU8522_TVDEC_COMB_DC_THR2_NTSC_REG073H_CVBS);
0256     au8522_writereg(state, AU8522_REG074H, AU8522_REG074H_CVBS);
0257     au8522_writereg(state, AU8522_REG075H, AU8522_REG075H_CVBS);
0258     au8522_writereg(state, AU8522_TVDEC_DCAGC_CTRL_REG077H,
0259             AU8522_TVDEC_DCAGC_CTRL_REG077H_CVBS);
0260     au8522_writereg(state, AU8522_TVDEC_PIC_START_ADJ_REG078H,
0261             AU8522_TVDEC_PIC_START_ADJ_REG078H_CVBS);
0262     au8522_writereg(state, AU8522_TVDEC_AGC_HIGH_LIMIT_REG079H,
0263             AU8522_TVDEC_AGC_HIGH_LIMIT_REG079H_CVBS);
0264     au8522_writereg(state, AU8522_TVDEC_MACROVISION_SYNC_THR_REG07AH,
0265             AU8522_TVDEC_MACROVISION_SYNC_THR_REG07AH_CVBS);
0266     au8522_writereg(state, AU8522_TVDEC_INTRP_CTRL_REG07BH,
0267             AU8522_TVDEC_INTRP_CTRL_REG07BH_CVBS);
0268     au8522_writereg(state, AU8522_TVDEC_AGC_LOW_LIMIT_REG0E4H,
0269             AU8522_TVDEC_AGC_LOW_LIMIT_REG0E4H_CVBS);
0270     au8522_writereg(state, AU8522_TOREGAAGC_REG0E5H,
0271             AU8522_TOREGAAGC_REG0E5H_CVBS);
0272     au8522_writereg(state, AU8522_REG016H, AU8522_REG016H_CVBS);
0273 
0274     /*
0275      * Despite what the table says, for the HVR-950q we still need
0276      * to be in CVBS mode for the S-Video input (reason unknown).
0277      */
0278     /* filter_coef_type = 3; */
0279     filter_coef_type = 5;
0280 
0281     /* Load the Video Decoder Filter Coefficients */
0282     for (i = 0; i < NUM_FILTER_COEF; i++) {
0283         au8522_writereg(state, filter_coef[i].reg_name,
0284                 filter_coef[i].reg_val[filter_coef_type]);
0285     }
0286 
0287     /* It's not clear what these registers are for, but they are always
0288        set to the same value regardless of what mode we're in */
0289     au8522_writereg(state, AU8522_REG42EH, 0x87);
0290     au8522_writereg(state, AU8522_REG42FH, 0xa2);
0291     au8522_writereg(state, AU8522_REG430H, 0xbf);
0292     au8522_writereg(state, AU8522_REG431H, 0xcb);
0293     au8522_writereg(state, AU8522_REG432H, 0xa1);
0294     au8522_writereg(state, AU8522_REG433H, 0x41);
0295     au8522_writereg(state, AU8522_REG434H, 0x88);
0296     au8522_writereg(state, AU8522_REG435H, 0xc2);
0297     au8522_writereg(state, AU8522_REG436H, 0x3c);
0298 }
0299 
0300 static void au8522_setup_cvbs_mode(struct au8522_state *state, u8 input_mode)
0301 {
0302     /* here we're going to try the pre-programmed route */
0303     au8522_writereg(state, AU8522_MODULE_CLOCK_CONTROL_REG0A3H,
0304             AU8522_MODULE_CLOCK_CONTROL_REG0A3H_CVBS);
0305 
0306     /* PGA in automatic mode */
0307     au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x00);
0308 
0309     /* Enable clamping control */
0310     au8522_writereg(state, AU8522_CLAMPING_CONTROL_REG083H, 0x00);
0311 
0312     au8522_writereg(state, AU8522_INPUT_CONTROL_REG081H, input_mode);
0313 
0314     setup_decoder_defaults(state, false);
0315 
0316     au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
0317             AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_CVBS);
0318 }
0319 
0320 static void au8522_setup_cvbs_tuner_mode(struct au8522_state *state,
0321                      u8 input_mode)
0322 {
0323     /* here we're going to try the pre-programmed route */
0324     au8522_writereg(state, AU8522_MODULE_CLOCK_CONTROL_REG0A3H,
0325             AU8522_MODULE_CLOCK_CONTROL_REG0A3H_CVBS);
0326 
0327     /* It's not clear why we have to have the PGA in automatic mode while
0328        enabling clamp control, but it's what Windows does */
0329     au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x00);
0330 
0331     /* Enable clamping control */
0332     au8522_writereg(state, AU8522_CLAMPING_CONTROL_REG083H, 0x0e);
0333 
0334     /* Disable automatic PGA (since the CVBS is coming from the tuner) */
0335     au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x10);
0336 
0337     /* Set input mode to CVBS on channel 4 with SIF audio input enabled */
0338     au8522_writereg(state, AU8522_INPUT_CONTROL_REG081H, input_mode);
0339 
0340     setup_decoder_defaults(state, false);
0341 
0342     au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
0343             AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_CVBS);
0344 }
0345 
0346 static void au8522_setup_svideo_mode(struct au8522_state *state,
0347                      u8 input_mode)
0348 {
0349     au8522_writereg(state, AU8522_MODULE_CLOCK_CONTROL_REG0A3H,
0350             AU8522_MODULE_CLOCK_CONTROL_REG0A3H_SVIDEO);
0351 
0352     /* Set input to Y on Channe1, C on Channel 3 */
0353     au8522_writereg(state, AU8522_INPUT_CONTROL_REG081H, input_mode);
0354 
0355     /* PGA in automatic mode */
0356     au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x00);
0357 
0358     /* Enable clamping control */
0359     au8522_writereg(state, AU8522_CLAMPING_CONTROL_REG083H, 0x00);
0360 
0361     setup_decoder_defaults(state, true);
0362 
0363     au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
0364             AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_CVBS);
0365 }
0366 
0367 /* ----------------------------------------------------------------------- */
0368 
0369 static void disable_audio_input(struct au8522_state *state)
0370 {
0371     au8522_writereg(state, AU8522_AUDIO_VOLUME_L_REG0F2H, 0x00);
0372     au8522_writereg(state, AU8522_AUDIO_VOLUME_R_REG0F3H, 0x00);
0373     au8522_writereg(state, AU8522_AUDIO_VOLUME_REG0F4H, 0x00);
0374 
0375     au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H, 0x04);
0376     au8522_writereg(state, AU8522_I2S_CTRL_2_REG112H, 0x02);
0377 
0378     au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
0379             AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_SVIDEO);
0380 }
0381 
0382 /* 0=disable, 1=SIF */
0383 static void set_audio_input(struct au8522_state *state)
0384 {
0385     int aud_input = state->aud_input;
0386     int i;
0387 
0388     /* Note that this function needs to be used in conjunction with setting
0389        the input routing via register 0x81 */
0390 
0391     if (aud_input == AU8522_AUDIO_NONE) {
0392         disable_audio_input(state);
0393         return;
0394     }
0395 
0396     if (aud_input != AU8522_AUDIO_SIF) {
0397         /* The caller asked for a mode we don't currently support */
0398         printk(KERN_ERR "Unsupported audio mode requested! mode=%d\n",
0399                aud_input);
0400         return;
0401     }
0402 
0403     /* Load the Audio Decoder Filter Coefficients */
0404     for (i = 0; i < NUM_LPFILTER_COEF; i++) {
0405         au8522_writereg(state, lpfilter_coef[i].reg_name,
0406                 lpfilter_coef[i].reg_val[0]);
0407     }
0408 
0409     /* Set the volume */
0410     au8522_writereg(state, AU8522_AUDIO_VOLUME_L_REG0F2H, 0x7F);
0411     au8522_writereg(state, AU8522_AUDIO_VOLUME_R_REG0F3H, 0x7F);
0412     au8522_writereg(state, AU8522_AUDIO_VOLUME_REG0F4H, 0xff);
0413 
0414     /* Not sure what this does */
0415     au8522_writereg(state, AU8522_REG0F9H, AU8522_REG0F9H_AUDIO);
0416 
0417     /* Setup the audio mode to stereo DBX */
0418     au8522_writereg(state, AU8522_AUDIO_MODE_REG0F1H, 0x82);
0419     msleep(70);
0420 
0421     /* Start the audio processing module */
0422     au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H, 0x9d);
0423 
0424     /* Set the audio frequency to 48 KHz */
0425     au8522_writereg(state, AU8522_AUDIOFREQ_REG606H, 0x03);
0426 
0427     /* Set the I2S parameters (WS, LSB, mode, sample rate */
0428     au8522_writereg(state, AU8522_I2S_CTRL_2_REG112H, 0xc2);
0429 
0430     /* Enable the I2S output */
0431     au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H, 0x09);
0432 }
0433 
0434 /* ----------------------------------------------------------------------- */
0435 
0436 static int au8522_s_ctrl(struct v4l2_ctrl *ctrl)
0437 {
0438     struct au8522_state *state =
0439         container_of(ctrl->handler, struct au8522_state, hdl);
0440 
0441     switch (ctrl->id) {
0442     case V4L2_CID_BRIGHTNESS:
0443         au8522_writereg(state, AU8522_TVDEC_BRIGHTNESS_REG00AH,
0444                 ctrl->val - 128);
0445         break;
0446     case V4L2_CID_CONTRAST:
0447         au8522_writereg(state, AU8522_TVDEC_CONTRAST_REG00BH,
0448                 ctrl->val);
0449         break;
0450     case V4L2_CID_SATURATION:
0451         au8522_writereg(state, AU8522_TVDEC_SATURATION_CB_REG00CH,
0452                 ctrl->val);
0453         au8522_writereg(state, AU8522_TVDEC_SATURATION_CR_REG00DH,
0454                 ctrl->val);
0455         break;
0456     case V4L2_CID_HUE:
0457         au8522_writereg(state, AU8522_TVDEC_HUE_H_REG00EH,
0458                 ctrl->val >> 8);
0459         au8522_writereg(state, AU8522_TVDEC_HUE_L_REG00FH,
0460                 ctrl->val & 0xFF);
0461         break;
0462     default:
0463         return -EINVAL;
0464     }
0465 
0466     return 0;
0467 }
0468 
0469 /* ----------------------------------------------------------------------- */
0470 
0471 #ifdef CONFIG_VIDEO_ADV_DEBUG
0472 static int au8522_g_register(struct v4l2_subdev *sd,
0473                  struct v4l2_dbg_register *reg)
0474 {
0475     struct au8522_state *state = to_state(sd);
0476 
0477     reg->val = au8522_readreg(state, reg->reg & 0xffff);
0478     return 0;
0479 }
0480 
0481 static int au8522_s_register(struct v4l2_subdev *sd,
0482                  const struct v4l2_dbg_register *reg)
0483 {
0484     struct au8522_state *state = to_state(sd);
0485 
0486     au8522_writereg(state, reg->reg, reg->val & 0xff);
0487     return 0;
0488 }
0489 #endif
0490 
0491 static void au8522_video_set(struct au8522_state *state)
0492 {
0493     u8 input_mode;
0494 
0495     au8522_writereg(state, 0xa4, 1 << 5);
0496 
0497     switch (state->vid_input) {
0498     case AU8522_COMPOSITE_CH1:
0499         input_mode = AU8522_INPUT_CONTROL_REG081H_CVBS_CH1;
0500         au8522_setup_cvbs_mode(state, input_mode);
0501         break;
0502     case AU8522_COMPOSITE_CH2:
0503         input_mode = AU8522_INPUT_CONTROL_REG081H_CVBS_CH2;
0504         au8522_setup_cvbs_mode(state, input_mode);
0505         break;
0506     case AU8522_COMPOSITE_CH3:
0507         input_mode = AU8522_INPUT_CONTROL_REG081H_CVBS_CH3;
0508         au8522_setup_cvbs_mode(state, input_mode);
0509         break;
0510     case AU8522_COMPOSITE_CH4:
0511         input_mode = AU8522_INPUT_CONTROL_REG081H_CVBS_CH4;
0512         au8522_setup_cvbs_mode(state, input_mode);
0513         break;
0514     case AU8522_SVIDEO_CH13:
0515         input_mode = AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH13;
0516         au8522_setup_svideo_mode(state, input_mode);
0517         break;
0518     case AU8522_SVIDEO_CH24:
0519         input_mode = AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH24;
0520         au8522_setup_svideo_mode(state, input_mode);
0521         break;
0522     default:
0523     case AU8522_COMPOSITE_CH4_SIF:
0524         input_mode = AU8522_INPUT_CONTROL_REG081H_CVBS_CH4_SIF;
0525         au8522_setup_cvbs_tuner_mode(state, input_mode);
0526         break;
0527     }
0528 }
0529 
0530 static int au8522_s_stream(struct v4l2_subdev *sd, int enable)
0531 {
0532     struct au8522_state *state = to_state(sd);
0533 
0534     if (enable) {
0535         /*
0536          * Clear out any state associated with the digital side of the
0537          * chip, so that when it gets powered back up it won't think
0538          * that it is already tuned
0539          */
0540         state->current_frequency = 0;
0541 
0542         au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
0543                 0x01);
0544         msleep(10);
0545 
0546         au8522_video_set(state);
0547         set_audio_input(state);
0548 
0549         state->operational_mode = AU8522_ANALOG_MODE;
0550     } else {
0551         /* This does not completely power down the device
0552            (it only reduces it from around 140ma to 80ma) */
0553         au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
0554                 1 << 5);
0555         state->operational_mode = AU8522_SUSPEND_MODE;
0556     }
0557     return 0;
0558 }
0559 
0560 static int au8522_s_video_routing(struct v4l2_subdev *sd,
0561                     u32 input, u32 output, u32 config)
0562 {
0563     struct au8522_state *state = to_state(sd);
0564 
0565     switch (input) {
0566     case AU8522_COMPOSITE_CH1:
0567     case AU8522_SVIDEO_CH13:
0568     case AU8522_COMPOSITE_CH4_SIF:
0569         state->vid_input = input;
0570         break;
0571     default:
0572         printk(KERN_ERR "au8522 mode not currently supported\n");
0573         return -EINVAL;
0574     }
0575 
0576     if (state->operational_mode == AU8522_ANALOG_MODE)
0577         au8522_video_set(state);
0578 
0579     return 0;
0580 }
0581 
0582 static int au8522_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
0583 {
0584     struct au8522_state *state = to_state(sd);
0585 
0586     if ((std & (V4L2_STD_PAL_M | V4L2_STD_NTSC_M)) == 0)
0587         return -EINVAL;
0588 
0589     state->std = std;
0590 
0591     if (state->operational_mode == AU8522_ANALOG_MODE)
0592         au8522_video_set(state);
0593 
0594     return 0;
0595 }
0596 
0597 static int au8522_s_audio_routing(struct v4l2_subdev *sd,
0598                     u32 input, u32 output, u32 config)
0599 {
0600     struct au8522_state *state = to_state(sd);
0601 
0602     state->aud_input = input;
0603 
0604     if (state->operational_mode == AU8522_ANALOG_MODE)
0605         set_audio_input(state);
0606 
0607     return 0;
0608 }
0609 
0610 static int au8522_g_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt)
0611 {
0612     int val = 0;
0613     struct au8522_state *state = to_state(sd);
0614     u8 lock_status;
0615     u8 pll_status;
0616 
0617     /* Interrogate the decoder to see if we are getting a real signal */
0618     lock_status = au8522_readreg(state, 0x00);
0619     pll_status = au8522_readreg(state, 0x7e);
0620     if ((lock_status == 0xa2) && (pll_status & 0x10))
0621         vt->signal = 0xffff;
0622     else
0623         vt->signal = 0x00;
0624 
0625     vt->capability |=
0626         V4L2_TUNER_CAP_STEREO | V4L2_TUNER_CAP_LANG1 |
0627         V4L2_TUNER_CAP_LANG2 | V4L2_TUNER_CAP_SAP;
0628 
0629     val = V4L2_TUNER_SUB_MONO;
0630     vt->rxsubchans = val;
0631     vt->audmode = V4L2_TUNER_MODE_STEREO;
0632     return 0;
0633 }
0634 
0635 /* ----------------------------------------------------------------------- */
0636 
0637 static const struct v4l2_subdev_core_ops au8522_core_ops = {
0638     .log_status = v4l2_ctrl_subdev_log_status,
0639 #ifdef CONFIG_VIDEO_ADV_DEBUG
0640     .g_register = au8522_g_register,
0641     .s_register = au8522_s_register,
0642 #endif
0643 };
0644 
0645 static const struct v4l2_subdev_tuner_ops au8522_tuner_ops = {
0646     .g_tuner = au8522_g_tuner,
0647 };
0648 
0649 static const struct v4l2_subdev_audio_ops au8522_audio_ops = {
0650     .s_routing = au8522_s_audio_routing,
0651 };
0652 
0653 static const struct v4l2_subdev_video_ops au8522_video_ops = {
0654     .s_routing = au8522_s_video_routing,
0655     .s_stream = au8522_s_stream,
0656     .s_std = au8522_s_std,
0657 };
0658 
0659 static const struct v4l2_subdev_ops au8522_ops = {
0660     .core = &au8522_core_ops,
0661     .tuner = &au8522_tuner_ops,
0662     .audio = &au8522_audio_ops,
0663     .video = &au8522_video_ops,
0664 };
0665 
0666 static const struct v4l2_ctrl_ops au8522_ctrl_ops = {
0667     .s_ctrl = au8522_s_ctrl,
0668 };
0669 
0670 /* ----------------------------------------------------------------------- */
0671 
0672 static int au8522_probe(struct i2c_client *client,
0673             const struct i2c_device_id *did)
0674 {
0675     struct au8522_state *state;
0676     struct v4l2_ctrl_handler *hdl;
0677     struct v4l2_subdev *sd;
0678     int instance;
0679 #ifdef CONFIG_MEDIA_CONTROLLER
0680     int ret;
0681 #endif
0682 
0683     /* Check if the adapter supports the needed features */
0684     if (!i2c_check_functionality(client->adapter,
0685                      I2C_FUNC_SMBUS_BYTE_DATA)) {
0686         return -EIO;
0687     }
0688 
0689     /* allocate memory for the internal state */
0690     instance = au8522_get_state(&state, client->adapter, client->addr);
0691     switch (instance) {
0692     case 0:
0693         printk(KERN_ERR "au8522_decoder allocation failed\n");
0694         return -EIO;
0695     case 1:
0696         /* new demod instance */
0697         printk(KERN_INFO "au8522_decoder creating new instance...\n");
0698         break;
0699     default:
0700         /* existing demod instance */
0701         printk(KERN_INFO "au8522_decoder attach existing instance.\n");
0702         break;
0703     }
0704 
0705     state->config.demod_address = 0x8e >> 1;
0706     state->i2c = client->adapter;
0707 
0708     sd = &state->sd;
0709     v4l2_i2c_subdev_init(sd, client, &au8522_ops);
0710 #if defined(CONFIG_MEDIA_CONTROLLER)
0711 
0712     state->pads[AU8522_PAD_IF_INPUT].flags = MEDIA_PAD_FL_SINK;
0713     state->pads[AU8522_PAD_IF_INPUT].sig_type = PAD_SIGNAL_ANALOG;
0714     state->pads[AU8522_PAD_VID_OUT].flags = MEDIA_PAD_FL_SOURCE;
0715     state->pads[AU8522_PAD_VID_OUT].sig_type = PAD_SIGNAL_DV;
0716     state->pads[AU8522_PAD_AUDIO_OUT].flags = MEDIA_PAD_FL_SOURCE;
0717     state->pads[AU8522_PAD_AUDIO_OUT].sig_type = PAD_SIGNAL_AUDIO;
0718     sd->entity.function = MEDIA_ENT_F_ATV_DECODER;
0719 
0720     ret = media_entity_pads_init(&sd->entity, ARRAY_SIZE(state->pads),
0721                 state->pads);
0722     if (ret < 0) {
0723         v4l_info(client, "failed to initialize media entity!\n");
0724         return ret;
0725     }
0726 #endif
0727 
0728     hdl = &state->hdl;
0729     v4l2_ctrl_handler_init(hdl, 4);
0730     v4l2_ctrl_new_std(hdl, &au8522_ctrl_ops,
0731             V4L2_CID_BRIGHTNESS, 0, 255, 1, 109);
0732     v4l2_ctrl_new_std(hdl, &au8522_ctrl_ops,
0733             V4L2_CID_CONTRAST, 0, 255, 1,
0734             AU8522_TVDEC_CONTRAST_REG00BH_CVBS);
0735     v4l2_ctrl_new_std(hdl, &au8522_ctrl_ops,
0736             V4L2_CID_SATURATION, 0, 255, 1, 128);
0737     v4l2_ctrl_new_std(hdl, &au8522_ctrl_ops,
0738             V4L2_CID_HUE, -32768, 32767, 1, 0);
0739     sd->ctrl_handler = hdl;
0740     if (hdl->error) {
0741         int err = hdl->error;
0742 
0743         v4l2_ctrl_handler_free(hdl);
0744         au8522_release_state(state);
0745         return err;
0746     }
0747 
0748     state->c = client;
0749     state->std = V4L2_STD_NTSC_M;
0750     state->vid_input = AU8522_COMPOSITE_CH1;
0751     state->aud_input = AU8522_AUDIO_NONE;
0752     state->id = 8522;
0753     state->rev = 0;
0754 
0755     /* Jam open the i2c gate to the tuner */
0756     au8522_writereg(state, 0x106, 1);
0757 
0758     return 0;
0759 }
0760 
0761 static int au8522_remove(struct i2c_client *client)
0762 {
0763     struct v4l2_subdev *sd = i2c_get_clientdata(client);
0764     v4l2_device_unregister_subdev(sd);
0765     v4l2_ctrl_handler_free(sd->ctrl_handler);
0766     au8522_release_state(to_state(sd));
0767     return 0;
0768 }
0769 
0770 static const struct i2c_device_id au8522_id[] = {
0771     {"au8522", 0},
0772     {}
0773 };
0774 
0775 MODULE_DEVICE_TABLE(i2c, au8522_id);
0776 
0777 static struct i2c_driver au8522_driver = {
0778     .driver = {
0779         .name   = "au8522",
0780     },
0781     .probe      = au8522_probe,
0782     .remove     = au8522_remove,
0783     .id_table   = au8522_id,
0784 };
0785 
0786 module_i2c_driver(au8522_driver);
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