media/dvb-frontends/atbm8830_priv.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  *    Support for AltoBeam GB20600 (a.k.a DMB-TH) demodulator
0004  *    ATBM8830, ATBM8831
0005  *
0006  *    Copyright (C) 2009 David T.L. Wong <davidtlwong@gmail.com>
0007  */
0008
0009 #ifndef __ATBM8830_PRIV_H
0010 #define __ATBM8830_PRIV_H
0011
0012 struct atbm_state {
0013     struct i2c_adapter *i2c;
0014     /* configuration settings */
0015     const struct atbm8830_config *config;
0016     struct dvb_frontend frontend;
0017 };
0018
0019 #define REG_CHIP_ID 0x0000
0020 #define REG_TUNER_BASEBAND  0x0001
0021 #define REG_DEMOD_RUN   0x0004
0022 #define REG_DSP_RESET   0x0005
0023 #define REG_RAM_RESET   0x0006
0024 #define REG_ADC_RESET   0x0007
0025 #define REG_TSPORT_RESET    0x0008
0026 #define REG_BLKERR_POL  0x000C
0027 #define REG_I2C_GATE    0x0103
0028 #define REG_TS_SAMPLE_EDGE  0x0301
0029 #define REG_TS_PKT_LEN_204  0x0302
0030 #define REG_TS_PKT_LEN_AUTO 0x0303
0031 #define REG_TS_SERIAL   0x0305
0032 #define REG_TS_CLK_FREERUN  0x0306
0033 #define REG_TS_VALID_MODE   0x0307
0034 #define REG_TS_CLK_MODE 0x030B /* 1 for serial, 0 for parallel */
0035
0036 #define REG_TS_ERRBIT_USE   0x030C
0037 #define REG_LOCK_STATUS 0x030D
0038 #define REG_ADC_CONFIG  0x0602
0039 #define REG_CARRIER_OFFSET  0x0827 /* 0x0827-0x0829 little endian */
0040 #define REG_DETECTED_PN_MODE    0x082D
0041 #define REG_READ_LATCH  0x084D
0042 #define REG_IF_FREQ 0x0A00 /* 0x0A00-0x0A02 little endian */
0043 #define REG_OSC_CLK 0x0A03 /* 0x0A03-0x0A05 little endian */
0044 #define REG_BYPASS_CCI  0x0A06
0045 #define REG_ANALOG_LUMA_DETECTED    0x0A25
0046 #define REG_ANALOG_AUDIO_DETECTED   0x0A26
0047 #define REG_ANALOG_CHROMA_DETECTED  0x0A39
0048 #define REG_FRAME_ERR_CNT   0x0B04
0049 #define REG_USE_EXT_ADC 0x0C00
0050 #define REG_SWAP_I_Q    0x0C01
0051 #define REG_TPS_MANUAL  0x0D01
0052 #define REG_TPS_CONFIG  0x0D02
0053 #define REG_BYPASS_DEINTERLEAVER    0x0E00
0054 #define REG_AGC_TARGET  0x1003 /* 0x1003-0x1005 little endian */
0055 #define REG_AGC_MIN 0x1020
0056 #define REG_AGC_MAX 0x1023
0057 #define REG_AGC_LOCK    0x1027
0058 #define REG_AGC_PWM_VAL 0x1028 /* 0x1028-0x1029 little endian */
0059 #define REG_AGC_HOLD_LOOP   0x1031
0060
0061 #endif
0062