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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * ascot2e.c
0004  *
0005  * Sony Ascot3E DVB-T/T2/C/C2 tuner driver
0006  *
0007  * Copyright 2012 Sony Corporation
0008  * Copyright (C) 2014 NetUP Inc.
0009  * Copyright (C) 2014 Sergey Kozlov <serjk@netup.ru>
0010  * Copyright (C) 2014 Abylay Ospan <aospan@netup.ru>
0011   */
0012 
0013 #include <linux/slab.h>
0014 #include <linux/module.h>
0015 #include <linux/dvb/frontend.h>
0016 #include <linux/types.h>
0017 #include "ascot2e.h"
0018 #include <media/dvb_frontend.h>
0019 
0020 #define MAX_WRITE_REGSIZE 10
0021 
0022 enum ascot2e_state {
0023     STATE_UNKNOWN,
0024     STATE_SLEEP,
0025     STATE_ACTIVE
0026 };
0027 
0028 struct ascot2e_priv {
0029     u32         frequency;
0030     u8          i2c_address;
0031     struct i2c_adapter  *i2c;
0032     enum ascot2e_state  state;
0033     void            *set_tuner_data;
0034     int         (*set_tuner)(void *, int);
0035 };
0036 
0037 enum ascot2e_tv_system_t {
0038     ASCOT2E_DTV_DVBT_5,
0039     ASCOT2E_DTV_DVBT_6,
0040     ASCOT2E_DTV_DVBT_7,
0041     ASCOT2E_DTV_DVBT_8,
0042     ASCOT2E_DTV_DVBT2_1_7,
0043     ASCOT2E_DTV_DVBT2_5,
0044     ASCOT2E_DTV_DVBT2_6,
0045     ASCOT2E_DTV_DVBT2_7,
0046     ASCOT2E_DTV_DVBT2_8,
0047     ASCOT2E_DTV_DVBC_6,
0048     ASCOT2E_DTV_DVBC_8,
0049     ASCOT2E_DTV_DVBC2_6,
0050     ASCOT2E_DTV_DVBC2_8,
0051     ASCOT2E_DTV_UNKNOWN
0052 };
0053 
0054 struct ascot2e_band_sett {
0055     u8  if_out_sel;
0056     u8  agc_sel;
0057     u8  mix_oll;
0058     u8  rf_gain;
0059     u8  if_bpf_gc;
0060     u8  fif_offset;
0061     u8  bw_offset;
0062     u8  bw;
0063     u8  rf_oldet;
0064     u8  if_bpf_f0;
0065 };
0066 
0067 #define ASCOT2E_AUTO        0xff
0068 #define ASCOT2E_OFFSET(ofs) ((u8)(ofs) & 0x1F)
0069 #define ASCOT2E_BW_6        0x00
0070 #define ASCOT2E_BW_7        0x01
0071 #define ASCOT2E_BW_8        0x02
0072 #define ASCOT2E_BW_1_7      0x03
0073 
0074 static struct ascot2e_band_sett ascot2e_sett[] = {
0075     { ASCOT2E_AUTO, ASCOT2E_AUTO, 0x03, ASCOT2E_AUTO, 0x06,
0076       ASCOT2E_OFFSET(-8), ASCOT2E_OFFSET(-6), ASCOT2E_BW_6,  0x0B, 0x00 },
0077     { ASCOT2E_AUTO, ASCOT2E_AUTO, 0x03, ASCOT2E_AUTO, 0x06,
0078       ASCOT2E_OFFSET(-8), ASCOT2E_OFFSET(-6), ASCOT2E_BW_6,  0x0B, 0x00 },
0079     { ASCOT2E_AUTO, ASCOT2E_AUTO, 0x03, ASCOT2E_AUTO, 0x06,
0080       ASCOT2E_OFFSET(-6), ASCOT2E_OFFSET(-4), ASCOT2E_BW_7,  0x0B, 0x00 },
0081     { ASCOT2E_AUTO, ASCOT2E_AUTO, 0x03, ASCOT2E_AUTO, 0x06,
0082       ASCOT2E_OFFSET(-4), ASCOT2E_OFFSET(-2), ASCOT2E_BW_8,  0x0B, 0x00 },
0083     { ASCOT2E_AUTO, ASCOT2E_AUTO, 0x03, ASCOT2E_AUTO, 0x06,
0084     ASCOT2E_OFFSET(-10), ASCOT2E_OFFSET(-16), ASCOT2E_BW_1_7, 0x0B, 0x00 },
0085     { ASCOT2E_AUTO, ASCOT2E_AUTO, 0x03, ASCOT2E_AUTO, 0x06,
0086       ASCOT2E_OFFSET(-8), ASCOT2E_OFFSET(-6), ASCOT2E_BW_6,  0x0B, 0x00 },
0087     { ASCOT2E_AUTO, ASCOT2E_AUTO, 0x03, ASCOT2E_AUTO, 0x06,
0088       ASCOT2E_OFFSET(-8), ASCOT2E_OFFSET(-6), ASCOT2E_BW_6,  0x0B, 0x00 },
0089     { ASCOT2E_AUTO, ASCOT2E_AUTO, 0x03, ASCOT2E_AUTO, 0x06,
0090       ASCOT2E_OFFSET(-6), ASCOT2E_OFFSET(-4), ASCOT2E_BW_7,  0x0B, 0x00 },
0091     { ASCOT2E_AUTO, ASCOT2E_AUTO, 0x03, ASCOT2E_AUTO, 0x06,
0092       ASCOT2E_OFFSET(-4), ASCOT2E_OFFSET(-2), ASCOT2E_BW_8,  0x0B, 0x00 },
0093     { ASCOT2E_AUTO, ASCOT2E_AUTO, 0x02, ASCOT2E_AUTO, 0x03,
0094       ASCOT2E_OFFSET(-6), ASCOT2E_OFFSET(-8), ASCOT2E_BW_6,  0x09, 0x00 },
0095     { ASCOT2E_AUTO, ASCOT2E_AUTO, 0x02, ASCOT2E_AUTO, 0x03,
0096       ASCOT2E_OFFSET(-2), ASCOT2E_OFFSET(-1), ASCOT2E_BW_8,  0x09, 0x00 },
0097     { ASCOT2E_AUTO, ASCOT2E_AUTO, 0x03, ASCOT2E_AUTO, 0x01,
0098       ASCOT2E_OFFSET(-6), ASCOT2E_OFFSET(-4), ASCOT2E_BW_6,  0x09, 0x00 },
0099     { ASCOT2E_AUTO, ASCOT2E_AUTO, 0x03, ASCOT2E_AUTO, 0x01,
0100       ASCOT2E_OFFSET(-2), ASCOT2E_OFFSET(2),  ASCOT2E_BW_8,  0x09, 0x00 }
0101 };
0102 
0103 static void ascot2e_i2c_debug(struct ascot2e_priv *priv,
0104                   u8 reg, u8 write, const u8 *data, u32 len)
0105 {
0106     dev_dbg(&priv->i2c->dev, "ascot2e: I2C %s reg 0x%02x size %d\n",
0107         (write == 0 ? "read" : "write"), reg, len);
0108     print_hex_dump_bytes("ascot2e: I2C data: ",
0109         DUMP_PREFIX_OFFSET, data, len);
0110 }
0111 
0112 static int ascot2e_write_regs(struct ascot2e_priv *priv,
0113                   u8 reg, const u8 *data, u32 len)
0114 {
0115     int ret;
0116     u8 buf[MAX_WRITE_REGSIZE + 1];
0117     struct i2c_msg msg[1] = {
0118         {
0119             .addr = priv->i2c_address,
0120             .flags = 0,
0121             .len = len + 1,
0122             .buf = buf,
0123         }
0124     };
0125 
0126     if (len + 1 > sizeof(buf)) {
0127         dev_warn(&priv->i2c->dev,"wr reg=%04x: len=%d is too big!\n",
0128              reg, len + 1);
0129         return -E2BIG;
0130     }
0131 
0132     ascot2e_i2c_debug(priv, reg, 1, data, len);
0133     buf[0] = reg;
0134     memcpy(&buf[1], data, len);
0135     ret = i2c_transfer(priv->i2c, msg, 1);
0136     if (ret >= 0 && ret != 1)
0137         ret = -EREMOTEIO;
0138     if (ret < 0) {
0139         dev_warn(&priv->i2c->dev,
0140             "%s: i2c wr failed=%d reg=%02x len=%d\n",
0141             KBUILD_MODNAME, ret, reg, len);
0142         return ret;
0143     }
0144     return 0;
0145 }
0146 
0147 static int ascot2e_write_reg(struct ascot2e_priv *priv, u8 reg, u8 val)
0148 {
0149     u8 tmp = val; /* see gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */
0150 
0151     return ascot2e_write_regs(priv, reg, &tmp, 1);
0152 }
0153 
0154 static int ascot2e_read_regs(struct ascot2e_priv *priv,
0155                  u8 reg, u8 *val, u32 len)
0156 {
0157     int ret;
0158     struct i2c_msg msg[2] = {
0159         {
0160             .addr = priv->i2c_address,
0161             .flags = 0,
0162             .len = 1,
0163             .buf = &reg,
0164         }, {
0165             .addr = priv->i2c_address,
0166             .flags = I2C_M_RD,
0167             .len = len,
0168             .buf = val,
0169         }
0170     };
0171 
0172     ret = i2c_transfer(priv->i2c, &msg[0], 1);
0173     if (ret >= 0 && ret != 1)
0174         ret = -EREMOTEIO;
0175     if (ret < 0) {
0176         dev_warn(&priv->i2c->dev,
0177             "%s: I2C rw failed=%d addr=%02x reg=%02x\n",
0178             KBUILD_MODNAME, ret, priv->i2c_address, reg);
0179         return ret;
0180     }
0181     ret = i2c_transfer(priv->i2c, &msg[1], 1);
0182     if (ret >= 0 && ret != 1)
0183         ret = -EREMOTEIO;
0184     if (ret < 0) {
0185         dev_warn(&priv->i2c->dev,
0186             "%s: i2c rd failed=%d addr=%02x reg=%02x\n",
0187             KBUILD_MODNAME, ret, priv->i2c_address, reg);
0188         return ret;
0189     }
0190     ascot2e_i2c_debug(priv, reg, 0, val, len);
0191     return 0;
0192 }
0193 
0194 static int ascot2e_read_reg(struct ascot2e_priv *priv, u8 reg, u8 *val)
0195 {
0196     return ascot2e_read_regs(priv, reg, val, 1);
0197 }
0198 
0199 static int ascot2e_set_reg_bits(struct ascot2e_priv *priv,
0200                 u8 reg, u8 data, u8 mask)
0201 {
0202     int res;
0203     u8 rdata;
0204 
0205     if (mask != 0xff) {
0206         res = ascot2e_read_reg(priv, reg, &rdata);
0207         if (res != 0)
0208             return res;
0209         data = ((data & mask) | (rdata & (mask ^ 0xFF)));
0210     }
0211     return ascot2e_write_reg(priv, reg, data);
0212 }
0213 
0214 static int ascot2e_enter_power_save(struct ascot2e_priv *priv)
0215 {
0216     u8 data[2];
0217 
0218     dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
0219     if (priv->state == STATE_SLEEP)
0220         return 0;
0221     data[0] = 0x00;
0222     data[1] = 0x04;
0223     ascot2e_write_regs(priv, 0x14, data, 2);
0224     ascot2e_write_reg(priv, 0x50, 0x01);
0225     priv->state = STATE_SLEEP;
0226     return 0;
0227 }
0228 
0229 static int ascot2e_leave_power_save(struct ascot2e_priv *priv)
0230 {
0231     u8 data[2] = { 0xFB, 0x0F };
0232 
0233     dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
0234     if (priv->state == STATE_ACTIVE)
0235         return 0;
0236     ascot2e_write_regs(priv, 0x14, data, 2);
0237     ascot2e_write_reg(priv, 0x50, 0x00);
0238     priv->state = STATE_ACTIVE;
0239     return 0;
0240 }
0241 
0242 static int ascot2e_init(struct dvb_frontend *fe)
0243 {
0244     struct ascot2e_priv *priv = fe->tuner_priv;
0245 
0246     dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
0247     return ascot2e_leave_power_save(priv);
0248 }
0249 
0250 static void ascot2e_release(struct dvb_frontend *fe)
0251 {
0252     struct ascot2e_priv *priv = fe->tuner_priv;
0253 
0254     dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
0255     kfree(fe->tuner_priv);
0256     fe->tuner_priv = NULL;
0257 }
0258 
0259 static int ascot2e_sleep(struct dvb_frontend *fe)
0260 {
0261     struct ascot2e_priv *priv = fe->tuner_priv;
0262 
0263     dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
0264     ascot2e_enter_power_save(priv);
0265     return 0;
0266 }
0267 
0268 static enum ascot2e_tv_system_t ascot2e_get_tv_system(struct dvb_frontend *fe)
0269 {
0270     enum ascot2e_tv_system_t system = ASCOT2E_DTV_UNKNOWN;
0271     struct dtv_frontend_properties *p = &fe->dtv_property_cache;
0272     struct ascot2e_priv *priv = fe->tuner_priv;
0273 
0274     if (p->delivery_system == SYS_DVBT) {
0275         if (p->bandwidth_hz <= 5000000)
0276             system = ASCOT2E_DTV_DVBT_5;
0277         else if (p->bandwidth_hz <= 6000000)
0278             system = ASCOT2E_DTV_DVBT_6;
0279         else if (p->bandwidth_hz <= 7000000)
0280             system = ASCOT2E_DTV_DVBT_7;
0281         else if (p->bandwidth_hz <= 8000000)
0282             system = ASCOT2E_DTV_DVBT_8;
0283         else {
0284             system = ASCOT2E_DTV_DVBT_8;
0285             p->bandwidth_hz = 8000000;
0286         }
0287     } else if (p->delivery_system == SYS_DVBT2) {
0288         if (p->bandwidth_hz <= 5000000)
0289             system = ASCOT2E_DTV_DVBT2_5;
0290         else if (p->bandwidth_hz <= 6000000)
0291             system = ASCOT2E_DTV_DVBT2_6;
0292         else if (p->bandwidth_hz <= 7000000)
0293             system = ASCOT2E_DTV_DVBT2_7;
0294         else if (p->bandwidth_hz <= 8000000)
0295             system = ASCOT2E_DTV_DVBT2_8;
0296         else {
0297             system = ASCOT2E_DTV_DVBT2_8;
0298             p->bandwidth_hz = 8000000;
0299         }
0300     } else if (p->delivery_system == SYS_DVBC_ANNEX_A) {
0301         if (p->bandwidth_hz <= 6000000)
0302             system = ASCOT2E_DTV_DVBC_6;
0303         else if (p->bandwidth_hz <= 8000000)
0304             system = ASCOT2E_DTV_DVBC_8;
0305     }
0306     dev_dbg(&priv->i2c->dev,
0307         "%s(): ASCOT2E DTV system %d (delsys %d, bandwidth %d)\n",
0308         __func__, (int)system, p->delivery_system, p->bandwidth_hz);
0309     return system;
0310 }
0311 
0312 static int ascot2e_set_params(struct dvb_frontend *fe)
0313 {
0314     u8 data[10];
0315     u32 frequency;
0316     enum ascot2e_tv_system_t tv_system;
0317     struct dtv_frontend_properties *p = &fe->dtv_property_cache;
0318     struct ascot2e_priv *priv = fe->tuner_priv;
0319 
0320     dev_dbg(&priv->i2c->dev, "%s(): tune frequency %dkHz\n",
0321         __func__, p->frequency / 1000);
0322     tv_system = ascot2e_get_tv_system(fe);
0323 
0324     if (tv_system == ASCOT2E_DTV_UNKNOWN) {
0325         dev_dbg(&priv->i2c->dev, "%s(): unknown DTV system\n",
0326             __func__);
0327         return -EINVAL;
0328     }
0329     if (priv->set_tuner)
0330         priv->set_tuner(priv->set_tuner_data, 1);
0331     frequency = roundup(p->frequency / 1000, 25);
0332     if (priv->state == STATE_SLEEP)
0333         ascot2e_leave_power_save(priv);
0334 
0335     /* IF_OUT_SEL / AGC_SEL setting */
0336     data[0] = 0x00;
0337     if (ascot2e_sett[tv_system].agc_sel != ASCOT2E_AUTO) {
0338         /* AGC pin setting from parameter table */
0339         data[0] |= (u8)(
0340             (ascot2e_sett[tv_system].agc_sel & 0x03) << 3);
0341     }
0342     if (ascot2e_sett[tv_system].if_out_sel != ASCOT2E_AUTO) {
0343         /* IFOUT pin setting from parameter table */
0344         data[0] |= (u8)(
0345             (ascot2e_sett[tv_system].if_out_sel & 0x01) << 2);
0346     }
0347     /* Set bit[4:2] only */
0348     ascot2e_set_reg_bits(priv, 0x05, data[0], 0x1c);
0349     /* 0x06 - 0x0F */
0350     /* REF_R setting (0x06) */
0351     if (tv_system == ASCOT2E_DTV_DVBC_6 ||
0352             tv_system == ASCOT2E_DTV_DVBC_8) {
0353         /* xtal, xtal*2 */
0354         data[0] = (frequency > 500000) ? 16 : 32;
0355     } else {
0356         /* xtal/8, xtal/4 */
0357         data[0] = (frequency > 500000) ? 2 : 4;
0358     }
0359     /* XOSC_SEL=100uA */
0360     data[1] = 0x04;
0361     /* KBW setting (0x08), KC0 setting (0x09), KC1 setting (0x0A) */
0362     if (tv_system == ASCOT2E_DTV_DVBC_6 ||
0363             tv_system == ASCOT2E_DTV_DVBC_8) {
0364         data[2] = 18;
0365         data[3] = 120;
0366         data[4] = 20;
0367     } else {
0368         data[2] = 48;
0369         data[3] = 10;
0370         data[4] = 30;
0371     }
0372     /* ORDER/R2_RANGE/R2_BANK/C2_BANK setting (0x0B) */
0373     if (tv_system == ASCOT2E_DTV_DVBC_6 ||
0374             tv_system == ASCOT2E_DTV_DVBC_8)
0375         data[5] = (frequency > 500000) ? 0x08 : 0x0c;
0376     else
0377         data[5] = (frequency > 500000) ? 0x30 : 0x38;
0378     /* Set MIX_OLL (0x0C) value from parameter table */
0379     data[6] = ascot2e_sett[tv_system].mix_oll;
0380     /* Set RF_GAIN (0x0D) setting from parameter table */
0381     if (ascot2e_sett[tv_system].rf_gain == ASCOT2E_AUTO) {
0382         /* RF_GAIN auto control enable */
0383         ascot2e_write_reg(priv, 0x4E, 0x01);
0384         /* RF_GAIN Default value */
0385         data[7] = 0x00;
0386     } else {
0387         /* RF_GAIN auto control disable */
0388         ascot2e_write_reg(priv, 0x4E, 0x00);
0389         data[7] = ascot2e_sett[tv_system].rf_gain;
0390     }
0391     /* Set IF_BPF_GC/FIF_OFFSET (0x0E) value from parameter table */
0392     data[8] = (u8)((ascot2e_sett[tv_system].fif_offset << 3) |
0393         (ascot2e_sett[tv_system].if_bpf_gc & 0x07));
0394     /* Set BW_OFFSET (0x0F) value from parameter table */
0395     data[9] = ascot2e_sett[tv_system].bw_offset;
0396     ascot2e_write_regs(priv, 0x06, data, 10);
0397     /*
0398      * 0x45 - 0x47
0399      * LNA optimization setting
0400      * RF_LNA_DIST1-5, RF_LNA_CM
0401      */
0402     if (tv_system == ASCOT2E_DTV_DVBC_6 ||
0403             tv_system == ASCOT2E_DTV_DVBC_8) {
0404         data[0] = 0x0F;
0405         data[1] = 0x00;
0406         data[2] = 0x01;
0407     } else {
0408         data[0] = 0x0F;
0409         data[1] = 0x00;
0410         data[2] = 0x03;
0411     }
0412     ascot2e_write_regs(priv, 0x45, data, 3);
0413     /* 0x49 - 0x4A
0414      Set RF_OLDET_ENX/RF_OLDET_OLL value from parameter table */
0415     data[0] = ascot2e_sett[tv_system].rf_oldet;
0416     /* Set IF_BPF_F0 value from parameter table */
0417     data[1] = ascot2e_sett[tv_system].if_bpf_f0;
0418     ascot2e_write_regs(priv, 0x49, data, 2);
0419     /*
0420      * Tune now
0421      * RFAGC fast mode / RFAGC auto control enable
0422      * (set bit[7], bit[5:4] only)
0423      * vco_cal = 1, set MIX_OL_CPU_EN
0424      */
0425     ascot2e_set_reg_bits(priv, 0x0c, 0x90, 0xb0);
0426     /* Logic wake up, CPU wake up */
0427     data[0] = 0xc4;
0428     data[1] = 0x40;
0429     ascot2e_write_regs(priv, 0x03, data, 2);
0430     /* 0x10 - 0x14 */
0431     data[0] = (u8)(frequency & 0xFF);         /* 0x10: FRF_L */
0432     data[1] = (u8)((frequency >> 8) & 0xFF);  /* 0x11: FRF_M */
0433     data[2] = (u8)((frequency >> 16) & 0x0F); /* 0x12: FRF_H (bit[3:0]) */
0434     /* 0x12: BW (bit[5:4]) */
0435     data[2] |= (u8)(ascot2e_sett[tv_system].bw << 4);
0436     data[3] = 0xFF; /* 0x13: VCO calibration enable */
0437     data[4] = 0xFF; /* 0x14: Analog block enable */
0438     /* Tune (Burst write) */
0439     ascot2e_write_regs(priv, 0x10, data, 5);
0440     msleep(50);
0441     /* CPU deep sleep */
0442     ascot2e_write_reg(priv, 0x04, 0x00);
0443     /* Logic sleep */
0444     ascot2e_write_reg(priv, 0x03, 0xC0);
0445     /* RFAGC normal mode (set bit[5:4] only) */
0446     ascot2e_set_reg_bits(priv, 0x0C, 0x00, 0x30);
0447     priv->frequency = frequency;
0448     return 0;
0449 }
0450 
0451 static int ascot2e_get_frequency(struct dvb_frontend *fe, u32 *frequency)
0452 {
0453     struct ascot2e_priv *priv = fe->tuner_priv;
0454 
0455     *frequency = priv->frequency * 1000;
0456     return 0;
0457 }
0458 
0459 static const struct dvb_tuner_ops ascot2e_tuner_ops = {
0460     .info = {
0461         .name = "Sony ASCOT2E",
0462         .frequency_min_hz  =    1 * MHz,
0463         .frequency_max_hz  = 1200 * MHz,
0464         .frequency_step_hz =   25 * kHz,
0465     },
0466     .init = ascot2e_init,
0467     .release = ascot2e_release,
0468     .sleep = ascot2e_sleep,
0469     .set_params = ascot2e_set_params,
0470     .get_frequency = ascot2e_get_frequency,
0471 };
0472 
0473 struct dvb_frontend *ascot2e_attach(struct dvb_frontend *fe,
0474                     const struct ascot2e_config *config,
0475                     struct i2c_adapter *i2c)
0476 {
0477     u8 data[4];
0478     struct ascot2e_priv *priv = NULL;
0479 
0480     priv = kzalloc(sizeof(struct ascot2e_priv), GFP_KERNEL);
0481     if (priv == NULL)
0482         return NULL;
0483     priv->i2c_address = (config->i2c_address >> 1);
0484     priv->i2c = i2c;
0485     priv->set_tuner_data = config->set_tuner_priv;
0486     priv->set_tuner = config->set_tuner_callback;
0487 
0488     if (fe->ops.i2c_gate_ctrl)
0489         fe->ops.i2c_gate_ctrl(fe, 1);
0490 
0491     /* 16 MHz xTal frequency */
0492     data[0] = 16;
0493     /* VCO current setting */
0494     data[1] = 0x06;
0495     /* Logic wake up, CPU boot */
0496     data[2] = 0xC4;
0497     data[3] = 0x40;
0498     ascot2e_write_regs(priv, 0x01, data, 4);
0499     /* RFVGA optimization setting (RF_DIST0 - RF_DIST2) */
0500     data[0] = 0x10;
0501     data[1] = 0x3F;
0502     data[2] = 0x25;
0503     ascot2e_write_regs(priv, 0x22, data, 3);
0504     /* PLL mode setting */
0505     ascot2e_write_reg(priv, 0x28, 0x1e);
0506     /* RSSI setting */
0507     ascot2e_write_reg(priv, 0x59, 0x04);
0508     /* TODO check CPU HW error state here */
0509     msleep(80);
0510     /* Xtal oscillator current control setting */
0511     ascot2e_write_reg(priv, 0x4c, 0x01);
0512     /* XOSC_SEL=100uA */
0513     ascot2e_write_reg(priv, 0x07, 0x04);
0514     /* CPU deep sleep */
0515     ascot2e_write_reg(priv, 0x04, 0x00);
0516     /* Logic sleep */
0517     ascot2e_write_reg(priv, 0x03, 0xc0);
0518     /* Power save setting */
0519     data[0] = 0x00;
0520     data[1] = 0x04;
0521     ascot2e_write_regs(priv, 0x14, data, 2);
0522     ascot2e_write_reg(priv, 0x50, 0x01);
0523     priv->state = STATE_SLEEP;
0524 
0525     if (fe->ops.i2c_gate_ctrl)
0526         fe->ops.i2c_gate_ctrl(fe, 0);
0527 
0528     memcpy(&fe->ops.tuner_ops, &ascot2e_tuner_ops,
0529                 sizeof(struct dvb_tuner_ops));
0530     fe->tuner_priv = priv;
0531     dev_info(&priv->i2c->dev,
0532         "Sony ASCOT2E attached on addr=%x at I2C adapter %p\n",
0533         priv->i2c_address, priv->i2c);
0534     return fe;
0535 }
0536 EXPORT_SYMBOL(ascot2e_attach);
0537 
0538 MODULE_DESCRIPTION("Sony ASCOT2E terr/cab tuner driver");
0539 MODULE_AUTHOR("info@netup.ru");
0540 MODULE_LICENSE("GPL");
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