Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Afatech AF9033 demodulator driver
0004  *
0005  * Copyright (C) 2009 Antti Palosaari <crope@iki.fi>
0006  * Copyright (C) 2012 Antti Palosaari <crope@iki.fi>
0007  */
0008 
0009 #include "af9033_priv.h"
0010 
0011 struct af9033_dev {
0012     struct i2c_client *client;
0013     struct regmap *regmap;
0014     struct dvb_frontend fe;
0015     struct af9033_config cfg;
0016     bool is_af9035;
0017     bool is_it9135;
0018 
0019     u32 bandwidth_hz;
0020     bool ts_mode_parallel;
0021     bool ts_mode_serial;
0022 
0023     enum fe_status fe_status;
0024     u64 post_bit_error_prev; /* for old read_ber we return (curr - prev) */
0025     u64 post_bit_error;
0026     u64 post_bit_count;
0027     u64 error_block_count;
0028     u64 total_block_count;
0029 };
0030 
0031 /* Write reg val table using reg addr auto increment */
0032 static int af9033_wr_reg_val_tab(struct af9033_dev *dev,
0033                  const struct reg_val *tab, int tab_len)
0034 {
0035     struct i2c_client *client = dev->client;
0036 #define MAX_TAB_LEN 212
0037     int ret, i, j;
0038     u8 buf[1 + MAX_TAB_LEN];
0039 
0040     dev_dbg(&client->dev, "tab_len=%d\n", tab_len);
0041 
0042     if (tab_len > sizeof(buf)) {
0043         dev_warn(&client->dev, "tab len %d is too big\n", tab_len);
0044         return -EINVAL;
0045     }
0046 
0047     for (i = 0, j = 0; i < tab_len; i++) {
0048         buf[j] = tab[i].val;
0049 
0050         if (i == tab_len - 1 || tab[i].reg != tab[i + 1].reg - 1) {
0051             ret = regmap_bulk_write(dev->regmap, tab[i].reg - j,
0052                         buf, j + 1);
0053             if (ret)
0054                 goto err;
0055 
0056             j = 0;
0057         } else {
0058             j++;
0059         }
0060     }
0061 
0062     return 0;
0063 err:
0064     dev_dbg(&client->dev, "failed=%d\n", ret);
0065     return ret;
0066 }
0067 
0068 static int af9033_init(struct dvb_frontend *fe)
0069 {
0070     struct af9033_dev *dev = fe->demodulator_priv;
0071     struct i2c_client *client = dev->client;
0072     struct dtv_frontend_properties *c = &fe->dtv_property_cache;
0073     int ret, i, len;
0074     unsigned int utmp;
0075     const struct reg_val *init;
0076     u8 buf[4];
0077     struct reg_val_mask tab[] = {
0078         { 0x80fb24, 0x00, 0x08 },
0079         { 0x80004c, 0x00, 0xff },
0080         { 0x00f641, dev->cfg.tuner, 0xff },
0081         { 0x80f5ca, 0x01, 0x01 },
0082         { 0x80f715, 0x01, 0x01 },
0083         { 0x00f41f, 0x04, 0x04 },
0084         { 0x00f41a, 0x01, 0x01 },
0085         { 0x80f731, 0x00, 0x01 },
0086         { 0x00d91e, 0x00, 0x01 },
0087         { 0x00d919, 0x00, 0x01 },
0088         { 0x80f732, 0x00, 0x01 },
0089         { 0x00d91f, 0x00, 0x01 },
0090         { 0x00d91a, 0x00, 0x01 },
0091         { 0x80f730, 0x00, 0x01 },
0092         { 0x80f778, 0x00, 0xff },
0093         { 0x80f73c, 0x01, 0x01 },
0094         { 0x80f776, 0x00, 0x01 },
0095         { 0x00d8fd, 0x01, 0xff },
0096         { 0x00d830, 0x01, 0xff },
0097         { 0x00d831, 0x00, 0xff },
0098         { 0x00d832, 0x00, 0xff },
0099         { 0x80f985, dev->ts_mode_serial, 0x01 },
0100         { 0x80f986, dev->ts_mode_parallel, 0x01 },
0101         { 0x00d827, 0x00, 0xff },
0102         { 0x00d829, 0x00, 0xff },
0103         { 0x800045, dev->cfg.adc_multiplier, 0xff },
0104     };
0105 
0106     dev_dbg(&client->dev, "\n");
0107 
0108     /* Main clk control */
0109     utmp = div_u64((u64)dev->cfg.clock * 0x80000, 1000000);
0110     buf[0] = (utmp >>  0) & 0xff;
0111     buf[1] = (utmp >>  8) & 0xff;
0112     buf[2] = (utmp >> 16) & 0xff;
0113     buf[3] = (utmp >> 24) & 0xff;
0114     ret = regmap_bulk_write(dev->regmap, 0x800025, buf, 4);
0115     if (ret)
0116         goto err;
0117 
0118     dev_dbg(&client->dev, "clk=%u clk_cw=%08x\n", dev->cfg.clock, utmp);
0119 
0120     /* ADC clk control */
0121     for (i = 0; i < ARRAY_SIZE(clock_adc_lut); i++) {
0122         if (clock_adc_lut[i].clock == dev->cfg.clock)
0123             break;
0124     }
0125     if (i == ARRAY_SIZE(clock_adc_lut)) {
0126         dev_err(&client->dev, "Couldn't find ADC config for clock %d\n",
0127             dev->cfg.clock);
0128         ret = -ENODEV;
0129         goto err;
0130     }
0131 
0132     utmp = div_u64((u64)clock_adc_lut[i].adc * 0x80000, 1000000);
0133     buf[0] = (utmp >>  0) & 0xff;
0134     buf[1] = (utmp >>  8) & 0xff;
0135     buf[2] = (utmp >> 16) & 0xff;
0136     ret = regmap_bulk_write(dev->regmap, 0x80f1cd, buf, 3);
0137     if (ret)
0138         goto err;
0139 
0140     dev_dbg(&client->dev, "adc=%u adc_cw=%06x\n",
0141         clock_adc_lut[i].adc, utmp);
0142 
0143     /* Config register table */
0144     for (i = 0; i < ARRAY_SIZE(tab); i++) {
0145         ret = regmap_update_bits(dev->regmap, tab[i].reg, tab[i].mask,
0146                      tab[i].val);
0147         if (ret)
0148             goto err;
0149     }
0150 
0151     /* Demod clk output */
0152     if (dev->cfg.dyn0_clk) {
0153         ret = regmap_write(dev->regmap, 0x80fba8, 0x00);
0154         if (ret)
0155             goto err;
0156     }
0157 
0158     /* TS interface */
0159     if (dev->cfg.ts_mode == AF9033_TS_MODE_USB) {
0160         ret = regmap_update_bits(dev->regmap, 0x80f9a5, 0x01, 0x00);
0161         if (ret)
0162             goto err;
0163         ret = regmap_update_bits(dev->regmap, 0x80f9b5, 0x01, 0x01);
0164         if (ret)
0165             goto err;
0166     } else {
0167         ret = regmap_update_bits(dev->regmap, 0x80f990, 0x01, 0x00);
0168         if (ret)
0169             goto err;
0170         ret = regmap_update_bits(dev->regmap, 0x80f9b5, 0x01, 0x00);
0171         if (ret)
0172             goto err;
0173     }
0174 
0175     /* Demod core settings */
0176     dev_dbg(&client->dev, "load ofsm settings\n");
0177     switch (dev->cfg.tuner) {
0178     case AF9033_TUNER_IT9135_38:
0179     case AF9033_TUNER_IT9135_51:
0180     case AF9033_TUNER_IT9135_52:
0181         len = ARRAY_SIZE(ofsm_init_it9135_v1);
0182         init = ofsm_init_it9135_v1;
0183         break;
0184     case AF9033_TUNER_IT9135_60:
0185     case AF9033_TUNER_IT9135_61:
0186     case AF9033_TUNER_IT9135_62:
0187         len = ARRAY_SIZE(ofsm_init_it9135_v2);
0188         init = ofsm_init_it9135_v2;
0189         break;
0190     default:
0191         len = ARRAY_SIZE(ofsm_init);
0192         init = ofsm_init;
0193         break;
0194     }
0195 
0196     ret = af9033_wr_reg_val_tab(dev, init, len);
0197     if (ret)
0198         goto err;
0199 
0200     /* Demod tuner specific settings */
0201     dev_dbg(&client->dev, "load tuner specific settings\n");
0202     switch (dev->cfg.tuner) {
0203     case AF9033_TUNER_TUA9001:
0204         len = ARRAY_SIZE(tuner_init_tua9001);
0205         init = tuner_init_tua9001;
0206         break;
0207     case AF9033_TUNER_FC0011:
0208         len = ARRAY_SIZE(tuner_init_fc0011);
0209         init = tuner_init_fc0011;
0210         break;
0211     case AF9033_TUNER_MXL5007T:
0212         len = ARRAY_SIZE(tuner_init_mxl5007t);
0213         init = tuner_init_mxl5007t;
0214         break;
0215     case AF9033_TUNER_TDA18218:
0216         len = ARRAY_SIZE(tuner_init_tda18218);
0217         init = tuner_init_tda18218;
0218         break;
0219     case AF9033_TUNER_FC2580:
0220         len = ARRAY_SIZE(tuner_init_fc2580);
0221         init = tuner_init_fc2580;
0222         break;
0223     case AF9033_TUNER_FC0012:
0224         len = ARRAY_SIZE(tuner_init_fc0012);
0225         init = tuner_init_fc0012;
0226         break;
0227     case AF9033_TUNER_IT9135_38:
0228         len = ARRAY_SIZE(tuner_init_it9135_38);
0229         init = tuner_init_it9135_38;
0230         break;
0231     case AF9033_TUNER_IT9135_51:
0232         len = ARRAY_SIZE(tuner_init_it9135_51);
0233         init = tuner_init_it9135_51;
0234         break;
0235     case AF9033_TUNER_IT9135_52:
0236         len = ARRAY_SIZE(tuner_init_it9135_52);
0237         init = tuner_init_it9135_52;
0238         break;
0239     case AF9033_TUNER_IT9135_60:
0240         len = ARRAY_SIZE(tuner_init_it9135_60);
0241         init = tuner_init_it9135_60;
0242         break;
0243     case AF9033_TUNER_IT9135_61:
0244         len = ARRAY_SIZE(tuner_init_it9135_61);
0245         init = tuner_init_it9135_61;
0246         break;
0247     case AF9033_TUNER_IT9135_62:
0248         len = ARRAY_SIZE(tuner_init_it9135_62);
0249         init = tuner_init_it9135_62;
0250         break;
0251     default:
0252         dev_dbg(&client->dev, "unsupported tuner ID=%d\n",
0253             dev->cfg.tuner);
0254         ret = -ENODEV;
0255         goto err;
0256     }
0257 
0258     ret = af9033_wr_reg_val_tab(dev, init, len);
0259     if (ret)
0260         goto err;
0261 
0262     if (dev->cfg.ts_mode == AF9033_TS_MODE_SERIAL) {
0263         ret = regmap_update_bits(dev->regmap, 0x00d91c, 0x01, 0x01);
0264         if (ret)
0265             goto err;
0266         ret = regmap_update_bits(dev->regmap, 0x00d917, 0x01, 0x00);
0267         if (ret)
0268             goto err;
0269         ret = regmap_update_bits(dev->regmap, 0x00d916, 0x01, 0x00);
0270         if (ret)
0271             goto err;
0272     }
0273 
0274     switch (dev->cfg.tuner) {
0275     case AF9033_TUNER_IT9135_60:
0276     case AF9033_TUNER_IT9135_61:
0277     case AF9033_TUNER_IT9135_62:
0278         ret = regmap_write(dev->regmap, 0x800000, 0x01);
0279         if (ret)
0280             goto err;
0281     }
0282 
0283     dev->bandwidth_hz = 0; /* Force to program all parameters */
0284     /* Init stats here in order signal app which stats are supported */
0285     c->strength.len = 1;
0286     c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
0287     c->cnr.len = 1;
0288     c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
0289     c->block_count.len = 1;
0290     c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
0291     c->block_error.len = 1;
0292     c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
0293     c->post_bit_count.len = 1;
0294     c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
0295     c->post_bit_error.len = 1;
0296     c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
0297 
0298     return 0;
0299 err:
0300     dev_dbg(&client->dev, "failed=%d\n", ret);
0301     return ret;
0302 }
0303 
0304 static int af9033_sleep(struct dvb_frontend *fe)
0305 {
0306     struct af9033_dev *dev = fe->demodulator_priv;
0307     struct i2c_client *client = dev->client;
0308     int ret;
0309     unsigned int utmp;
0310 
0311     dev_dbg(&client->dev, "\n");
0312 
0313     ret = regmap_write(dev->regmap, 0x80004c, 0x01);
0314     if (ret)
0315         goto err;
0316     ret = regmap_write(dev->regmap, 0x800000, 0x00);
0317     if (ret)
0318         goto err;
0319     ret = regmap_read_poll_timeout(dev->regmap, 0x80004c, utmp, utmp == 0,
0320                        5000, 1000000);
0321     if (ret)
0322         goto err;
0323     ret = regmap_update_bits(dev->regmap, 0x80fb24, 0x08, 0x08);
0324     if (ret)
0325         goto err;
0326 
0327     /* Prevent current leak by setting TS interface to parallel mode */
0328     if (dev->cfg.ts_mode == AF9033_TS_MODE_SERIAL) {
0329         /* Enable parallel TS */
0330         ret = regmap_update_bits(dev->regmap, 0x00d917, 0x01, 0x00);
0331         if (ret)
0332             goto err;
0333         ret = regmap_update_bits(dev->regmap, 0x00d916, 0x01, 0x01);
0334         if (ret)
0335             goto err;
0336     }
0337 
0338     return 0;
0339 err:
0340     dev_dbg(&client->dev, "failed=%d\n", ret);
0341     return ret;
0342 }
0343 
0344 static int af9033_get_tune_settings(struct dvb_frontend *fe,
0345                     struct dvb_frontend_tune_settings *fesettings)
0346 {
0347     /* 800 => 2000 because IT9135 v2 is slow to gain lock */
0348     fesettings->min_delay_ms = 2000;
0349     fesettings->step_size = 0;
0350     fesettings->max_drift = 0;
0351 
0352     return 0;
0353 }
0354 
0355 static int af9033_set_frontend(struct dvb_frontend *fe)
0356 {
0357     struct af9033_dev *dev = fe->demodulator_priv;
0358     struct i2c_client *client = dev->client;
0359     struct dtv_frontend_properties *c = &fe->dtv_property_cache;
0360     int ret, i;
0361     unsigned int utmp, adc_freq;
0362     u8 tmp, buf[3], bandwidth_reg_val;
0363     u32 if_frequency;
0364 
0365     dev_dbg(&client->dev, "frequency=%u bandwidth_hz=%u\n",
0366         c->frequency, c->bandwidth_hz);
0367 
0368     /* Check bandwidth */
0369     switch (c->bandwidth_hz) {
0370     case 6000000:
0371         bandwidth_reg_val = 0x00;
0372         break;
0373     case 7000000:
0374         bandwidth_reg_val = 0x01;
0375         break;
0376     case 8000000:
0377         bandwidth_reg_val = 0x02;
0378         break;
0379     default:
0380         dev_dbg(&client->dev, "invalid bandwidth_hz\n");
0381         ret = -EINVAL;
0382         goto err;
0383     }
0384 
0385     /* Program tuner */
0386     if (fe->ops.tuner_ops.set_params)
0387         fe->ops.tuner_ops.set_params(fe);
0388 
0389     /* Coefficients */
0390     if (c->bandwidth_hz != dev->bandwidth_hz) {
0391         for (i = 0; i < ARRAY_SIZE(coeff_lut); i++) {
0392             if (coeff_lut[i].clock == dev->cfg.clock &&
0393                 coeff_lut[i].bandwidth_hz == c->bandwidth_hz) {
0394                 break;
0395             }
0396         }
0397         if (i == ARRAY_SIZE(coeff_lut)) {
0398             dev_err(&client->dev,
0399                 "Couldn't find config for clock %u\n",
0400                 dev->cfg.clock);
0401             ret = -EINVAL;
0402             goto err;
0403         }
0404 
0405         ret = regmap_bulk_write(dev->regmap, 0x800001, coeff_lut[i].val,
0406                     sizeof(coeff_lut[i].val));
0407         if (ret)
0408             goto err;
0409     }
0410 
0411     /* IF frequency control */
0412     if (c->bandwidth_hz != dev->bandwidth_hz) {
0413         for (i = 0; i < ARRAY_SIZE(clock_adc_lut); i++) {
0414             if (clock_adc_lut[i].clock == dev->cfg.clock)
0415                 break;
0416         }
0417         if (i == ARRAY_SIZE(clock_adc_lut)) {
0418             dev_err(&client->dev,
0419                 "Couldn't find ADC clock for clock %u\n",
0420                 dev->cfg.clock);
0421             ret = -EINVAL;
0422             goto err;
0423         }
0424         adc_freq = clock_adc_lut[i].adc;
0425 
0426         if (dev->cfg.adc_multiplier == AF9033_ADC_MULTIPLIER_2X)
0427             adc_freq = 2 * adc_freq;
0428 
0429         /* Get used IF frequency */
0430         if (fe->ops.tuner_ops.get_if_frequency)
0431             fe->ops.tuner_ops.get_if_frequency(fe, &if_frequency);
0432         else
0433             if_frequency = 0;
0434 
0435         utmp = DIV_ROUND_CLOSEST_ULL((u64)if_frequency * 0x800000,
0436                          adc_freq);
0437 
0438         if (!dev->cfg.spec_inv && if_frequency)
0439             utmp = 0x800000 - utmp;
0440 
0441         buf[0] = (utmp >>  0) & 0xff;
0442         buf[1] = (utmp >>  8) & 0xff;
0443         buf[2] = (utmp >> 16) & 0xff;
0444         ret = regmap_bulk_write(dev->regmap, 0x800029, buf, 3);
0445         if (ret)
0446             goto err;
0447 
0448         dev_dbg(&client->dev, "if_frequency_cw=%06x\n", utmp);
0449 
0450         dev->bandwidth_hz = c->bandwidth_hz;
0451     }
0452 
0453     ret = regmap_update_bits(dev->regmap, 0x80f904, 0x03,
0454                  bandwidth_reg_val);
0455     if (ret)
0456         goto err;
0457     ret = regmap_write(dev->regmap, 0x800040, 0x00);
0458     if (ret)
0459         goto err;
0460     ret = regmap_write(dev->regmap, 0x800047, 0x00);
0461     if (ret)
0462         goto err;
0463     ret = regmap_update_bits(dev->regmap, 0x80f999, 0x01, 0x00);
0464     if (ret)
0465         goto err;
0466 
0467     if (c->frequency <= 230000000)
0468         tmp = 0x00; /* VHF */
0469     else
0470         tmp = 0x01; /* UHF */
0471 
0472     ret = regmap_write(dev->regmap, 0x80004b, tmp);
0473     if (ret)
0474         goto err;
0475     /* Reset FSM */
0476     ret = regmap_write(dev->regmap, 0x800000, 0x00);
0477     if (ret)
0478         goto err;
0479 
0480     return 0;
0481 err:
0482     dev_dbg(&client->dev, "failed=%d\n", ret);
0483     return ret;
0484 }
0485 
0486 static int af9033_get_frontend(struct dvb_frontend *fe,
0487                    struct dtv_frontend_properties *c)
0488 {
0489     struct af9033_dev *dev = fe->demodulator_priv;
0490     struct i2c_client *client = dev->client;
0491     int ret;
0492     u8 buf[8];
0493 
0494     dev_dbg(&client->dev, "\n");
0495 
0496     /* Read all needed TPS registers */
0497     ret = regmap_bulk_read(dev->regmap, 0x80f900, buf, 8);
0498     if (ret)
0499         goto err;
0500 
0501     switch ((buf[0] >> 0) & 3) {
0502     case 0:
0503         c->transmission_mode = TRANSMISSION_MODE_2K;
0504         break;
0505     case 1:
0506         c->transmission_mode = TRANSMISSION_MODE_8K;
0507         break;
0508     }
0509 
0510     switch ((buf[1] >> 0) & 3) {
0511     case 0:
0512         c->guard_interval = GUARD_INTERVAL_1_32;
0513         break;
0514     case 1:
0515         c->guard_interval = GUARD_INTERVAL_1_16;
0516         break;
0517     case 2:
0518         c->guard_interval = GUARD_INTERVAL_1_8;
0519         break;
0520     case 3:
0521         c->guard_interval = GUARD_INTERVAL_1_4;
0522         break;
0523     }
0524 
0525     switch ((buf[2] >> 0) & 7) {
0526     case 0:
0527         c->hierarchy = HIERARCHY_NONE;
0528         break;
0529     case 1:
0530         c->hierarchy = HIERARCHY_1;
0531         break;
0532     case 2:
0533         c->hierarchy = HIERARCHY_2;
0534         break;
0535     case 3:
0536         c->hierarchy = HIERARCHY_4;
0537         break;
0538     }
0539 
0540     switch ((buf[3] >> 0) & 3) {
0541     case 0:
0542         c->modulation = QPSK;
0543         break;
0544     case 1:
0545         c->modulation = QAM_16;
0546         break;
0547     case 2:
0548         c->modulation = QAM_64;
0549         break;
0550     }
0551 
0552     switch ((buf[4] >> 0) & 3) {
0553     case 0:
0554         c->bandwidth_hz = 6000000;
0555         break;
0556     case 1:
0557         c->bandwidth_hz = 7000000;
0558         break;
0559     case 2:
0560         c->bandwidth_hz = 8000000;
0561         break;
0562     }
0563 
0564     switch ((buf[6] >> 0) & 7) {
0565     case 0:
0566         c->code_rate_HP = FEC_1_2;
0567         break;
0568     case 1:
0569         c->code_rate_HP = FEC_2_3;
0570         break;
0571     case 2:
0572         c->code_rate_HP = FEC_3_4;
0573         break;
0574     case 3:
0575         c->code_rate_HP = FEC_5_6;
0576         break;
0577     case 4:
0578         c->code_rate_HP = FEC_7_8;
0579         break;
0580     case 5:
0581         c->code_rate_HP = FEC_NONE;
0582         break;
0583     }
0584 
0585     switch ((buf[7] >> 0) & 7) {
0586     case 0:
0587         c->code_rate_LP = FEC_1_2;
0588         break;
0589     case 1:
0590         c->code_rate_LP = FEC_2_3;
0591         break;
0592     case 2:
0593         c->code_rate_LP = FEC_3_4;
0594         break;
0595     case 3:
0596         c->code_rate_LP = FEC_5_6;
0597         break;
0598     case 4:
0599         c->code_rate_LP = FEC_7_8;
0600         break;
0601     case 5:
0602         c->code_rate_LP = FEC_NONE;
0603         break;
0604     }
0605 
0606     return 0;
0607 err:
0608     dev_dbg(&client->dev, "failed=%d\n", ret);
0609     return ret;
0610 }
0611 
0612 static int af9033_read_status(struct dvb_frontend *fe, enum fe_status *status)
0613 {
0614     struct af9033_dev *dev = fe->demodulator_priv;
0615     struct i2c_client *client = dev->client;
0616     struct dtv_frontend_properties *c = &fe->dtv_property_cache;
0617     int ret, tmp = 0;
0618     u8 buf[7];
0619     unsigned int utmp, utmp1;
0620 
0621     dev_dbg(&client->dev, "\n");
0622 
0623     *status = 0;
0624 
0625     /* Radio channel status: 0=no result, 1=has signal, 2=no signal */
0626     ret = regmap_read(dev->regmap, 0x800047, &utmp);
0627     if (ret)
0628         goto err;
0629 
0630     /* Has signal */
0631     if (utmp == 0x01)
0632         *status |= FE_HAS_SIGNAL;
0633 
0634     if (utmp != 0x02) {
0635         /* TPS lock */
0636         ret = regmap_read(dev->regmap, 0x80f5a9, &utmp);
0637         if (ret)
0638             goto err;
0639 
0640         if ((utmp >> 0) & 0x01)
0641             *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
0642                     FE_HAS_VITERBI;
0643 
0644         /* Full lock */
0645         ret = regmap_read(dev->regmap, 0x80f999, &utmp);
0646         if (ret)
0647             goto err;
0648 
0649         if ((utmp >> 0) & 0x01)
0650             *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
0651                     FE_HAS_VITERBI | FE_HAS_SYNC |
0652                     FE_HAS_LOCK;
0653     }
0654 
0655     dev->fe_status = *status;
0656 
0657     /* Signal strength */
0658     if (dev->fe_status & FE_HAS_SIGNAL) {
0659         if (dev->is_af9035) {
0660             ret = regmap_read(dev->regmap, 0x80004a, &utmp);
0661             if (ret)
0662                 goto err;
0663             tmp = -utmp * 1000;
0664         } else {
0665             ret = regmap_read(dev->regmap, 0x8000f7, &utmp);
0666             if (ret)
0667                 goto err;
0668             tmp = (utmp - 100) * 1000;
0669         }
0670 
0671         c->strength.len = 1;
0672         c->strength.stat[0].scale = FE_SCALE_DECIBEL;
0673         c->strength.stat[0].svalue = tmp;
0674     } else {
0675         c->strength.len = 1;
0676         c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
0677     }
0678 
0679     /* CNR */
0680     if (dev->fe_status & FE_HAS_VITERBI) {
0681         /* Read raw SNR value */
0682         ret = regmap_bulk_read(dev->regmap, 0x80002c, buf, 3);
0683         if (ret)
0684             goto err;
0685 
0686         utmp1 = buf[2] << 16 | buf[1] << 8 | buf[0] << 0;
0687 
0688         /* Read superframe number */
0689         ret = regmap_read(dev->regmap, 0x80f78b, &utmp);
0690         if (ret)
0691             goto err;
0692 
0693         if (utmp)
0694             utmp1 /= utmp;
0695 
0696         /* Read current transmission mode */
0697         ret = regmap_read(dev->regmap, 0x80f900, &utmp);
0698         if (ret)
0699             goto err;
0700 
0701         switch ((utmp >> 0) & 3) {
0702         case 0:
0703             /* 2k */
0704             utmp1 *= 4;
0705             break;
0706         case 1:
0707             /* 8k */
0708             utmp1 *= 1;
0709             break;
0710         case 2:
0711             /* 4k */
0712             utmp1 *= 2;
0713             break;
0714         default:
0715             utmp1 *= 0;
0716             break;
0717         }
0718 
0719         /* Read current modulation */
0720         ret = regmap_read(dev->regmap, 0x80f903, &utmp);
0721         if (ret)
0722             goto err;
0723 
0724         switch ((utmp >> 0) & 3) {
0725         case 0:
0726             /*
0727              * QPSK
0728              * CNR[dB] 13 * -log10((1690000 - value) / value) + 2.6
0729              * value [653799, 1689999], 2.6 / 13 = 3355443
0730              */
0731             utmp1 = clamp(utmp1, 653799U, 1689999U);
0732             utmp1 = ((u64)(intlog10(utmp1)
0733                  - intlog10(1690000 - utmp1)
0734                  + 3355443) * 13 * 1000) >> 24;
0735             break;
0736         case 1:
0737             /*
0738              * QAM-16
0739              * CNR[dB] 6 * log10((value - 370000) / (828000 - value)) + 15.7
0740              * value [371105, 827999], 15.7 / 6 = 43900382
0741              */
0742             utmp1 = clamp(utmp1, 371105U, 827999U);
0743             utmp1 = ((u64)(intlog10(utmp1 - 370000)
0744                  - intlog10(828000 - utmp1)
0745                  + 43900382) * 6 * 1000) >> 24;
0746             break;
0747         case 2:
0748             /*
0749              * QAM-64
0750              * CNR[dB] 8 * log10((value - 193000) / (425000 - value)) + 23.8
0751              * value [193246, 424999], 23.8 / 8 = 49912218
0752              */
0753             utmp1 = clamp(utmp1, 193246U, 424999U);
0754             utmp1 = ((u64)(intlog10(utmp1 - 193000)
0755                  - intlog10(425000 - utmp1)
0756                  + 49912218) * 8 * 1000) >> 24;
0757             break;
0758         default:
0759             utmp1 = 0;
0760             break;
0761         }
0762 
0763         dev_dbg(&client->dev, "cnr=%u\n", utmp1);
0764 
0765         c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
0766         c->cnr.stat[0].svalue = utmp1;
0767     } else {
0768         c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
0769     }
0770 
0771     /* UCB/PER/BER */
0772     if (dev->fe_status & FE_HAS_LOCK) {
0773         /* Outer FEC, 204 byte packets */
0774         u16 abort_packet_count, rsd_packet_count;
0775         /* Inner FEC, bits */
0776         u32 rsd_bit_err_count;
0777 
0778         /*
0779          * Packet count used for measurement is 10000
0780          * (rsd_packet_count). Maybe it should be increased?
0781          */
0782 
0783         ret = regmap_bulk_read(dev->regmap, 0x800032, buf, 7);
0784         if (ret)
0785             goto err;
0786 
0787         abort_packet_count = (buf[1] << 8) | (buf[0] << 0);
0788         rsd_bit_err_count = (buf[4] << 16) | (buf[3] << 8) | buf[2];
0789         rsd_packet_count = (buf[6] << 8) | (buf[5] << 0);
0790 
0791         dev->error_block_count += abort_packet_count;
0792         dev->total_block_count += rsd_packet_count;
0793         dev->post_bit_error += rsd_bit_err_count;
0794         dev->post_bit_count += rsd_packet_count * 204 * 8;
0795 
0796         c->block_count.len = 1;
0797         c->block_count.stat[0].scale = FE_SCALE_COUNTER;
0798         c->block_count.stat[0].uvalue = dev->total_block_count;
0799 
0800         c->block_error.len = 1;
0801         c->block_error.stat[0].scale = FE_SCALE_COUNTER;
0802         c->block_error.stat[0].uvalue = dev->error_block_count;
0803 
0804         c->post_bit_count.len = 1;
0805         c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
0806         c->post_bit_count.stat[0].uvalue = dev->post_bit_count;
0807 
0808         c->post_bit_error.len = 1;
0809         c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
0810         c->post_bit_error.stat[0].uvalue = dev->post_bit_error;
0811     }
0812 
0813     return 0;
0814 err:
0815     dev_dbg(&client->dev, "failed=%d\n", ret);
0816     return ret;
0817 }
0818 
0819 static int af9033_read_snr(struct dvb_frontend *fe, u16 *snr)
0820 {
0821     struct af9033_dev *dev = fe->demodulator_priv;
0822     struct i2c_client *client = dev->client;
0823     struct dtv_frontend_properties *c = &dev->fe.dtv_property_cache;
0824     int ret;
0825     unsigned int utmp;
0826 
0827     dev_dbg(&client->dev, "\n");
0828 
0829     /* Use DVBv5 CNR */
0830     if (c->cnr.stat[0].scale == FE_SCALE_DECIBEL) {
0831         /* Return 0.1 dB for AF9030 and 0-0xffff for IT9130. */
0832         if (dev->is_af9035) {
0833             /* 1000x => 10x (0.1 dB) */
0834             *snr = div_s64(c->cnr.stat[0].svalue, 100);
0835         } else {
0836             /* 1000x => 1x (1 dB) */
0837             *snr = div_s64(c->cnr.stat[0].svalue, 1000);
0838 
0839             /* Read current modulation */
0840             ret = regmap_read(dev->regmap, 0x80f903, &utmp);
0841             if (ret)
0842                 goto err;
0843 
0844             /* scale value to 0x0000-0xffff */
0845             switch ((utmp >> 0) & 3) {
0846             case 0:
0847                 *snr = *snr * 0xffff / 23;
0848                 break;
0849             case 1:
0850                 *snr = *snr * 0xffff / 26;
0851                 break;
0852             case 2:
0853                 *snr = *snr * 0xffff / 32;
0854                 break;
0855             default:
0856                 ret = -EINVAL;
0857                 goto err;
0858             }
0859         }
0860     } else {
0861         *snr = 0;
0862     }
0863 
0864     return 0;
0865 err:
0866     dev_dbg(&client->dev, "failed=%d\n", ret);
0867     return ret;
0868 }
0869 
0870 static int af9033_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
0871 {
0872     struct af9033_dev *dev = fe->demodulator_priv;
0873     struct i2c_client *client = dev->client;
0874     struct dtv_frontend_properties *c = &dev->fe.dtv_property_cache;
0875     int ret, tmp, power_real;
0876     unsigned int utmp;
0877     u8 gain_offset, buf[7];
0878 
0879     dev_dbg(&client->dev, "\n");
0880 
0881     if (dev->is_af9035) {
0882         /* Read signal strength of 0-100 scale */
0883         ret = regmap_read(dev->regmap, 0x800048, &utmp);
0884         if (ret)
0885             goto err;
0886 
0887         /* Scale value to 0x0000-0xffff */
0888         *strength = utmp * 0xffff / 100;
0889     } else {
0890         ret = regmap_read(dev->regmap, 0x8000f7, &utmp);
0891         if (ret)
0892             goto err;
0893 
0894         ret = regmap_bulk_read(dev->regmap, 0x80f900, buf, 7);
0895         if (ret)
0896             goto err;
0897 
0898         if (c->frequency <= 300000000)
0899             gain_offset = 7; /* VHF */
0900         else
0901             gain_offset = 4; /* UHF */
0902 
0903         power_real = (utmp - 100 - gain_offset) -
0904             power_reference[((buf[3] >> 0) & 3)][((buf[6] >> 0) & 7)];
0905 
0906         if (power_real < -15)
0907             tmp = 0;
0908         else if ((power_real >= -15) && (power_real < 0))
0909             tmp = (2 * (power_real + 15)) / 3;
0910         else if ((power_real >= 0) && (power_real < 20))
0911             tmp = 4 * power_real + 10;
0912         else if ((power_real >= 20) && (power_real < 35))
0913             tmp = (2 * (power_real - 20)) / 3 + 90;
0914         else
0915             tmp = 100;
0916 
0917         /* Scale value to 0x0000-0xffff */
0918         *strength = tmp * 0xffff / 100;
0919     }
0920 
0921     return 0;
0922 err:
0923     dev_dbg(&client->dev, "failed=%d\n", ret);
0924     return ret;
0925 }
0926 
0927 static int af9033_read_ber(struct dvb_frontend *fe, u32 *ber)
0928 {
0929     struct af9033_dev *dev = fe->demodulator_priv;
0930 
0931     *ber = (dev->post_bit_error - dev->post_bit_error_prev);
0932     dev->post_bit_error_prev = dev->post_bit_error;
0933 
0934     return 0;
0935 }
0936 
0937 static int af9033_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
0938 {
0939     struct af9033_dev *dev = fe->demodulator_priv;
0940 
0941     *ucblocks = dev->error_block_count;
0942 
0943     return 0;
0944 }
0945 
0946 static int af9033_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
0947 {
0948     struct af9033_dev *dev = fe->demodulator_priv;
0949     struct i2c_client *client = dev->client;
0950     int ret;
0951 
0952     dev_dbg(&client->dev, "enable=%d\n", enable);
0953 
0954     ret = regmap_update_bits(dev->regmap, 0x00fa04, 0x01, enable);
0955     if (ret)
0956         goto err;
0957 
0958     return 0;
0959 err:
0960     dev_dbg(&client->dev, "failed=%d\n", ret);
0961     return ret;
0962 }
0963 
0964 static int af9033_pid_filter_ctrl(struct dvb_frontend *fe, int onoff)
0965 {
0966     struct af9033_dev *dev = fe->demodulator_priv;
0967     struct i2c_client *client = dev->client;
0968     int ret;
0969 
0970     dev_dbg(&client->dev, "onoff=%d\n", onoff);
0971 
0972     ret = regmap_update_bits(dev->regmap, 0x80f993, 0x01, onoff);
0973     if (ret)
0974         goto err;
0975 
0976     return 0;
0977 err:
0978     dev_dbg(&client->dev, "failed=%d\n", ret);
0979     return ret;
0980 }
0981 
0982 static int af9033_pid_filter(struct dvb_frontend *fe, int index, u16 pid,
0983                  int onoff)
0984 {
0985     struct af9033_dev *dev = fe->demodulator_priv;
0986     struct i2c_client *client = dev->client;
0987     int ret;
0988     u8 wbuf[2] = {(pid >> 0) & 0xff, (pid >> 8) & 0xff};
0989 
0990     dev_dbg(&client->dev, "index=%d pid=%04x onoff=%d\n",
0991         index, pid, onoff);
0992 
0993     if (pid > 0x1fff)
0994         return 0;
0995 
0996     ret = regmap_bulk_write(dev->regmap, 0x80f996, wbuf, 2);
0997     if (ret)
0998         goto err;
0999     ret = regmap_write(dev->regmap, 0x80f994, onoff);
1000     if (ret)
1001         goto err;
1002     ret = regmap_write(dev->regmap, 0x80f995, index);
1003     if (ret)
1004         goto err;
1005 
1006     return 0;
1007 err:
1008     dev_dbg(&client->dev, "failed=%d\n", ret);
1009     return ret;
1010 }
1011 
1012 static const struct dvb_frontend_ops af9033_ops = {
1013     .delsys = {SYS_DVBT},
1014     .info = {
1015         .name = "Afatech AF9033 (DVB-T)",
1016         .frequency_min_hz = 174 * MHz,
1017         .frequency_max_hz = 862 * MHz,
1018         .frequency_stepsize_hz = 250 * kHz,
1019         .caps = FE_CAN_FEC_1_2 |
1020             FE_CAN_FEC_2_3 |
1021             FE_CAN_FEC_3_4 |
1022             FE_CAN_FEC_5_6 |
1023             FE_CAN_FEC_7_8 |
1024             FE_CAN_FEC_AUTO |
1025             FE_CAN_QPSK |
1026             FE_CAN_QAM_16 |
1027             FE_CAN_QAM_64 |
1028             FE_CAN_QAM_AUTO |
1029             FE_CAN_TRANSMISSION_MODE_AUTO |
1030             FE_CAN_GUARD_INTERVAL_AUTO |
1031             FE_CAN_HIERARCHY_AUTO |
1032             FE_CAN_RECOVER |
1033             FE_CAN_MUTE_TS
1034     },
1035 
1036     .init = af9033_init,
1037     .sleep = af9033_sleep,
1038 
1039     .get_tune_settings = af9033_get_tune_settings,
1040     .set_frontend = af9033_set_frontend,
1041     .get_frontend = af9033_get_frontend,
1042 
1043     .read_status = af9033_read_status,
1044     .read_snr = af9033_read_snr,
1045     .read_signal_strength = af9033_read_signal_strength,
1046     .read_ber = af9033_read_ber,
1047     .read_ucblocks = af9033_read_ucblocks,
1048 
1049     .i2c_gate_ctrl = af9033_i2c_gate_ctrl,
1050 };
1051 
1052 static int af9033_probe(struct i2c_client *client,
1053             const struct i2c_device_id *id)
1054 {
1055     struct af9033_config *cfg = client->dev.platform_data;
1056     struct af9033_dev *dev;
1057     int ret;
1058     u8 buf[8];
1059     u32 reg;
1060     static const struct regmap_config regmap_config = {
1061         .reg_bits    =  24,
1062         .val_bits    =  8,
1063     };
1064 
1065     /* Allocate memory for the internal state */
1066     dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1067     if (!dev) {
1068         ret = -ENOMEM;
1069         goto err;
1070     }
1071 
1072     /* Setup the state */
1073     dev->client = client;
1074     memcpy(&dev->cfg, cfg, sizeof(dev->cfg));
1075     switch (dev->cfg.ts_mode) {
1076     case AF9033_TS_MODE_PARALLEL:
1077         dev->ts_mode_parallel = true;
1078         break;
1079     case AF9033_TS_MODE_SERIAL:
1080         dev->ts_mode_serial = true;
1081         break;
1082     case AF9033_TS_MODE_USB:
1083         /* USB mode for AF9035 */
1084     default:
1085         break;
1086     }
1087 
1088     if (dev->cfg.clock != 12000000) {
1089         ret = -ENODEV;
1090         dev_err(&client->dev,
1091             "Unsupported clock %u Hz. Only 12000000 Hz is supported currently\n",
1092             dev->cfg.clock);
1093         goto err_kfree;
1094     }
1095 
1096     /* Create regmap */
1097     dev->regmap = regmap_init_i2c(client, &regmap_config);
1098     if (IS_ERR(dev->regmap)) {
1099         ret = PTR_ERR(dev->regmap);
1100         goto err_kfree;
1101     }
1102 
1103     /* Firmware version */
1104     switch (dev->cfg.tuner) {
1105     case AF9033_TUNER_IT9135_38:
1106     case AF9033_TUNER_IT9135_51:
1107     case AF9033_TUNER_IT9135_52:
1108     case AF9033_TUNER_IT9135_60:
1109     case AF9033_TUNER_IT9135_61:
1110     case AF9033_TUNER_IT9135_62:
1111         dev->is_it9135 = true;
1112         reg = 0x004bfc;
1113         break;
1114     default:
1115         dev->is_af9035 = true;
1116         reg = 0x0083e9;
1117         break;
1118     }
1119 
1120     ret = regmap_bulk_read(dev->regmap, reg, &buf[0], 4);
1121     if (ret)
1122         goto err_regmap_exit;
1123     ret = regmap_bulk_read(dev->regmap, 0x804191, &buf[4], 4);
1124     if (ret)
1125         goto err_regmap_exit;
1126 
1127     dev_info(&client->dev,
1128          "firmware version: LINK %d.%d.%d.%d - OFDM %d.%d.%d.%d\n",
1129          buf[0], buf[1], buf[2], buf[3],
1130          buf[4], buf[5], buf[6], buf[7]);
1131 
1132     /* Sleep as chip seems to be partly active by default */
1133     /* IT9135 did not like to sleep at that early */
1134     if (dev->is_af9035) {
1135         ret = regmap_write(dev->regmap, 0x80004c, 0x01);
1136         if (ret)
1137             goto err_regmap_exit;
1138         ret = regmap_write(dev->regmap, 0x800000, 0x00);
1139         if (ret)
1140             goto err_regmap_exit;
1141     }
1142 
1143     /* Create dvb frontend */
1144     memcpy(&dev->fe.ops, &af9033_ops, sizeof(dev->fe.ops));
1145     dev->fe.demodulator_priv = dev;
1146     *cfg->fe = &dev->fe;
1147     if (cfg->ops) {
1148         cfg->ops->pid_filter = af9033_pid_filter;
1149         cfg->ops->pid_filter_ctrl = af9033_pid_filter_ctrl;
1150     }
1151     cfg->regmap = dev->regmap;
1152     i2c_set_clientdata(client, dev);
1153 
1154     dev_info(&client->dev, "Afatech AF9033 successfully attached\n");
1155 
1156     return 0;
1157 err_regmap_exit:
1158     regmap_exit(dev->regmap);
1159 err_kfree:
1160     kfree(dev);
1161 err:
1162     dev_dbg(&client->dev, "failed=%d\n", ret);
1163     return ret;
1164 }
1165 
1166 static int af9033_remove(struct i2c_client *client)
1167 {
1168     struct af9033_dev *dev = i2c_get_clientdata(client);
1169 
1170     dev_dbg(&client->dev, "\n");
1171 
1172     regmap_exit(dev->regmap);
1173     kfree(dev);
1174 
1175     return 0;
1176 }
1177 
1178 static const struct i2c_device_id af9033_id_table[] = {
1179     {"af9033", 0},
1180     {}
1181 };
1182 MODULE_DEVICE_TABLE(i2c, af9033_id_table);
1183 
1184 static struct i2c_driver af9033_driver = {
1185     .driver = {
1186         .name   = "af9033",
1187         .suppress_bind_attrs    = true,
1188     },
1189     .probe      = af9033_probe,
1190     .remove     = af9033_remove,
1191     .id_table   = af9033_id_table,
1192 };
1193 
1194 module_i2c_driver(af9033_driver);
1195 
1196 MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
1197 MODULE_DESCRIPTION("Afatech AF9033 DVB-T demodulator driver");
1198 MODULE_LICENSE("GPL");
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!