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0001 // SPDX-License-Identifier: GPL-2.0
0002 #include <media/drv-intf/saa7146_vv.h>
0003 
0004 static int vbi_pixel_to_capture = 720 * 2;
0005 
0006 static int vbi_workaround(struct saa7146_dev *dev)
0007 {
0008     struct saa7146_vv *vv = dev->vv_data;
0009 
0010     u32          *cpu;
0011     dma_addr_t   dma_addr;
0012 
0013     int count = 0;
0014     int i;
0015 
0016     DECLARE_WAITQUEUE(wait, current);
0017 
0018     DEB_VBI("dev:%p\n", dev);
0019 
0020     /* once again, a bug in the saa7146: the brs acquisition
0021        is buggy and especially the BXO-counter does not work
0022        as specified. there is this workaround, but please
0023        don't let me explain it. ;-) */
0024 
0025     cpu = dma_alloc_coherent(&dev->pci->dev, 4096, &dma_addr, GFP_KERNEL);
0026     if (NULL == cpu)
0027         return -ENOMEM;
0028 
0029     /* setup some basic programming, just for the workaround */
0030     saa7146_write(dev, BASE_EVEN3,  dma_addr);
0031     saa7146_write(dev, BASE_ODD3,   dma_addr+vbi_pixel_to_capture);
0032     saa7146_write(dev, PROT_ADDR3,  dma_addr+4096);
0033     saa7146_write(dev, PITCH3,  vbi_pixel_to_capture);
0034     saa7146_write(dev, BASE_PAGE3,  0x0);
0035     saa7146_write(dev, NUM_LINE_BYTE3, (2<<16)|((vbi_pixel_to_capture)<<0));
0036     saa7146_write(dev, MC2, MASK_04|MASK_20);
0037 
0038     /* load brs-control register */
0039     WRITE_RPS1(CMD_WR_REG | (1 << 8) | (BRS_CTRL/4));
0040     /* BXO = 1h, BRS to outbound */
0041     WRITE_RPS1(0xc000008c);
0042     /* wait for vbi_a or vbi_b*/
0043     if ( 0 != (SAA7146_USE_PORT_B_FOR_VBI & dev->ext_vv_data->flags)) {
0044         DEB_D("...using port b\n");
0045         WRITE_RPS1(CMD_PAUSE | CMD_OAN | CMD_SIG1 | CMD_E_FID_B);
0046         WRITE_RPS1(CMD_PAUSE | CMD_OAN | CMD_SIG1 | CMD_O_FID_B);
0047 /*
0048         WRITE_RPS1(CMD_PAUSE | MASK_09);
0049 */
0050     } else {
0051         DEB_D("...using port a\n");
0052         WRITE_RPS1(CMD_PAUSE | MASK_10);
0053     }
0054     /* upload brs */
0055     WRITE_RPS1(CMD_UPLOAD | MASK_08);
0056     /* load brs-control register */
0057     WRITE_RPS1(CMD_WR_REG | (1 << 8) | (BRS_CTRL/4));
0058     /* BYO = 1, BXO = NQBIL (=1728 for PAL, for NTSC this is 858*2) - NumByte3 (=1440) = 288 */
0059     WRITE_RPS1(((1728-(vbi_pixel_to_capture)) << 7) | MASK_19);
0060     /* wait for brs_done */
0061     WRITE_RPS1(CMD_PAUSE | MASK_08);
0062     /* upload brs */
0063     WRITE_RPS1(CMD_UPLOAD | MASK_08);
0064     /* load video-dma3 NumLines3 and NumBytes3 */
0065     WRITE_RPS1(CMD_WR_REG | (1 << 8) | (NUM_LINE_BYTE3/4));
0066     /* dev->vbi_count*2 lines, 720 pixel (= 1440 Bytes) */
0067     WRITE_RPS1((2 << 16) | (vbi_pixel_to_capture));
0068     /* load brs-control register */
0069     WRITE_RPS1(CMD_WR_REG | (1 << 8) | (BRS_CTRL/4));
0070     /* Set BRS right: note: this is an experimental value for BXO (=> PAL!) */
0071     WRITE_RPS1((540 << 7) | (5 << 19));  // 5 == vbi_start
0072     /* wait for brs_done */
0073     WRITE_RPS1(CMD_PAUSE | MASK_08);
0074     /* upload brs and video-dma3*/
0075     WRITE_RPS1(CMD_UPLOAD | MASK_08 | MASK_04);
0076     /* load mc2 register: enable dma3 */
0077     WRITE_RPS1(CMD_WR_REG | (1 << 8) | (MC1/4));
0078     WRITE_RPS1(MASK_20 | MASK_04);
0079     /* generate interrupt */
0080     WRITE_RPS1(CMD_INTERRUPT);
0081     /* stop rps1 */
0082     WRITE_RPS1(CMD_STOP);
0083 
0084     /* we have to do the workaround twice to be sure that
0085        everything is ok */
0086     for(i = 0; i < 2; i++) {
0087 
0088         /* indicate to the irq handler that we do the workaround */
0089         saa7146_write(dev, MC2, MASK_31|MASK_15);
0090 
0091         saa7146_write(dev, NUM_LINE_BYTE3, (1<<16)|(2<<0));
0092         saa7146_write(dev, MC2, MASK_04|MASK_20);
0093 
0094         /* enable rps1 irqs */
0095         SAA7146_IER_ENABLE(dev,MASK_28);
0096 
0097         /* prepare to wait to be woken up by the irq-handler */
0098         add_wait_queue(&vv->vbi_wq, &wait);
0099         set_current_state(TASK_INTERRUPTIBLE);
0100 
0101         /* start rps1 to enable workaround */
0102         saa7146_write(dev, RPS_ADDR1, dev->d_rps1.dma_handle);
0103         saa7146_write(dev, MC1, (MASK_13 | MASK_29));
0104 
0105         schedule();
0106 
0107         DEB_VBI("brs bug workaround %d/1\n", i);
0108 
0109         remove_wait_queue(&vv->vbi_wq, &wait);
0110         __set_current_state(TASK_RUNNING);
0111 
0112         /* disable rps1 irqs */
0113         SAA7146_IER_DISABLE(dev,MASK_28);
0114 
0115         /* stop video-dma3 */
0116         saa7146_write(dev, MC1, MASK_20);
0117 
0118         if(signal_pending(current)) {
0119 
0120             DEB_VBI("aborted (rps:0x%08x)\n",
0121                 saa7146_read(dev, RPS_ADDR1));
0122 
0123             /* stop rps1 for sure */
0124             saa7146_write(dev, MC1, MASK_29);
0125 
0126             dma_free_coherent(&dev->pci->dev, 4096, cpu, dma_addr);
0127             return -EINTR;
0128         }
0129     }
0130 
0131     dma_free_coherent(&dev->pci->dev, 4096, cpu, dma_addr);
0132     return 0;
0133 }
0134 
0135 static void saa7146_set_vbi_capture(struct saa7146_dev *dev, struct saa7146_buf *buf, struct saa7146_buf *next)
0136 {
0137     struct saa7146_vv *vv = dev->vv_data;
0138 
0139     struct saa7146_video_dma vdma3;
0140 
0141     int count = 0;
0142     unsigned long e_wait = vv->current_hps_sync == SAA7146_HPS_SYNC_PORT_A ? CMD_E_FID_A : CMD_E_FID_B;
0143     unsigned long o_wait = vv->current_hps_sync == SAA7146_HPS_SYNC_PORT_A ? CMD_O_FID_A : CMD_O_FID_B;
0144 
0145 /*
0146     vdma3.base_even = 0xc8000000+2560*70;
0147     vdma3.base_odd  = 0xc8000000;
0148     vdma3.prot_addr = 0xc8000000+2560*164;
0149     vdma3.pitch = 2560;
0150     vdma3.base_page = 0;
0151     vdma3.num_line_byte = (64<<16)|((vbi_pixel_to_capture)<<0); // set above!
0152 */
0153     vdma3.base_even = buf->pt[2].offset;
0154     vdma3.base_odd  = buf->pt[2].offset + 16 * vbi_pixel_to_capture;
0155     vdma3.prot_addr = buf->pt[2].offset + 16 * 2 * vbi_pixel_to_capture;
0156     vdma3.pitch = vbi_pixel_to_capture;
0157     vdma3.base_page = buf->pt[2].dma | ME1;
0158     vdma3.num_line_byte = (16 << 16) | vbi_pixel_to_capture;
0159 
0160     saa7146_write_out_dma(dev, 3, &vdma3);
0161 
0162     /* write beginning of rps-program */
0163     count = 0;
0164 
0165     /* wait for o_fid_a/b / e_fid_a/b toggle only if bit 1 is not set */
0166 
0167     /* we don't wait here for the first field anymore. this is different from the video
0168        capture and might cause that the first buffer is only half filled (with only
0169        one field). but since this is some sort of streaming data, this is not that negative.
0170        but by doing this, we can use the whole engine from videobuf-dma-sg.c... */
0171 
0172 /*
0173     WRITE_RPS1(CMD_PAUSE | CMD_OAN | CMD_SIG1 | e_wait);
0174     WRITE_RPS1(CMD_PAUSE | CMD_OAN | CMD_SIG1 | o_wait);
0175 */
0176     /* set bit 1 */
0177     WRITE_RPS1(CMD_WR_REG | (1 << 8) | (MC2/4));
0178     WRITE_RPS1(MASK_28 | MASK_12);
0179 
0180     /* turn on video-dma3 */
0181     WRITE_RPS1(CMD_WR_REG_MASK | (MC1/4));
0182     WRITE_RPS1(MASK_04 | MASK_20);          /* => mask */
0183     WRITE_RPS1(MASK_04 | MASK_20);          /* => values */
0184 
0185     /* wait for o_fid_a/b / e_fid_a/b toggle */
0186     WRITE_RPS1(CMD_PAUSE | o_wait);
0187     WRITE_RPS1(CMD_PAUSE | e_wait);
0188 
0189     /* generate interrupt */
0190     WRITE_RPS1(CMD_INTERRUPT);
0191 
0192     /* stop */
0193     WRITE_RPS1(CMD_STOP);
0194 
0195     /* enable rps1 irqs */
0196     SAA7146_IER_ENABLE(dev, MASK_28);
0197 
0198     /* write the address of the rps-program */
0199     saa7146_write(dev, RPS_ADDR1, dev->d_rps1.dma_handle);
0200 
0201     /* turn on rps */
0202     saa7146_write(dev, MC1, (MASK_13 | MASK_29));
0203 }
0204 
0205 static int buffer_activate(struct saa7146_dev *dev,
0206                struct saa7146_buf *buf,
0207                struct saa7146_buf *next)
0208 {
0209     struct saa7146_vv *vv = dev->vv_data;
0210     buf->vb.state = VIDEOBUF_ACTIVE;
0211 
0212     DEB_VBI("dev:%p, buf:%p, next:%p\n", dev, buf, next);
0213     saa7146_set_vbi_capture(dev,buf,next);
0214 
0215     mod_timer(&vv->vbi_dmaq.timeout, jiffies+BUFFER_TIMEOUT);
0216     return 0;
0217 }
0218 
0219 static int buffer_prepare(struct videobuf_queue *q, struct videobuf_buffer *vb,enum v4l2_field field)
0220 {
0221     struct file *file = q->priv_data;
0222     struct saa7146_fh *fh = file->private_data;
0223     struct saa7146_dev *dev = fh->dev;
0224     struct saa7146_buf *buf = (struct saa7146_buf *)vb;
0225 
0226     int err = 0;
0227     int lines, llength, size;
0228 
0229     lines   = 16 * 2 ; /* 2 fields */
0230     llength = vbi_pixel_to_capture;
0231     size = lines * llength;
0232 
0233     DEB_VBI("vb:%p\n", vb);
0234 
0235     if (0 != buf->vb.baddr  &&  buf->vb.bsize < size) {
0236         DEB_VBI("size mismatch\n");
0237         return -EINVAL;
0238     }
0239 
0240     if (buf->vb.size != size)
0241         saa7146_dma_free(dev,q,buf);
0242 
0243     if (VIDEOBUF_NEEDS_INIT == buf->vb.state) {
0244         struct videobuf_dmabuf *dma=videobuf_to_dma(&buf->vb);
0245 
0246         buf->vb.width  = llength;
0247         buf->vb.height = lines;
0248         buf->vb.size   = size;
0249         buf->vb.field  = field; // FIXME: check this
0250 
0251         saa7146_pgtable_free(dev->pci, &buf->pt[2]);
0252         saa7146_pgtable_alloc(dev->pci, &buf->pt[2]);
0253 
0254         err = videobuf_iolock(q,&buf->vb, NULL);
0255         if (err)
0256             goto oops;
0257         err = saa7146_pgtable_build_single(dev->pci, &buf->pt[2],
0258                          dma->sglist, dma->sglen);
0259         if (0 != err)
0260             return err;
0261     }
0262     buf->vb.state = VIDEOBUF_PREPARED;
0263     buf->activate = buffer_activate;
0264 
0265     return 0;
0266 
0267  oops:
0268     DEB_VBI("error out\n");
0269     saa7146_dma_free(dev,q,buf);
0270 
0271     return err;
0272 }
0273 
0274 static int buffer_setup(struct videobuf_queue *q, unsigned int *count, unsigned int *size)
0275 {
0276     int llength,lines;
0277 
0278     lines   = 16 * 2 ; /* 2 fields */
0279     llength = vbi_pixel_to_capture;
0280 
0281     *size = lines * llength;
0282     *count = 2;
0283 
0284     DEB_VBI("count:%d, size:%d\n", *count, *size);
0285 
0286     return 0;
0287 }
0288 
0289 static void buffer_queue(struct videobuf_queue *q, struct videobuf_buffer *vb)
0290 {
0291     struct file *file = q->priv_data;
0292     struct saa7146_fh *fh = file->private_data;
0293     struct saa7146_dev *dev = fh->dev;
0294     struct saa7146_vv *vv = dev->vv_data;
0295     struct saa7146_buf *buf = (struct saa7146_buf *)vb;
0296 
0297     DEB_VBI("vb:%p\n", vb);
0298     saa7146_buffer_queue(dev, &vv->vbi_dmaq, buf);
0299 }
0300 
0301 static void buffer_release(struct videobuf_queue *q, struct videobuf_buffer *vb)
0302 {
0303     struct file *file = q->priv_data;
0304     struct saa7146_fh *fh   = file->private_data;
0305     struct saa7146_dev *dev = fh->dev;
0306     struct saa7146_buf *buf = (struct saa7146_buf *)vb;
0307 
0308     DEB_VBI("vb:%p\n", vb);
0309     saa7146_dma_free(dev,q,buf);
0310 }
0311 
0312 static const struct videobuf_queue_ops vbi_qops = {
0313     .buf_setup    = buffer_setup,
0314     .buf_prepare  = buffer_prepare,
0315     .buf_queue    = buffer_queue,
0316     .buf_release  = buffer_release,
0317 };
0318 
0319 /* ------------------------------------------------------------------ */
0320 
0321 static void vbi_stop(struct saa7146_fh *fh, struct file *file)
0322 {
0323     struct saa7146_dev *dev = fh->dev;
0324     struct saa7146_vv *vv = dev->vv_data;
0325     unsigned long flags;
0326     DEB_VBI("dev:%p, fh:%p\n", dev, fh);
0327 
0328     spin_lock_irqsave(&dev->slock,flags);
0329 
0330     /* disable rps1  */
0331     saa7146_write(dev, MC1, MASK_29);
0332 
0333     /* disable rps1 irqs */
0334     SAA7146_IER_DISABLE(dev, MASK_28);
0335 
0336     /* shut down dma 3 transfers */
0337     saa7146_write(dev, MC1, MASK_20);
0338 
0339     if (vv->vbi_dmaq.curr)
0340         saa7146_buffer_finish(dev, &vv->vbi_dmaq, VIDEOBUF_DONE);
0341 
0342     videobuf_queue_cancel(&fh->vbi_q);
0343 
0344     vv->vbi_streaming = NULL;
0345 
0346     del_timer(&vv->vbi_dmaq.timeout);
0347     del_timer(&vv->vbi_read_timeout);
0348 
0349     spin_unlock_irqrestore(&dev->slock, flags);
0350 }
0351 
0352 static void vbi_read_timeout(struct timer_list *t)
0353 {
0354     struct saa7146_vv *vv = from_timer(vv, t, vbi_read_timeout);
0355     struct file *file = vv->vbi_read_timeout_file;
0356     struct saa7146_fh *fh = file->private_data;
0357     struct saa7146_dev *dev = fh->dev;
0358 
0359     DEB_VBI("dev:%p, fh:%p\n", dev, fh);
0360 
0361     vbi_stop(fh, file);
0362 }
0363 
0364 static void vbi_init(struct saa7146_dev *dev, struct saa7146_vv *vv)
0365 {
0366     DEB_VBI("dev:%p\n", dev);
0367 
0368     INIT_LIST_HEAD(&vv->vbi_dmaq.queue);
0369 
0370     timer_setup(&vv->vbi_dmaq.timeout, saa7146_buffer_timeout, 0);
0371     vv->vbi_dmaq.dev              = dev;
0372 
0373     init_waitqueue_head(&vv->vbi_wq);
0374 }
0375 
0376 static int vbi_open(struct saa7146_dev *dev, struct file *file)
0377 {
0378     struct saa7146_fh *fh = file->private_data;
0379     struct saa7146_vv *vv = fh->dev->vv_data;
0380 
0381     u32 arbtr_ctrl  = saa7146_read(dev, PCI_BT_V1);
0382     int ret = 0;
0383 
0384     DEB_VBI("dev:%p, fh:%p\n", dev, fh);
0385 
0386     ret = saa7146_res_get(fh, RESOURCE_DMA3_BRS);
0387     if (0 == ret) {
0388         DEB_S("cannot get vbi RESOURCE_DMA3_BRS resource\n");
0389         return -EBUSY;
0390     }
0391 
0392     /* adjust arbitrition control for video dma 3 */
0393     arbtr_ctrl &= ~0x1f0000;
0394     arbtr_ctrl |=  0x1d0000;
0395     saa7146_write(dev, PCI_BT_V1, arbtr_ctrl);
0396     saa7146_write(dev, MC2, (MASK_04|MASK_20));
0397 
0398     videobuf_queue_sg_init(&fh->vbi_q, &vbi_qops,
0399                 &dev->pci->dev, &dev->slock,
0400                 V4L2_BUF_TYPE_VBI_CAPTURE,
0401                 V4L2_FIELD_SEQ_TB, // FIXME: does this really work?
0402                 sizeof(struct saa7146_buf),
0403                 file, &dev->v4l2_lock);
0404 
0405     vv->vbi_read_timeout.function = vbi_read_timeout;
0406     vv->vbi_read_timeout_file = file;
0407 
0408     /* initialize the brs */
0409     if ( 0 != (SAA7146_USE_PORT_B_FOR_VBI & dev->ext_vv_data->flags)) {
0410         saa7146_write(dev, BRS_CTRL, MASK_30|MASK_29 | (7 << 19));
0411     } else {
0412         saa7146_write(dev, BRS_CTRL, 0x00000001);
0413 
0414         if (0 != (ret = vbi_workaround(dev))) {
0415             DEB_VBI("vbi workaround failed!\n");
0416             /* return ret;*/
0417         }
0418     }
0419 
0420     /* upload brs register */
0421     saa7146_write(dev, MC2, (MASK_08|MASK_24));
0422     return 0;
0423 }
0424 
0425 static void vbi_close(struct saa7146_dev *dev, struct file *file)
0426 {
0427     struct saa7146_fh *fh = file->private_data;
0428     struct saa7146_vv *vv = dev->vv_data;
0429     DEB_VBI("dev:%p, fh:%p\n", dev, fh);
0430 
0431     if( fh == vv->vbi_streaming ) {
0432         vbi_stop(fh, file);
0433     }
0434     saa7146_res_free(fh, RESOURCE_DMA3_BRS);
0435 }
0436 
0437 static void vbi_irq_done(struct saa7146_dev *dev, unsigned long status)
0438 {
0439     struct saa7146_vv *vv = dev->vv_data;
0440     spin_lock(&dev->slock);
0441 
0442     if (vv->vbi_dmaq.curr) {
0443         DEB_VBI("dev:%p, curr:%p\n", dev, vv->vbi_dmaq.curr);
0444         /* this must be += 2, one count for each field */
0445         vv->vbi_fieldcount+=2;
0446         vv->vbi_dmaq.curr->vb.field_count = vv->vbi_fieldcount;
0447         saa7146_buffer_finish(dev, &vv->vbi_dmaq, VIDEOBUF_DONE);
0448     } else {
0449         DEB_VBI("dev:%p\n", dev);
0450     }
0451     saa7146_buffer_next(dev, &vv->vbi_dmaq, 1);
0452 
0453     spin_unlock(&dev->slock);
0454 }
0455 
0456 static ssize_t vbi_read(struct file *file, char __user *data, size_t count, loff_t *ppos)
0457 {
0458     struct saa7146_fh *fh = file->private_data;
0459     struct saa7146_dev *dev = fh->dev;
0460     struct saa7146_vv *vv = dev->vv_data;
0461     ssize_t ret = 0;
0462 
0463     DEB_VBI("dev:%p, fh:%p\n", dev, fh);
0464 
0465     if( NULL == vv->vbi_streaming ) {
0466         // fixme: check if dma3 is available
0467         // fixme: activate vbi engine here if necessary. (really?)
0468         vv->vbi_streaming = fh;
0469     }
0470 
0471     if( fh != vv->vbi_streaming ) {
0472         DEB_VBI("open %p is already using vbi capture\n",
0473             vv->vbi_streaming);
0474         return -EBUSY;
0475     }
0476 
0477     mod_timer(&vv->vbi_read_timeout, jiffies+BUFFER_TIMEOUT);
0478     ret = videobuf_read_stream(&fh->vbi_q, data, count, ppos, 1,
0479                    file->f_flags & O_NONBLOCK);
0480 /*
0481     printk("BASE_ODD3:      0x%08x\n", saa7146_read(dev, BASE_ODD3));
0482     printk("BASE_EVEN3:     0x%08x\n", saa7146_read(dev, BASE_EVEN3));
0483     printk("PROT_ADDR3:     0x%08x\n", saa7146_read(dev, PROT_ADDR3));
0484     printk("PITCH3:         0x%08x\n", saa7146_read(dev, PITCH3));
0485     printk("BASE_PAGE3:     0x%08x\n", saa7146_read(dev, BASE_PAGE3));
0486     printk("NUM_LINE_BYTE3: 0x%08x\n", saa7146_read(dev, NUM_LINE_BYTE3));
0487     printk("BRS_CTRL:       0x%08x\n", saa7146_read(dev, BRS_CTRL));
0488 */
0489     return ret;
0490 }
0491 
0492 const struct saa7146_use_ops saa7146_vbi_uops = {
0493     .init       = vbi_init,
0494     .open       = vbi_open,
0495     .release    = vbi_close,
0496     .irq_done   = vbi_irq_done,
0497     .read       = vbi_read,
0498 };
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