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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
0003 
0004 #include <linux/kernel.h>
0005 #include <linux/export.h>
0006 #include <media/drv-intf/saa7146_vv.h>
0007 
0008 static void calculate_output_format_register(struct saa7146_dev* saa, u32 palette, u32* clip_format)
0009 {
0010     /* clear out the necessary bits */
0011     *clip_format &= 0x0000ffff;
0012     /* set these bits new */
0013     *clip_format |=  (( ((palette&0xf00)>>8) << 30) | ((palette&0x00f) << 24) | (((palette&0x0f0)>>4) << 16));
0014 }
0015 
0016 static void calculate_hps_source_and_sync(struct saa7146_dev *dev, int source, int sync, u32* hps_ctrl)
0017 {
0018     *hps_ctrl &= ~(MASK_30 | MASK_31 | MASK_28);
0019     *hps_ctrl |= (source << 30) | (sync << 28);
0020 }
0021 
0022 static void calculate_hxo_and_hyo(struct saa7146_vv *vv, u32* hps_h_scale, u32* hps_ctrl)
0023 {
0024     int hyo = 0, hxo = 0;
0025 
0026     hyo = vv->standard->v_offset;
0027     hxo = vv->standard->h_offset;
0028 
0029     *hps_h_scale    &= ~(MASK_B0 | 0xf00);
0030     *hps_h_scale    |= (hxo <<  0);
0031 
0032     *hps_ctrl   &= ~(MASK_W0 | MASK_B2);
0033     *hps_ctrl   |= (hyo << 12);
0034 }
0035 
0036 /* helper functions for the calculation of the horizontal- and vertical
0037    scaling registers, clip-format-register etc ...
0038    these functions take pointers to the (most-likely read-out
0039    original-values) and manipulate them according to the requested
0040    changes.
0041 */
0042 
0043 /* hps_coeff used for CXY and CXUV; scale 1/1 -> scale 1/64 */
0044 static struct {
0045     u16 hps_coeff;
0046     u16 weight_sum;
0047 } hps_h_coeff_tab [] = {
0048     {0x00,   2}, {0x02,   4}, {0x00,   4}, {0x06,   8}, {0x02,   8},
0049     {0x08,   8}, {0x00,   8}, {0x1E,  16}, {0x0E,   8}, {0x26,   8},
0050     {0x06,   8}, {0x42,   8}, {0x02,   8}, {0x80,   8}, {0x00,   8},
0051     {0xFE,  16}, {0xFE,   8}, {0x7E,   8}, {0x7E,   8}, {0x3E,   8},
0052     {0x3E,   8}, {0x1E,   8}, {0x1E,   8}, {0x0E,   8}, {0x0E,   8},
0053     {0x06,   8}, {0x06,   8}, {0x02,   8}, {0x02,   8}, {0x00,   8},
0054     {0x00,   8}, {0xFE,  16}, {0xFE,   8}, {0xFE,   8}, {0xFE,   8},
0055     {0xFE,   8}, {0xFE,   8}, {0xFE,   8}, {0xFE,   8}, {0xFE,   8},
0056     {0xFE,   8}, {0xFE,   8}, {0xFE,   8}, {0xFE,   8}, {0xFE,   8},
0057     {0xFE,   8}, {0xFE,   8}, {0xFE,   8}, {0xFE,   8}, {0x7E,   8},
0058     {0x7E,   8}, {0x3E,   8}, {0x3E,   8}, {0x1E,   8}, {0x1E,   8},
0059     {0x0E,   8}, {0x0E,   8}, {0x06,   8}, {0x06,   8}, {0x02,   8},
0060     {0x02,   8}, {0x00,   8}, {0x00,   8}, {0xFE,  16}
0061 };
0062 
0063 /* table of attenuation values for horizontal scaling */
0064 static u8 h_attenuation[] = { 1, 2, 4, 8, 2, 4, 8, 16, 0};
0065 
0066 /* calculate horizontal scale registers */
0067 static int calculate_h_scale_registers(struct saa7146_dev *dev,
0068     int in_x, int out_x, int flip_lr,
0069     u32* hps_ctrl, u32* hps_v_gain, u32* hps_h_prescale, u32* hps_h_scale)
0070 {
0071     /* horizontal prescaler */
0072     u32 dcgx = 0, xpsc = 0, xacm = 0, cxy = 0, cxuv = 0;
0073     /* horizontal scaler */
0074     u32 xim = 0, xp = 0, xsci =0;
0075     /* vertical scale & gain */
0076     u32 pfuv = 0;
0077 
0078     /* helper variables */
0079     u32 h_atten = 0, i = 0;
0080 
0081     if ( 0 == out_x ) {
0082         return -EINVAL;
0083     }
0084 
0085     /* mask out vanity-bit */
0086     *hps_ctrl &= ~MASK_29;
0087 
0088     /* calculate prescale-(xspc)-value: [n   .. 1/2) : 1
0089                         [1/2 .. 1/3) : 2
0090                         [1/3 .. 1/4) : 3
0091                         ...     */
0092     if (in_x > out_x) {
0093         xpsc = in_x / out_x;
0094     }
0095     else {
0096         /* zooming */
0097         xpsc = 1;
0098     }
0099 
0100     /* if flip_lr-bit is set, number of pixels after
0101        horizontal prescaling must be < 384 */
0102     if ( 0 != flip_lr ) {
0103 
0104         /* set vanity bit */
0105         *hps_ctrl |= MASK_29;
0106 
0107         while (in_x / xpsc >= 384 )
0108             xpsc++;
0109     }
0110     /* if zooming is wanted, number of pixels after
0111        horizontal prescaling must be < 768 */
0112     else {
0113         while ( in_x / xpsc >= 768 )
0114             xpsc++;
0115     }
0116 
0117     /* maximum prescale is 64 (p.69) */
0118     if ( xpsc > 64 )
0119         xpsc = 64;
0120 
0121     /* keep xacm clear*/
0122     xacm = 0;
0123 
0124     /* set horizontal filter parameters (CXY = CXUV) */
0125     cxy = hps_h_coeff_tab[( (xpsc - 1) < 63 ? (xpsc - 1) : 63 )].hps_coeff;
0126     cxuv = cxy;
0127 
0128     /* calculate and set horizontal fine scale (xsci) */
0129 
0130     /* bypass the horizontal scaler ? */
0131     if ( (in_x == out_x) && ( 1 == xpsc ) )
0132         xsci = 0x400;
0133     else
0134         xsci = ( (1024 * in_x) / (out_x * xpsc) ) + xpsc;
0135 
0136     /* set start phase for horizontal fine scale (xp) to 0 */
0137     xp = 0;
0138 
0139     /* set xim, if we bypass the horizontal scaler */
0140     if ( 0x400 == xsci )
0141         xim = 1;
0142     else
0143         xim = 0;
0144 
0145     /* if the prescaler is bypassed, enable horizontal
0146        accumulation mode (xacm) and clear dcgx */
0147     if( 1 == xpsc ) {
0148         xacm = 1;
0149         dcgx = 0;
0150     } else {
0151         xacm = 0;
0152         /* get best match in the table of attenuations
0153            for horizontal scaling */
0154         h_atten = hps_h_coeff_tab[( (xpsc - 1) < 63 ? (xpsc - 1) : 63 )].weight_sum;
0155 
0156         for (i = 0; h_attenuation[i] != 0; i++) {
0157             if (h_attenuation[i] >= h_atten)
0158                 break;
0159         }
0160 
0161         dcgx = i;
0162     }
0163 
0164     /* the horizontal scaling increment controls the UV filter
0165        to reduce the bandwidth to improve the display quality,
0166        so set it ... */
0167     if ( xsci == 0x400)
0168         pfuv = 0x00;
0169     else if ( xsci < 0x600)
0170         pfuv = 0x01;
0171     else if ( xsci < 0x680)
0172         pfuv = 0x11;
0173     else if ( xsci < 0x700)
0174         pfuv = 0x22;
0175     else
0176         pfuv = 0x33;
0177 
0178 
0179     *hps_v_gain  &= MASK_W0|MASK_B2;
0180     *hps_v_gain  |= (pfuv << 24);
0181 
0182     *hps_h_scale    &= ~(MASK_W1 | 0xf000);
0183     *hps_h_scale    |= (xim << 31) | (xp << 24) | (xsci << 12);
0184 
0185     *hps_h_prescale |= (dcgx << 27) | ((xpsc-1) << 18) | (xacm << 17) | (cxy << 8) | (cxuv << 0);
0186 
0187     return 0;
0188 }
0189 
0190 static struct {
0191     u16 hps_coeff;
0192     u16 weight_sum;
0193 } hps_v_coeff_tab [] = {
0194  {0x0100,   2},  {0x0102,   4},  {0x0300,   4},  {0x0106,   8},  {0x0502,   8},
0195  {0x0708,   8},  {0x0F00,   8},  {0x011E,  16},  {0x110E,  16},  {0x1926,  16},
0196  {0x3906,  16},  {0x3D42,  16},  {0x7D02,  16},  {0x7F80,  16},  {0xFF00,  16},
0197  {0x01FE,  32},  {0x01FE,  32},  {0x817E,  32},  {0x817E,  32},  {0xC13E,  32},
0198  {0xC13E,  32},  {0xE11E,  32},  {0xE11E,  32},  {0xF10E,  32},  {0xF10E,  32},
0199  {0xF906,  32},  {0xF906,  32},  {0xFD02,  32},  {0xFD02,  32},  {0xFF00,  32},
0200  {0xFF00,  32},  {0x01FE,  64},  {0x01FE,  64},  {0x01FE,  64},  {0x01FE,  64},
0201  {0x01FE,  64},  {0x01FE,  64},  {0x01FE,  64},  {0x01FE,  64},  {0x01FE,  64},
0202  {0x01FE,  64},  {0x01FE,  64},  {0x01FE,  64},  {0x01FE,  64},  {0x01FE,  64},
0203  {0x01FE,  64},  {0x01FE,  64},  {0x01FE,  64},  {0x01FE,  64},  {0x817E,  64},
0204  {0x817E,  64},  {0xC13E,  64},  {0xC13E,  64},  {0xE11E,  64},  {0xE11E,  64},
0205  {0xF10E,  64},  {0xF10E,  64},  {0xF906,  64},  {0xF906,  64},  {0xFD02,  64},
0206  {0xFD02,  64},  {0xFF00,  64},  {0xFF00,  64},  {0x01FE, 128}
0207 };
0208 
0209 /* table of attenuation values for vertical scaling */
0210 static u16 v_attenuation[] = { 2, 4, 8, 16, 32, 64, 128, 256, 0};
0211 
0212 /* calculate vertical scale registers */
0213 static int calculate_v_scale_registers(struct saa7146_dev *dev, enum v4l2_field field,
0214     int in_y, int out_y, u32* hps_v_scale, u32* hps_v_gain)
0215 {
0216     int lpi = 0;
0217 
0218     /* vertical scaling */
0219     u32 yacm = 0, ysci = 0, yacl = 0, ypo = 0, ype = 0;
0220     /* vertical scale & gain */
0221     u32 dcgy = 0, cya_cyb = 0;
0222 
0223     /* helper variables */
0224     u32 v_atten = 0, i = 0;
0225 
0226     /* error, if vertical zooming */
0227     if ( in_y < out_y ) {
0228         return -EINVAL;
0229     }
0230 
0231     /* linear phase interpolation may be used
0232        if scaling is between 1 and 1/2 (both fields used)
0233        or scaling is between 1/2 and 1/4 (if only one field is used) */
0234 
0235     if (V4L2_FIELD_HAS_BOTH(field)) {
0236         if( 2*out_y >= in_y) {
0237             lpi = 1;
0238         }
0239     } else if (field == V4L2_FIELD_TOP
0240         || field == V4L2_FIELD_ALTERNATE
0241         || field == V4L2_FIELD_BOTTOM) {
0242         if( 4*out_y >= in_y ) {
0243             lpi = 1;
0244         }
0245         out_y *= 2;
0246     }
0247     if( 0 != lpi ) {
0248 
0249         yacm = 0;
0250         yacl = 0;
0251         cya_cyb = 0x00ff;
0252 
0253         /* calculate scaling increment */
0254         if ( in_y > out_y )
0255             ysci = ((1024 * in_y) / (out_y + 1)) - 1024;
0256         else
0257             ysci = 0;
0258 
0259         dcgy = 0;
0260 
0261         /* calculate ype and ypo */
0262         ype = ysci / 16;
0263         ypo = ype + (ysci / 64);
0264 
0265     } else {
0266         yacm = 1;
0267 
0268         /* calculate scaling increment */
0269         ysci = (((10 * 1024 * (in_y - out_y - 1)) / in_y) + 9) / 10;
0270 
0271         /* calculate ype and ypo */
0272         ypo = ype = ((ysci + 15) / 16);
0273 
0274         /* the sequence length interval (yacl) has to be set according
0275            to the prescale value, e.g.  [n   .. 1/2) : 0
0276                         [1/2 .. 1/3) : 1
0277                         [1/3 .. 1/4) : 2
0278                         ... */
0279         if ( ysci < 512) {
0280             yacl = 0;
0281         } else {
0282             yacl = ( ysci / (1024 - ysci) );
0283         }
0284 
0285         /* get filter coefficients for cya, cyb from table hps_v_coeff_tab */
0286         cya_cyb = hps_v_coeff_tab[ (yacl < 63 ? yacl : 63 ) ].hps_coeff;
0287 
0288         /* get best match in the table of attenuations for vertical scaling */
0289         v_atten = hps_v_coeff_tab[ (yacl < 63 ? yacl : 63 ) ].weight_sum;
0290 
0291         for (i = 0; v_attenuation[i] != 0; i++) {
0292             if (v_attenuation[i] >= v_atten)
0293                 break;
0294         }
0295 
0296         dcgy = i;
0297     }
0298 
0299     /* ypo and ype swapped in spec ? */
0300     *hps_v_scale    |= (yacm << 31) | (ysci << 21) | (yacl << 15) | (ypo << 8 ) | (ype << 1);
0301 
0302     *hps_v_gain &= ~(MASK_W0|MASK_B2);
0303     *hps_v_gain |= (dcgy << 16) | (cya_cyb << 0);
0304 
0305     return 0;
0306 }
0307 
0308 /* simple bubble-sort algorithm with duplicate elimination */
0309 static int sort_and_eliminate(u32* values, int* count)
0310 {
0311     int low = 0, high = 0, top = 0;
0312     int cur = 0, next = 0;
0313 
0314     /* sanity checks */
0315     if( (0 > *count) || (NULL == values) ) {
0316         return -EINVAL;
0317     }
0318 
0319     /* bubble sort the first @count items of the array @values */
0320     for( top = *count; top > 0; top--) {
0321         for( low = 0, high = 1; high < top; low++, high++) {
0322             if( values[low] > values[high] )
0323                 swap(values[low], values[high]);
0324         }
0325     }
0326 
0327     /* remove duplicate items */
0328     for( cur = 0, next = 1; next < *count; next++) {
0329         if( values[cur] != values[next])
0330             values[++cur] = values[next];
0331     }
0332 
0333     *count = cur + 1;
0334 
0335     return 0;
0336 }
0337 
0338 static void calculate_clipping_registers_rect(struct saa7146_dev *dev, struct saa7146_fh *fh,
0339     struct saa7146_video_dma *vdma2, u32* clip_format, u32* arbtr_ctrl, enum v4l2_field field)
0340 {
0341     struct saa7146_vv *vv = dev->vv_data;
0342     __le32 *clipping = vv->d_clipping.cpu_addr;
0343 
0344     int width = vv->ov.win.w.width;
0345     int height =  vv->ov.win.w.height;
0346     int clipcount = vv->ov.nclips;
0347 
0348     u32 line_list[32];
0349     u32 pixel_list[32];
0350     int numdwords = 0;
0351 
0352     int i = 0, j = 0;
0353     int cnt_line = 0, cnt_pixel = 0;
0354 
0355     int x[32], y[32], w[32], h[32];
0356 
0357     /* clear out memory */
0358     memset(&line_list[0],  0x00, sizeof(u32)*32);
0359     memset(&pixel_list[0], 0x00, sizeof(u32)*32);
0360     memset(clipping,  0x00, SAA7146_CLIPPING_MEM);
0361 
0362     /* fill the line and pixel-lists */
0363     for(i = 0; i < clipcount; i++) {
0364         int l = 0, r = 0, t = 0, b = 0;
0365 
0366         x[i] = vv->ov.clips[i].c.left;
0367         y[i] = vv->ov.clips[i].c.top;
0368         w[i] = vv->ov.clips[i].c.width;
0369         h[i] = vv->ov.clips[i].c.height;
0370 
0371         if( w[i] < 0) {
0372             x[i] += w[i]; w[i] = -w[i];
0373         }
0374         if( h[i] < 0) {
0375             y[i] += h[i]; h[i] = -h[i];
0376         }
0377         if( x[i] < 0) {
0378             w[i] += x[i]; x[i] = 0;
0379         }
0380         if( y[i] < 0) {
0381             h[i] += y[i]; y[i] = 0;
0382         }
0383         if( 0 != vv->vflip ) {
0384             y[i] = height - y[i] - h[i];
0385         }
0386 
0387         l = x[i];
0388         r = x[i]+w[i];
0389         t = y[i];
0390         b = y[i]+h[i];
0391 
0392         /* insert left/right coordinates */
0393         pixel_list[ 2*i   ] = min_t(int, l, width);
0394         pixel_list[(2*i)+1] = min_t(int, r, width);
0395         /* insert top/bottom coordinates */
0396         line_list[ 2*i   ] = min_t(int, t, height);
0397         line_list[(2*i)+1] = min_t(int, b, height);
0398     }
0399 
0400     /* sort and eliminate lists */
0401     cnt_line = cnt_pixel = 2*clipcount;
0402     sort_and_eliminate( &pixel_list[0], &cnt_pixel );
0403     sort_and_eliminate( &line_list[0], &cnt_line );
0404 
0405     /* calculate the number of used u32s */
0406     numdwords = max_t(int, (cnt_line+1), (cnt_pixel+1))*2;
0407     numdwords = max_t(int, 4, numdwords);
0408     numdwords = min_t(int, 64, numdwords);
0409 
0410     /* fill up cliptable */
0411     for(i = 0; i < cnt_pixel; i++) {
0412         clipping[2*i] |= cpu_to_le32(pixel_list[i] << 16);
0413     }
0414     for(i = 0; i < cnt_line; i++) {
0415         clipping[(2*i)+1] |= cpu_to_le32(line_list[i] << 16);
0416     }
0417 
0418     /* fill up cliptable with the display infos */
0419     for(j = 0; j < clipcount; j++) {
0420 
0421         for(i = 0; i < cnt_pixel; i++) {
0422 
0423             if( x[j] < 0)
0424                 x[j] = 0;
0425 
0426             if( pixel_list[i] < (x[j] + w[j])) {
0427 
0428                 if ( pixel_list[i] >= x[j] ) {
0429                     clipping[2*i] |= cpu_to_le32(1 << j);
0430                 }
0431             }
0432         }
0433         for(i = 0; i < cnt_line; i++) {
0434 
0435             if( y[j] < 0)
0436                 y[j] = 0;
0437 
0438             if( line_list[i] < (y[j] + h[j]) ) {
0439 
0440                 if( line_list[i] >= y[j] ) {
0441                     clipping[(2*i)+1] |= cpu_to_le32(1 << j);
0442                 }
0443             }
0444         }
0445     }
0446 
0447     /* adjust arbitration control register */
0448     *arbtr_ctrl &= 0xffff00ff;
0449     *arbtr_ctrl |= 0x00001c00;
0450 
0451     vdma2->base_even    = vv->d_clipping.dma_handle;
0452     vdma2->base_odd     = vv->d_clipping.dma_handle;
0453     vdma2->prot_addr    = vv->d_clipping.dma_handle+((sizeof(u32))*(numdwords));
0454     vdma2->base_page    = 0x04;
0455     vdma2->pitch        = 0x00;
0456     vdma2->num_line_byte    = (0 << 16 | (sizeof(u32))*(numdwords-1) );
0457 
0458     /* set clipping-mode. this depends on the field(s) used */
0459     *clip_format &= 0xfffffff7;
0460     if (V4L2_FIELD_HAS_BOTH(field)) {
0461         *clip_format |= 0x00000008;
0462     } else {
0463         *clip_format |= 0x00000000;
0464     }
0465 }
0466 
0467 /* disable clipping */
0468 static void saa7146_disable_clipping(struct saa7146_dev *dev)
0469 {
0470     u32 clip_format = saa7146_read(dev, CLIP_FORMAT_CTRL);
0471 
0472     /* mask out relevant bits (=lower word)*/
0473     clip_format &= MASK_W1;
0474 
0475     /* upload clipping-registers*/
0476     saa7146_write(dev, CLIP_FORMAT_CTRL,clip_format);
0477     saa7146_write(dev, MC2, (MASK_05 | MASK_21));
0478 
0479     /* disable video dma2 */
0480     saa7146_write(dev, MC1, MASK_21);
0481 }
0482 
0483 static void saa7146_set_clipping_rect(struct saa7146_fh *fh)
0484 {
0485     struct saa7146_dev *dev = fh->dev;
0486     struct saa7146_vv *vv = dev->vv_data;
0487     enum v4l2_field field = vv->ov.win.field;
0488     struct  saa7146_video_dma vdma2;
0489     u32 clip_format;
0490     u32 arbtr_ctrl;
0491 
0492     /* check clipcount, disable clipping if clipcount == 0*/
0493     if (vv->ov.nclips == 0) {
0494         saa7146_disable_clipping(dev);
0495         return;
0496     }
0497 
0498     clip_format = saa7146_read(dev, CLIP_FORMAT_CTRL);
0499     arbtr_ctrl = saa7146_read(dev, PCI_BT_V1);
0500 
0501     calculate_clipping_registers_rect(dev, fh, &vdma2, &clip_format, &arbtr_ctrl, field);
0502 
0503     /* set clipping format */
0504     clip_format &= 0xffff0008;
0505     clip_format |= (SAA7146_CLIPPING_RECT << 4);
0506 
0507     /* prepare video dma2 */
0508     saa7146_write(dev, BASE_EVEN2,      vdma2.base_even);
0509     saa7146_write(dev, BASE_ODD2,       vdma2.base_odd);
0510     saa7146_write(dev, PROT_ADDR2,      vdma2.prot_addr);
0511     saa7146_write(dev, BASE_PAGE2,      vdma2.base_page);
0512     saa7146_write(dev, PITCH2,      vdma2.pitch);
0513     saa7146_write(dev, NUM_LINE_BYTE2,  vdma2.num_line_byte);
0514 
0515     /* prepare the rest */
0516     saa7146_write(dev, CLIP_FORMAT_CTRL,clip_format);
0517     saa7146_write(dev, PCI_BT_V1, arbtr_ctrl);
0518 
0519     /* upload clip_control-register, clipping-registers, enable video dma2 */
0520     saa7146_write(dev, MC2, (MASK_05 | MASK_21 | MASK_03 | MASK_19));
0521     saa7146_write(dev, MC1, (MASK_05 | MASK_21));
0522 }
0523 
0524 static void saa7146_set_window(struct saa7146_dev *dev, int width, int height, enum v4l2_field field)
0525 {
0526     struct saa7146_vv *vv = dev->vv_data;
0527 
0528     int source = vv->current_hps_source;
0529     int sync = vv->current_hps_sync;
0530 
0531     u32 hps_v_scale = 0, hps_v_gain  = 0, hps_ctrl = 0, hps_h_prescale = 0, hps_h_scale = 0;
0532 
0533     /* set vertical scale */
0534     hps_v_scale = 0; /* all bits get set by the function-call */
0535     hps_v_gain  = 0; /* fixme: saa7146_read(dev, HPS_V_GAIN);*/
0536     calculate_v_scale_registers(dev, field, vv->standard->v_field*2, height, &hps_v_scale, &hps_v_gain);
0537 
0538     /* set horizontal scale */
0539     hps_ctrl    = 0;
0540     hps_h_prescale  = 0; /* all bits get set in the function */
0541     hps_h_scale = 0;
0542     calculate_h_scale_registers(dev, vv->standard->h_pixels, width, vv->hflip, &hps_ctrl, &hps_v_gain, &hps_h_prescale, &hps_h_scale);
0543 
0544     /* set hyo and hxo */
0545     calculate_hxo_and_hyo(vv, &hps_h_scale, &hps_ctrl);
0546     calculate_hps_source_and_sync(dev, source, sync, &hps_ctrl);
0547 
0548     /* write out new register contents */
0549     saa7146_write(dev, HPS_V_SCALE, hps_v_scale);
0550     saa7146_write(dev, HPS_V_GAIN,  hps_v_gain);
0551     saa7146_write(dev, HPS_CTRL,    hps_ctrl);
0552     saa7146_write(dev, HPS_H_PRESCALE,hps_h_prescale);
0553     saa7146_write(dev, HPS_H_SCALE, hps_h_scale);
0554 
0555     /* upload shadow-ram registers */
0556     saa7146_write(dev, MC2, (MASK_05 | MASK_06 | MASK_21 | MASK_22) );
0557 }
0558 
0559 /* calculate the new memory offsets for a desired position */
0560 static void saa7146_set_position(struct saa7146_dev *dev, int w_x, int w_y, int w_height, enum v4l2_field field, u32 pixelformat)
0561 {
0562     struct saa7146_vv *vv = dev->vv_data;
0563     struct saa7146_format *sfmt = saa7146_format_by_fourcc(dev, pixelformat);
0564 
0565     int b_depth = vv->ov_fmt->depth;
0566     int b_bpl = vv->ov_fb.fmt.bytesperline;
0567     /* The unsigned long cast is to remove a 64-bit compile warning since
0568        it looks like a 64-bit address is cast to a 32-bit value, even
0569        though the base pointer is really a 32-bit physical address that
0570        goes into a 32-bit DMA register.
0571        FIXME: might not work on some 64-bit platforms, but see the FIXME
0572        in struct v4l2_framebuffer (videodev2.h) for that.
0573      */
0574     u32 base = (u32)(unsigned long)vv->ov_fb.base;
0575 
0576     struct  saa7146_video_dma vdma1;
0577 
0578     /* calculate memory offsets for picture, look if we shall top-down-flip */
0579     vdma1.pitch = 2*b_bpl;
0580     if ( 0 == vv->vflip ) {
0581         vdma1.base_even = base + (w_y * (vdma1.pitch/2)) + (w_x * (b_depth / 8));
0582         vdma1.base_odd  = vdma1.base_even + (vdma1.pitch / 2);
0583         vdma1.prot_addr = vdma1.base_even + (w_height * (vdma1.pitch / 2));
0584     }
0585     else {
0586         vdma1.base_even = base + ((w_y+w_height) * (vdma1.pitch/2)) + (w_x * (b_depth / 8));
0587         vdma1.base_odd  = vdma1.base_even - (vdma1.pitch / 2);
0588         vdma1.prot_addr = vdma1.base_odd - (w_height * (vdma1.pitch / 2));
0589     }
0590 
0591     if (V4L2_FIELD_HAS_BOTH(field)) {
0592     } else if (field == V4L2_FIELD_ALTERNATE) {
0593         /* fixme */
0594         vdma1.base_odd = vdma1.prot_addr;
0595         vdma1.pitch /= 2;
0596     } else if (field == V4L2_FIELD_TOP) {
0597         vdma1.base_odd = vdma1.prot_addr;
0598         vdma1.pitch /= 2;
0599     } else if (field == V4L2_FIELD_BOTTOM) {
0600         vdma1.base_odd = vdma1.base_even;
0601         vdma1.base_even = vdma1.prot_addr;
0602         vdma1.pitch /= 2;
0603     }
0604 
0605     if ( 0 != vv->vflip ) {
0606         vdma1.pitch *= -1;
0607     }
0608 
0609     vdma1.base_page = sfmt->swap;
0610     vdma1.num_line_byte = (vv->standard->v_field<<16)+vv->standard->h_pixels;
0611 
0612     saa7146_write_out_dma(dev, 1, &vdma1);
0613 }
0614 
0615 static void saa7146_set_output_format(struct saa7146_dev *dev, unsigned long palette)
0616 {
0617     u32 clip_format = saa7146_read(dev, CLIP_FORMAT_CTRL);
0618 
0619     /* call helper function */
0620     calculate_output_format_register(dev,palette,&clip_format);
0621 
0622     /* update the hps registers */
0623     saa7146_write(dev, CLIP_FORMAT_CTRL, clip_format);
0624     saa7146_write(dev, MC2, (MASK_05 | MASK_21));
0625 }
0626 
0627 /* select input-source */
0628 void saa7146_set_hps_source_and_sync(struct saa7146_dev *dev, int source, int sync)
0629 {
0630     struct saa7146_vv *vv = dev->vv_data;
0631     u32 hps_ctrl = 0;
0632 
0633     /* read old state */
0634     hps_ctrl = saa7146_read(dev, HPS_CTRL);
0635 
0636     hps_ctrl &= ~( MASK_31 | MASK_30 | MASK_28 );
0637     hps_ctrl |= (source << 30) | (sync << 28);
0638 
0639     /* write back & upload register */
0640     saa7146_write(dev, HPS_CTRL, hps_ctrl);
0641     saa7146_write(dev, MC2, (MASK_05 | MASK_21));
0642 
0643     vv->current_hps_source = source;
0644     vv->current_hps_sync = sync;
0645 }
0646 EXPORT_SYMBOL_GPL(saa7146_set_hps_source_and_sync);
0647 
0648 int saa7146_enable_overlay(struct saa7146_fh *fh)
0649 {
0650     struct saa7146_dev *dev = fh->dev;
0651     struct saa7146_vv *vv = dev->vv_data;
0652 
0653     saa7146_set_window(dev, vv->ov.win.w.width, vv->ov.win.w.height, vv->ov.win.field);
0654     saa7146_set_position(dev, vv->ov.win.w.left, vv->ov.win.w.top, vv->ov.win.w.height, vv->ov.win.field, vv->ov_fmt->pixelformat);
0655     saa7146_set_output_format(dev, vv->ov_fmt->trans);
0656     saa7146_set_clipping_rect(fh);
0657 
0658     /* enable video dma1 */
0659     saa7146_write(dev, MC1, (MASK_06 | MASK_22));
0660     return 0;
0661 }
0662 
0663 void saa7146_disable_overlay(struct saa7146_fh *fh)
0664 {
0665     struct saa7146_dev *dev = fh->dev;
0666 
0667     /* disable clipping + video dma1 */
0668     saa7146_disable_clipping(dev);
0669     saa7146_write(dev, MC1, MASK_22);
0670 }
0671 
0672 void saa7146_write_out_dma(struct saa7146_dev* dev, int which, struct saa7146_video_dma* vdma)
0673 {
0674     int where = 0;
0675 
0676     if( which < 1 || which > 3) {
0677         return;
0678     }
0679 
0680     /* calculate starting address */
0681     where  = (which-1)*0x18;
0682 
0683     saa7146_write(dev, where,   vdma->base_odd);
0684     saa7146_write(dev, where+0x04,  vdma->base_even);
0685     saa7146_write(dev, where+0x08,  vdma->prot_addr);
0686     saa7146_write(dev, where+0x0c,  vdma->pitch);
0687     saa7146_write(dev, where+0x10,  vdma->base_page);
0688     saa7146_write(dev, where+0x14,  vdma->num_line_byte);
0689 
0690     /* upload */
0691     saa7146_write(dev, MC2, (MASK_02<<(which-1))|(MASK_18<<(which-1)));
0692 /*
0693     printk("vdma%d.base_even:     0x%08x\n", which,vdma->base_even);
0694     printk("vdma%d.base_odd:      0x%08x\n", which,vdma->base_odd);
0695     printk("vdma%d.prot_addr:     0x%08x\n", which,vdma->prot_addr);
0696     printk("vdma%d.base_page:     0x%08x\n", which,vdma->base_page);
0697     printk("vdma%d.pitch:         0x%08x\n", which,vdma->pitch);
0698     printk("vdma%d.num_line_byte: 0x%08x\n", which,vdma->num_line_byte);
0699 */
0700 }
0701 
0702 static int calculate_video_dma_grab_packed(struct saa7146_dev* dev, struct saa7146_buf *buf)
0703 {
0704     struct saa7146_vv *vv = dev->vv_data;
0705     struct saa7146_video_dma vdma1;
0706 
0707     struct saa7146_format *sfmt = saa7146_format_by_fourcc(dev,buf->fmt->pixelformat);
0708 
0709     int width = buf->fmt->width;
0710     int height = buf->fmt->height;
0711     int bytesperline = buf->fmt->bytesperline;
0712     enum v4l2_field field = buf->fmt->field;
0713 
0714     int depth = sfmt->depth;
0715 
0716     DEB_CAP("[size=%dx%d,fields=%s]\n",
0717         width, height, v4l2_field_names[field]);
0718 
0719     if( bytesperline != 0) {
0720         vdma1.pitch = bytesperline*2;
0721     } else {
0722         vdma1.pitch = (width*depth*2)/8;
0723     }
0724     vdma1.num_line_byte = ((vv->standard->v_field<<16) + vv->standard->h_pixels);
0725     vdma1.base_page     = buf->pt[0].dma | ME1 | sfmt->swap;
0726 
0727     if( 0 != vv->vflip ) {
0728         vdma1.prot_addr = buf->pt[0].offset;
0729         vdma1.base_even = buf->pt[0].offset+(vdma1.pitch/2)*height;
0730         vdma1.base_odd  = vdma1.base_even - (vdma1.pitch/2);
0731     } else {
0732         vdma1.base_even = buf->pt[0].offset;
0733         vdma1.base_odd  = vdma1.base_even + (vdma1.pitch/2);
0734         vdma1.prot_addr = buf->pt[0].offset+(vdma1.pitch/2)*height;
0735     }
0736 
0737     if (V4L2_FIELD_HAS_BOTH(field)) {
0738     } else if (field == V4L2_FIELD_ALTERNATE) {
0739         /* fixme */
0740         if ( vv->last_field == V4L2_FIELD_TOP ) {
0741             vdma1.base_odd  = vdma1.prot_addr;
0742             vdma1.pitch /= 2;
0743         } else if ( vv->last_field == V4L2_FIELD_BOTTOM ) {
0744             vdma1.base_odd  = vdma1.base_even;
0745             vdma1.base_even = vdma1.prot_addr;
0746             vdma1.pitch /= 2;
0747         }
0748     } else if (field == V4L2_FIELD_TOP) {
0749         vdma1.base_odd  = vdma1.prot_addr;
0750         vdma1.pitch /= 2;
0751     } else if (field == V4L2_FIELD_BOTTOM) {
0752         vdma1.base_odd  = vdma1.base_even;
0753         vdma1.base_even = vdma1.prot_addr;
0754         vdma1.pitch /= 2;
0755     }
0756 
0757     if( 0 != vv->vflip ) {
0758         vdma1.pitch *= -1;
0759     }
0760 
0761     saa7146_write_out_dma(dev, 1, &vdma1);
0762     return 0;
0763 }
0764 
0765 static int calc_planar_422(struct saa7146_vv *vv, struct saa7146_buf *buf, struct saa7146_video_dma *vdma2, struct saa7146_video_dma *vdma3)
0766 {
0767     int height = buf->fmt->height;
0768     int width = buf->fmt->width;
0769 
0770     vdma2->pitch    = width;
0771     vdma3->pitch    = width;
0772 
0773     /* fixme: look at bytesperline! */
0774 
0775     if( 0 != vv->vflip ) {
0776         vdma2->prot_addr    = buf->pt[1].offset;
0777         vdma2->base_even    = ((vdma2->pitch/2)*height)+buf->pt[1].offset;
0778         vdma2->base_odd     = vdma2->base_even - (vdma2->pitch/2);
0779 
0780         vdma3->prot_addr    = buf->pt[2].offset;
0781         vdma3->base_even    = ((vdma3->pitch/2)*height)+buf->pt[2].offset;
0782         vdma3->base_odd     = vdma3->base_even - (vdma3->pitch/2);
0783     } else {
0784         vdma3->base_even    = buf->pt[2].offset;
0785         vdma3->base_odd     = vdma3->base_even + (vdma3->pitch/2);
0786         vdma3->prot_addr    = (vdma3->pitch/2)*height+buf->pt[2].offset;
0787 
0788         vdma2->base_even    = buf->pt[1].offset;
0789         vdma2->base_odd     = vdma2->base_even + (vdma2->pitch/2);
0790         vdma2->prot_addr    = (vdma2->pitch/2)*height+buf->pt[1].offset;
0791     }
0792 
0793     return 0;
0794 }
0795 
0796 static int calc_planar_420(struct saa7146_vv *vv, struct saa7146_buf *buf, struct saa7146_video_dma *vdma2, struct saa7146_video_dma *vdma3)
0797 {
0798     int height = buf->fmt->height;
0799     int width = buf->fmt->width;
0800 
0801     vdma2->pitch    = width/2;
0802     vdma3->pitch    = width/2;
0803 
0804     if( 0 != vv->vflip ) {
0805         vdma2->prot_addr    = buf->pt[2].offset;
0806         vdma2->base_even    = ((vdma2->pitch/2)*height)+buf->pt[2].offset;
0807         vdma2->base_odd     = vdma2->base_even - (vdma2->pitch/2);
0808 
0809         vdma3->prot_addr    = buf->pt[1].offset;
0810         vdma3->base_even    = ((vdma3->pitch/2)*height)+buf->pt[1].offset;
0811         vdma3->base_odd     = vdma3->base_even - (vdma3->pitch/2);
0812 
0813     } else {
0814         vdma3->base_even    = buf->pt[2].offset;
0815         vdma3->base_odd     = vdma3->base_even + (vdma3->pitch);
0816         vdma3->prot_addr    = (vdma3->pitch/2)*height+buf->pt[2].offset;
0817 
0818         vdma2->base_even    = buf->pt[1].offset;
0819         vdma2->base_odd     = vdma2->base_even + (vdma2->pitch);
0820         vdma2->prot_addr    = (vdma2->pitch/2)*height+buf->pt[1].offset;
0821     }
0822     return 0;
0823 }
0824 
0825 static int calculate_video_dma_grab_planar(struct saa7146_dev* dev, struct saa7146_buf *buf)
0826 {
0827     struct saa7146_vv *vv = dev->vv_data;
0828     struct saa7146_video_dma vdma1;
0829     struct saa7146_video_dma vdma2;
0830     struct saa7146_video_dma vdma3;
0831 
0832     struct saa7146_format *sfmt = saa7146_format_by_fourcc(dev,buf->fmt->pixelformat);
0833 
0834     int width = buf->fmt->width;
0835     int height = buf->fmt->height;
0836     enum v4l2_field field = buf->fmt->field;
0837 
0838     BUG_ON(0 == buf->pt[0].dma);
0839     BUG_ON(0 == buf->pt[1].dma);
0840     BUG_ON(0 == buf->pt[2].dma);
0841 
0842     DEB_CAP("[size=%dx%d,fields=%s]\n",
0843         width, height, v4l2_field_names[field]);
0844 
0845     /* fixme: look at bytesperline! */
0846 
0847     /* fixme: what happens for user space buffers here?. The offsets are
0848        most likely wrong, this version here only works for page-aligned
0849        buffers, modifications to the pagetable-functions are necessary...*/
0850 
0851     vdma1.pitch     = width*2;
0852     vdma1.num_line_byte = ((vv->standard->v_field<<16) + vv->standard->h_pixels);
0853     vdma1.base_page     = buf->pt[0].dma | ME1;
0854 
0855     if( 0 != vv->vflip ) {
0856         vdma1.prot_addr = buf->pt[0].offset;
0857         vdma1.base_even = ((vdma1.pitch/2)*height)+buf->pt[0].offset;
0858         vdma1.base_odd  = vdma1.base_even - (vdma1.pitch/2);
0859     } else {
0860         vdma1.base_even = buf->pt[0].offset;
0861         vdma1.base_odd  = vdma1.base_even + (vdma1.pitch/2);
0862         vdma1.prot_addr = (vdma1.pitch/2)*height+buf->pt[0].offset;
0863     }
0864 
0865     vdma2.num_line_byte = 0; /* unused */
0866     vdma2.base_page     = buf->pt[1].dma | ME1;
0867 
0868     vdma3.num_line_byte = 0; /* unused */
0869     vdma3.base_page     = buf->pt[2].dma | ME1;
0870 
0871     switch( sfmt->depth ) {
0872         case 12: {
0873             calc_planar_420(vv,buf,&vdma2,&vdma3);
0874             break;
0875         }
0876         case 16: {
0877             calc_planar_422(vv,buf,&vdma2,&vdma3);
0878             break;
0879         }
0880         default: {
0881             return -1;
0882         }
0883     }
0884 
0885     if (V4L2_FIELD_HAS_BOTH(field)) {
0886     } else if (field == V4L2_FIELD_ALTERNATE) {
0887         /* fixme */
0888         vdma1.base_odd  = vdma1.prot_addr;
0889         vdma1.pitch /= 2;
0890         vdma2.base_odd  = vdma2.prot_addr;
0891         vdma2.pitch /= 2;
0892         vdma3.base_odd  = vdma3.prot_addr;
0893         vdma3.pitch /= 2;
0894     } else if (field == V4L2_FIELD_TOP) {
0895         vdma1.base_odd  = vdma1.prot_addr;
0896         vdma1.pitch /= 2;
0897         vdma2.base_odd  = vdma2.prot_addr;
0898         vdma2.pitch /= 2;
0899         vdma3.base_odd  = vdma3.prot_addr;
0900         vdma3.pitch /= 2;
0901     } else if (field == V4L2_FIELD_BOTTOM) {
0902         vdma1.base_odd  = vdma1.base_even;
0903         vdma1.base_even = vdma1.prot_addr;
0904         vdma1.pitch /= 2;
0905         vdma2.base_odd  = vdma2.base_even;
0906         vdma2.base_even = vdma2.prot_addr;
0907         vdma2.pitch /= 2;
0908         vdma3.base_odd  = vdma3.base_even;
0909         vdma3.base_even = vdma3.prot_addr;
0910         vdma3.pitch /= 2;
0911     }
0912 
0913     if( 0 != vv->vflip ) {
0914         vdma1.pitch *= -1;
0915         vdma2.pitch *= -1;
0916         vdma3.pitch *= -1;
0917     }
0918 
0919     saa7146_write_out_dma(dev, 1, &vdma1);
0920     if( (sfmt->flags & FORMAT_BYTE_SWAP) != 0 ) {
0921         saa7146_write_out_dma(dev, 3, &vdma2);
0922         saa7146_write_out_dma(dev, 2, &vdma3);
0923     } else {
0924         saa7146_write_out_dma(dev, 2, &vdma2);
0925         saa7146_write_out_dma(dev, 3, &vdma3);
0926     }
0927     return 0;
0928 }
0929 
0930 static void program_capture_engine(struct saa7146_dev *dev, int planar)
0931 {
0932     struct saa7146_vv *vv = dev->vv_data;
0933     int count = 0;
0934 
0935     unsigned long e_wait = vv->current_hps_sync == SAA7146_HPS_SYNC_PORT_A ? CMD_E_FID_A : CMD_E_FID_B;
0936     unsigned long o_wait = vv->current_hps_sync == SAA7146_HPS_SYNC_PORT_A ? CMD_O_FID_A : CMD_O_FID_B;
0937 
0938     /* wait for o_fid_a/b / e_fid_a/b toggle only if rps register 0 is not set*/
0939     WRITE_RPS0(CMD_PAUSE | CMD_OAN | CMD_SIG0 | o_wait);
0940     WRITE_RPS0(CMD_PAUSE | CMD_OAN | CMD_SIG0 | e_wait);
0941 
0942     /* set rps register 0 */
0943     WRITE_RPS0(CMD_WR_REG | (1 << 8) | (MC2/4));
0944     WRITE_RPS0(MASK_27 | MASK_11);
0945 
0946     /* turn on video-dma1 */
0947     WRITE_RPS0(CMD_WR_REG_MASK | (MC1/4));
0948     WRITE_RPS0(MASK_06 | MASK_22);          /* => mask */
0949     WRITE_RPS0(MASK_06 | MASK_22);          /* => values */
0950     if( 0 != planar ) {
0951         /* turn on video-dma2 */
0952         WRITE_RPS0(CMD_WR_REG_MASK | (MC1/4));
0953         WRITE_RPS0(MASK_05 | MASK_21);          /* => mask */
0954         WRITE_RPS0(MASK_05 | MASK_21);          /* => values */
0955 
0956         /* turn on video-dma3 */
0957         WRITE_RPS0(CMD_WR_REG_MASK | (MC1/4));
0958         WRITE_RPS0(MASK_04 | MASK_20);          /* => mask */
0959         WRITE_RPS0(MASK_04 | MASK_20);          /* => values */
0960     }
0961 
0962     /* wait for o_fid_a/b / e_fid_a/b toggle */
0963     if ( vv->last_field == V4L2_FIELD_INTERLACED ) {
0964         WRITE_RPS0(CMD_PAUSE | o_wait);
0965         WRITE_RPS0(CMD_PAUSE | e_wait);
0966     } else if ( vv->last_field == V4L2_FIELD_TOP ) {
0967         WRITE_RPS0(CMD_PAUSE | (vv->current_hps_sync == SAA7146_HPS_SYNC_PORT_A ? MASK_10 : MASK_09));
0968         WRITE_RPS0(CMD_PAUSE | o_wait);
0969     } else if ( vv->last_field == V4L2_FIELD_BOTTOM ) {
0970         WRITE_RPS0(CMD_PAUSE | (vv->current_hps_sync == SAA7146_HPS_SYNC_PORT_A ? MASK_10 : MASK_09));
0971         WRITE_RPS0(CMD_PAUSE | e_wait);
0972     }
0973 
0974     /* turn off video-dma1 */
0975     WRITE_RPS0(CMD_WR_REG_MASK | (MC1/4));
0976     WRITE_RPS0(MASK_22 | MASK_06);          /* => mask */
0977     WRITE_RPS0(MASK_22);                /* => values */
0978     if( 0 != planar ) {
0979         /* turn off video-dma2 */
0980         WRITE_RPS0(CMD_WR_REG_MASK | (MC1/4));
0981         WRITE_RPS0(MASK_05 | MASK_21);          /* => mask */
0982         WRITE_RPS0(MASK_21);                /* => values */
0983 
0984         /* turn off video-dma3 */
0985         WRITE_RPS0(CMD_WR_REG_MASK | (MC1/4));
0986         WRITE_RPS0(MASK_04 | MASK_20);          /* => mask */
0987         WRITE_RPS0(MASK_20);                /* => values */
0988     }
0989 
0990     /* generate interrupt */
0991     WRITE_RPS0(CMD_INTERRUPT);
0992 
0993     /* stop */
0994     WRITE_RPS0(CMD_STOP);
0995 }
0996 
0997 void saa7146_set_capture(struct saa7146_dev *dev, struct saa7146_buf *buf, struct saa7146_buf *next)
0998 {
0999     struct saa7146_format *sfmt = saa7146_format_by_fourcc(dev,buf->fmt->pixelformat);
1000     struct saa7146_vv *vv = dev->vv_data;
1001     u32 vdma1_prot_addr;
1002 
1003     DEB_CAP("buf:%p, next:%p\n", buf, next);
1004 
1005     vdma1_prot_addr = saa7146_read(dev, PROT_ADDR1);
1006     if( 0 == vdma1_prot_addr ) {
1007         /* clear out beginning of streaming bit (rps register 0)*/
1008         DEB_CAP("forcing sync to new frame\n");
1009         saa7146_write(dev, MC2, MASK_27 );
1010     }
1011 
1012     saa7146_set_window(dev, buf->fmt->width, buf->fmt->height, buf->fmt->field);
1013     saa7146_set_output_format(dev, sfmt->trans);
1014     saa7146_disable_clipping(dev);
1015 
1016     if ( vv->last_field == V4L2_FIELD_INTERLACED ) {
1017     } else if ( vv->last_field == V4L2_FIELD_TOP ) {
1018         vv->last_field = V4L2_FIELD_BOTTOM;
1019     } else if ( vv->last_field == V4L2_FIELD_BOTTOM ) {
1020         vv->last_field = V4L2_FIELD_TOP;
1021     }
1022 
1023     if( 0 != IS_PLANAR(sfmt->trans)) {
1024         calculate_video_dma_grab_planar(dev, buf);
1025         program_capture_engine(dev,1);
1026     } else {
1027         calculate_video_dma_grab_packed(dev, buf);
1028         program_capture_engine(dev,0);
1029     }
1030 
1031 /*
1032     printk("vdma%d.base_even:     0x%08x\n", 1,saa7146_read(dev,BASE_EVEN1));
1033     printk("vdma%d.base_odd:      0x%08x\n", 1,saa7146_read(dev,BASE_ODD1));
1034     printk("vdma%d.prot_addr:     0x%08x\n", 1,saa7146_read(dev,PROT_ADDR1));
1035     printk("vdma%d.base_page:     0x%08x\n", 1,saa7146_read(dev,BASE_PAGE1));
1036     printk("vdma%d.pitch:         0x%08x\n", 1,saa7146_read(dev,PITCH1));
1037     printk("vdma%d.num_line_byte: 0x%08x\n", 1,saa7146_read(dev,NUM_LINE_BYTE1));
1038     printk("vdma%d => vptr      : 0x%08x\n", 1,saa7146_read(dev,PCI_VDP1));
1039 */
1040 
1041     /* write the address of the rps-program */
1042     saa7146_write(dev, RPS_ADDR0, dev->d_rps0.dma_handle);
1043 
1044     /* turn on rps */
1045     saa7146_write(dev, MC1, (MASK_12 | MASK_28));
1046 }
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