OSCL-LXR linux-6.0.1/​drivers/​media/​cec/​platform/​tegra/​tegra_cec.h	Source navigation Diff markup Identifier search General search
	Version: linux-6.0.1 spark-3.0.0 hadoop-3.2.0-src hadoop-3.3.0-src spark-2.4.7 linux-4.15.13 hadoop-2.7.4-src Revert   Change

 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Tegra CEC register definitions
  *
  * The original 3.10 CEC driver using a custom API:
  *
  * Copyright (c) 2012-2015, NVIDIA CORPORATION.  All rights reserved.
  *
  * Conversion to the CEC framework and to the mainline kernel:
  *
  * Copyright 2016-2017 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
  */
 
 #ifndef TEGRA_CEC_H
 #define TEGRA_CEC_H
 
 /* CEC registers */
 #define TEGRA_CEC_SW_CONTROL    0x000
 #define TEGRA_CEC_HW_CONTROL    0x004
 #define TEGRA_CEC_INPUT_FILTER  0x008
 #define TEGRA_CEC_TX_REGISTER   0x010
 #define TEGRA_CEC_RX_REGISTER   0x014
 #define TEGRA_CEC_RX_TIMING_0   0x018
 #define TEGRA_CEC_RX_TIMING_1   0x01c
 #define TEGRA_CEC_RX_TIMING_2   0x020
 #define TEGRA_CEC_TX_TIMING_0   0x024
 #define TEGRA_CEC_TX_TIMING_1   0x028
 #define TEGRA_CEC_TX_TIMING_2   0x02c
 #define TEGRA_CEC_INT_STAT  0x030
 #define TEGRA_CEC_INT_MASK  0x034
 #define TEGRA_CEC_HW_DEBUG_RX   0x038
 #define TEGRA_CEC_HW_DEBUG_TX   0x03c
 
 #define TEGRA_CEC_HWCTRL_RX_LADDR_MASK              0x7fff
 #define TEGRA_CEC_HWCTRL_RX_LADDR(x)    \
     ((x) & TEGRA_CEC_HWCTRL_RX_LADDR_MASK)
 #define TEGRA_CEC_HWCTRL_RX_SNOOP               BIT(15)
 #define TEGRA_CEC_HWCTRL_RX_NAK_MODE                BIT(16)
 #define TEGRA_CEC_HWCTRL_TX_NAK_MODE                BIT(24)
 #define TEGRA_CEC_HWCTRL_FAST_SIM_MODE              BIT(30)
 #define TEGRA_CEC_HWCTRL_TX_RX_MODE             BIT(31)
 
 #define TEGRA_CEC_INPUT_FILTER_MODE             BIT(31)
 #define TEGRA_CEC_INPUT_FILTER_FIFO_LENGTH_SHIFT        0
 
 #define TEGRA_CEC_TX_REG_DATA_SHIFT             0
 #define TEGRA_CEC_TX_REG_EOM                    BIT(8)
 #define TEGRA_CEC_TX_REG_BCAST                  BIT(12)
 #define TEGRA_CEC_TX_REG_START_BIT              BIT(16)
 #define TEGRA_CEC_TX_REG_RETRY                  BIT(17)
 
 #define TEGRA_CEC_RX_REGISTER_SHIFT             0
 #define TEGRA_CEC_RX_REGISTER_EOM               BIT(8)
 #define TEGRA_CEC_RX_REGISTER_ACK               BIT(9)
 
 #define TEGRA_CEC_RX_TIM0_START_BIT_MAX_LO_TIME_SHIFT       0
 #define TEGRA_CEC_RX_TIM0_START_BIT_MIN_LO_TIME_SHIFT       8
 #define TEGRA_CEC_RX_TIM0_START_BIT_MAX_DURATION_SHIFT      16
 #define TEGRA_CEC_RX_TIM0_START_BIT_MIN_DURATION_SHIFT      24
 
 #define TEGRA_CEC_RX_TIM1_DATA_BIT_MAX_LO_TIME_SHIFT        0
 #define TEGRA_CEC_RX_TIM1_DATA_BIT_SAMPLE_TIME_SHIFT        8
 #define TEGRA_CEC_RX_TIM1_DATA_BIT_MAX_DURATION_SHIFT       16
 #define TEGRA_CEC_RX_TIM1_DATA_BIT_MIN_DURATION_SHIFT       24
 
 #define TEGRA_CEC_RX_TIM2_END_OF_BLOCK_TIME_SHIFT       0
 
 #define TEGRA_CEC_TX_TIM0_START_BIT_LO_TIME_SHIFT       0
 #define TEGRA_CEC_TX_TIM0_START_BIT_DURATION_SHIFT      8
 #define TEGRA_CEC_TX_TIM0_BUS_XITION_TIME_SHIFT         16
 #define TEGRA_CEC_TX_TIM0_BUS_ERROR_LO_TIME_SHIFT       24
 
 #define TEGRA_CEC_TX_TIM1_LO_DATA_BIT_LO_TIME_SHIFT     0
 #define TEGRA_CEC_TX_TIM1_HI_DATA_BIT_LO_TIME_SHIFT     8
 #define TEGRA_CEC_TX_TIM1_DATA_BIT_DURATION_SHIFT       16
 #define TEGRA_CEC_TX_TIM1_ACK_NAK_BIT_SAMPLE_TIME_SHIFT     24
 
 #define TEGRA_CEC_TX_TIM2_BUS_IDLE_TIME_ADDITIONAL_FRAME_SHIFT  0
 #define TEGRA_CEC_TX_TIM2_BUS_IDLE_TIME_NEW_FRAME_SHIFT     4
 #define TEGRA_CEC_TX_TIM2_BUS_IDLE_TIME_RETRY_FRAME_SHIFT   8
 
 #define TEGRA_CEC_INT_STAT_TX_REGISTER_EMPTY            BIT(0)
 #define TEGRA_CEC_INT_STAT_TX_REGISTER_UNDERRUN         BIT(1)
 #define TEGRA_CEC_INT_STAT_TX_FRAME_OR_BLOCK_NAKD       BIT(2)
 #define TEGRA_CEC_INT_STAT_TX_ARBITRATION_FAILED        BIT(3)
 #define TEGRA_CEC_INT_STAT_TX_BUS_ANOMALY_DETECTED      BIT(4)
 #define TEGRA_CEC_INT_STAT_TX_FRAME_TRANSMITTED         BIT(5)
 #define TEGRA_CEC_INT_STAT_RX_REGISTER_FULL         BIT(8)
 #define TEGRA_CEC_INT_STAT_RX_REGISTER_OVERRUN          BIT(9)
 #define TEGRA_CEC_INT_STAT_RX_START_BIT_DETECTED        BIT(10)
 #define TEGRA_CEC_INT_STAT_RX_BUS_ANOMALY_DETECTED      BIT(11)
 #define TEGRA_CEC_INT_STAT_RX_BUS_ERROR_DETECTED        BIT(12)
 #define TEGRA_CEC_INT_STAT_FILTERED_RX_DATA_PIN_TRANSITION_H2L  BIT(13)
 #define TEGRA_CEC_INT_STAT_FILTERED_RX_DATA_PIN_TRANSITION_L2H  BIT(14)
 
 #define TEGRA_CEC_INT_MASK_TX_REGISTER_EMPTY            BIT(0)
 #define TEGRA_CEC_INT_MASK_TX_REGISTER_UNDERRUN         BIT(1)
 #define TEGRA_CEC_INT_MASK_TX_FRAME_OR_BLOCK_NAKD       BIT(2)
 #define TEGRA_CEC_INT_MASK_TX_ARBITRATION_FAILED        BIT(3)
 #define TEGRA_CEC_INT_MASK_TX_BUS_ANOMALY_DETECTED      BIT(4)
 #define TEGRA_CEC_INT_MASK_TX_FRAME_TRANSMITTED         BIT(5)
 #define TEGRA_CEC_INT_MASK_RX_REGISTER_FULL         BIT(8)
 #define TEGRA_CEC_INT_MASK_RX_REGISTER_OVERRUN          BIT(9)
 #define TEGRA_CEC_INT_MASK_RX_START_BIT_DETECTED        BIT(10)
 #define TEGRA_CEC_INT_MASK_RX_BUS_ANOMALY_DETECTED      BIT(11)
 #define TEGRA_CEC_INT_MASK_RX_BUS_ERROR_DETECTED        BIT(12)
 #define TEGRA_CEC_INT_MASK_FILTERED_RX_DATA_PIN_TRANSITION_H2L  BIT(13)
 #define TEGRA_CEC_INT_MASK_FILTERED_RX_DATA_PIN_TRANSITION_L2H  BIT(14)
 
 #define TEGRA_CEC_HW_DEBUG_TX_DURATION_COUNT_SHIFT      0
 #define TEGRA_CEC_HW_DEBUG_TX_TXBIT_COUNT_SHIFT         17
 #define TEGRA_CEC_HW_DEBUG_TX_STATE_SHIFT           21
 #define TEGRA_CEC_HW_DEBUG_TX_FORCELOOUT            BIT(25)
 #define TEGRA_CEC_HW_DEBUG_TX_TXDATABIT_SAMPLE_TIMER        BIT(26)
 
 #endif /* TEGRA_CEC_H */

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