platform/tegra/tegra_cec.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Tegra CEC implementation
0004  *
0005  * The original 3.10 CEC driver using a custom API:
0006  *
0007  * Copyright (c) 2012-2015, NVIDIA CORPORATION.  All rights reserved.
0008  *
0009  * Conversion to the CEC framework and to the mainline kernel:
0010  *
0011  * Copyright 2016-2017 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
0012  */
0013
0014 #include <linux/module.h>
0015 #include <linux/kernel.h>
0016 #include <linux/err.h>
0017 #include <linux/errno.h>
0018 #include <linux/interrupt.h>
0019 #include <linux/slab.h>
0020 #include <linux/io.h>
0021 #include <linux/clk.h>
0022 #include <linux/delay.h>
0023 #include <linux/pm.h>
0024 #include <linux/of.h>
0025 #include <linux/of_platform.h>
0026 #include <linux/platform_device.h>
0027 #include <linux/clk/tegra.h>
0028
0029 #include <media/cec-notifier.h>
0030
0031 #include "tegra_cec.h"
0032
0033 #define TEGRA_CEC_NAME "tegra-cec"
0034
0035 struct tegra_cec {
0036     struct cec_adapter  *adap;
0037     struct device       *dev;
0038     struct clk      *clk;
0039     void __iomem        *cec_base;
0040     struct cec_notifier *notifier;
0041     int         tegra_cec_irq;
0042     bool            rx_done;
0043     bool            tx_done;
0044     int         tx_status;
0045     u8          rx_buf[CEC_MAX_MSG_SIZE];
0046     u8          rx_buf_cnt;
0047     u32         tx_buf[CEC_MAX_MSG_SIZE];
0048     u8          tx_buf_cur;
0049     u8          tx_buf_cnt;
0050 };
0051
0052 static inline u32 cec_read(struct tegra_cec *cec, u32 reg)
0053 {
0054     return readl(cec->cec_base + reg);
0055 }
0056
0057 static inline void cec_write(struct tegra_cec *cec, u32 reg, u32 val)
0058 {
0059     writel(val, cec->cec_base + reg);
0060 }
0061
0062 static void tegra_cec_error_recovery(struct tegra_cec *cec)
0063 {
0064     u32 hw_ctrl;
0065
0066     hw_ctrl = cec_read(cec, TEGRA_CEC_HW_CONTROL);
0067     cec_write(cec, TEGRA_CEC_HW_CONTROL, 0);
0068     cec_write(cec, TEGRA_CEC_INT_STAT, 0xffffffff);
0069     cec_write(cec, TEGRA_CEC_HW_CONTROL, hw_ctrl);
0070 }
0071
0072 static irqreturn_t tegra_cec_irq_thread_handler(int irq, void *data)
0073 {
0074     struct device *dev = data;
0075     struct tegra_cec *cec = dev_get_drvdata(dev);
0076
0077     if (cec->tx_done) {
0078         cec_transmit_attempt_done(cec->adap, cec->tx_status);
0079         cec->tx_done = false;
0080     }
0081     if (cec->rx_done) {
0082         struct cec_msg msg = {};
0083
0084         msg.len = cec->rx_buf_cnt;
0085         memcpy(msg.msg, cec->rx_buf, msg.len);
0086         cec_received_msg(cec->adap, &msg);
0087         cec->rx_done = false;
0088         cec->rx_buf_cnt = 0;
0089     }
0090     return IRQ_HANDLED;
0091 }
0092
0093 static irqreturn_t tegra_cec_irq_handler(int irq, void *data)
0094 {
0095     struct device *dev = data;
0096     struct tegra_cec *cec = dev_get_drvdata(dev);
0097     u32 status, mask;
0098
0099     status = cec_read(cec, TEGRA_CEC_INT_STAT);
0100     mask = cec_read(cec, TEGRA_CEC_INT_MASK);
0101
0102     status &= mask;
0103
0104     if (!status)
0105         return IRQ_HANDLED;
0106
0107     if (status & TEGRA_CEC_INT_STAT_TX_REGISTER_UNDERRUN) {
0108         dev_err(dev, "TX underrun, interrupt timing issue!\n");
0109
0110         tegra_cec_error_recovery(cec);
0111         cec_write(cec, TEGRA_CEC_INT_MASK,
0112               mask & ~TEGRA_CEC_INT_MASK_TX_REGISTER_EMPTY);
0113
0114         cec->tx_done = true;
0115         cec->tx_status = CEC_TX_STATUS_ERROR;
0116         return IRQ_WAKE_THREAD;
0117     }
0118
0119     if ((status & TEGRA_CEC_INT_STAT_TX_ARBITRATION_FAILED) ||
0120            (status & TEGRA_CEC_INT_STAT_TX_BUS_ANOMALY_DETECTED)) {
0121         tegra_cec_error_recovery(cec);
0122         cec_write(cec, TEGRA_CEC_INT_MASK,
0123               mask & ~TEGRA_CEC_INT_MASK_TX_REGISTER_EMPTY);
0124
0125         cec->tx_done = true;
0126         if (status & TEGRA_CEC_INT_STAT_TX_BUS_ANOMALY_DETECTED)
0127             cec->tx_status = CEC_TX_STATUS_LOW_DRIVE;
0128         else
0129             cec->tx_status = CEC_TX_STATUS_ARB_LOST;
0130         return IRQ_WAKE_THREAD;
0131     }
0132
0133     if (status & TEGRA_CEC_INT_STAT_TX_FRAME_TRANSMITTED) {
0134         cec_write(cec, TEGRA_CEC_INT_STAT,
0135               TEGRA_CEC_INT_STAT_TX_FRAME_TRANSMITTED);
0136
0137         if (status & TEGRA_CEC_INT_STAT_TX_FRAME_OR_BLOCK_NAKD) {
0138             tegra_cec_error_recovery(cec);
0139
0140             cec->tx_done = true;
0141             cec->tx_status = CEC_TX_STATUS_NACK;
0142         } else {
0143             cec->tx_done = true;
0144             cec->tx_status = CEC_TX_STATUS_OK;
0145         }
0146         return IRQ_WAKE_THREAD;
0147     }
0148
0149     if (status & TEGRA_CEC_INT_STAT_TX_FRAME_OR_BLOCK_NAKD)
0150         dev_warn(dev, "TX NAKed on the fly!\n");
0151
0152     if (status & TEGRA_CEC_INT_STAT_TX_REGISTER_EMPTY) {
0153         if (cec->tx_buf_cur == cec->tx_buf_cnt) {
0154             cec_write(cec, TEGRA_CEC_INT_MASK,
0155                   mask & ~TEGRA_CEC_INT_MASK_TX_REGISTER_EMPTY);
0156         } else {
0157             cec_write(cec, TEGRA_CEC_TX_REGISTER,
0158                   cec->tx_buf[cec->tx_buf_cur++]);
0159             cec_write(cec, TEGRA_CEC_INT_STAT,
0160                   TEGRA_CEC_INT_STAT_TX_REGISTER_EMPTY);
0161         }
0162     }
0163
0164     if (status & TEGRA_CEC_INT_STAT_RX_START_BIT_DETECTED) {
0165         cec_write(cec, TEGRA_CEC_INT_STAT,
0166               TEGRA_CEC_INT_STAT_RX_START_BIT_DETECTED);
0167         cec->rx_done = false;
0168         cec->rx_buf_cnt = 0;
0169     }
0170     if (status & TEGRA_CEC_INT_STAT_RX_REGISTER_FULL) {
0171         u32 v;
0172
0173         cec_write(cec, TEGRA_CEC_INT_STAT,
0174               TEGRA_CEC_INT_STAT_RX_REGISTER_FULL);
0175         v = cec_read(cec, TEGRA_CEC_RX_REGISTER);
0176         if (cec->rx_buf_cnt < CEC_MAX_MSG_SIZE)
0177             cec->rx_buf[cec->rx_buf_cnt++] = v & 0xff;
0178         if (v & TEGRA_CEC_RX_REGISTER_EOM) {
0179             cec->rx_done = true;
0180             return IRQ_WAKE_THREAD;
0181         }
0182     }
0183
0184     return IRQ_HANDLED;
0185 }
0186
0187 static int tegra_cec_adap_enable(struct cec_adapter *adap, bool enable)
0188 {
0189     struct tegra_cec *cec = adap->priv;
0190
0191     cec->rx_buf_cnt = 0;
0192     cec->tx_buf_cnt = 0;
0193     cec->tx_buf_cur = 0;
0194
0195     cec_write(cec, TEGRA_CEC_HW_CONTROL, 0);
0196     cec_write(cec, TEGRA_CEC_INT_MASK, 0);
0197     cec_write(cec, TEGRA_CEC_INT_STAT, 0xffffffff);
0198     cec_write(cec, TEGRA_CEC_SW_CONTROL, 0);
0199
0200     if (!enable)
0201         return 0;
0202
0203     cec_write(cec, TEGRA_CEC_INPUT_FILTER, (1U << 31) | 0x20);
0204
0205     cec_write(cec, TEGRA_CEC_RX_TIMING_0,
0206           (0x7a << TEGRA_CEC_RX_TIM0_START_BIT_MAX_LO_TIME_SHIFT) |
0207           (0x6d << TEGRA_CEC_RX_TIM0_START_BIT_MIN_LO_TIME_SHIFT) |
0208           (0x93 << TEGRA_CEC_RX_TIM0_START_BIT_MAX_DURATION_SHIFT) |
0209           (0x86 << TEGRA_CEC_RX_TIM0_START_BIT_MIN_DURATION_SHIFT));
0210
0211     cec_write(cec, TEGRA_CEC_RX_TIMING_1,
0212           (0x35 << TEGRA_CEC_RX_TIM1_DATA_BIT_MAX_LO_TIME_SHIFT) |
0213           (0x21 << TEGRA_CEC_RX_TIM1_DATA_BIT_SAMPLE_TIME_SHIFT) |
0214           (0x56 << TEGRA_CEC_RX_TIM1_DATA_BIT_MAX_DURATION_SHIFT) |
0215           (0x40 << TEGRA_CEC_RX_TIM1_DATA_BIT_MIN_DURATION_SHIFT));
0216
0217     cec_write(cec, TEGRA_CEC_RX_TIMING_2,
0218           (0x50 << TEGRA_CEC_RX_TIM2_END_OF_BLOCK_TIME_SHIFT));
0219
0220     cec_write(cec, TEGRA_CEC_TX_TIMING_0,
0221           (0x74 << TEGRA_CEC_TX_TIM0_START_BIT_LO_TIME_SHIFT) |
0222           (0x8d << TEGRA_CEC_TX_TIM0_START_BIT_DURATION_SHIFT) |
0223           (0x08 << TEGRA_CEC_TX_TIM0_BUS_XITION_TIME_SHIFT) |
0224           (0x71 << TEGRA_CEC_TX_TIM0_BUS_ERROR_LO_TIME_SHIFT));
0225
0226     cec_write(cec, TEGRA_CEC_TX_TIMING_1,
0227           (0x2f << TEGRA_CEC_TX_TIM1_LO_DATA_BIT_LO_TIME_SHIFT) |
0228           (0x13 << TEGRA_CEC_TX_TIM1_HI_DATA_BIT_LO_TIME_SHIFT) |
0229           (0x4b << TEGRA_CEC_TX_TIM1_DATA_BIT_DURATION_SHIFT) |
0230           (0x21 << TEGRA_CEC_TX_TIM1_ACK_NAK_BIT_SAMPLE_TIME_SHIFT));
0231
0232     cec_write(cec, TEGRA_CEC_TX_TIMING_2,
0233           (0x07 << TEGRA_CEC_TX_TIM2_BUS_IDLE_TIME_ADDITIONAL_FRAME_SHIFT) |
0234           (0x05 << TEGRA_CEC_TX_TIM2_BUS_IDLE_TIME_NEW_FRAME_SHIFT) |
0235           (0x03 << TEGRA_CEC_TX_TIM2_BUS_IDLE_TIME_RETRY_FRAME_SHIFT));
0236
0237     cec_write(cec, TEGRA_CEC_INT_MASK,
0238           TEGRA_CEC_INT_MASK_TX_REGISTER_UNDERRUN |
0239           TEGRA_CEC_INT_MASK_TX_FRAME_OR_BLOCK_NAKD |
0240           TEGRA_CEC_INT_MASK_TX_ARBITRATION_FAILED |
0241           TEGRA_CEC_INT_MASK_TX_BUS_ANOMALY_DETECTED |
0242           TEGRA_CEC_INT_MASK_TX_FRAME_TRANSMITTED |
0243           TEGRA_CEC_INT_MASK_RX_REGISTER_FULL |
0244           TEGRA_CEC_INT_MASK_RX_START_BIT_DETECTED);
0245
0246     cec_write(cec, TEGRA_CEC_HW_CONTROL, TEGRA_CEC_HWCTRL_TX_RX_MODE);
0247     return 0;
0248 }
0249
0250 static int tegra_cec_adap_log_addr(struct cec_adapter *adap, u8 logical_addr)
0251 {
0252     struct tegra_cec *cec = adap->priv;
0253     u32 state = cec_read(cec, TEGRA_CEC_HW_CONTROL);
0254
0255     if (logical_addr == CEC_LOG_ADDR_INVALID)
0256         state &= ~TEGRA_CEC_HWCTRL_RX_LADDR_MASK;
0257     else
0258         state |= TEGRA_CEC_HWCTRL_RX_LADDR((1 << logical_addr));
0259
0260     cec_write(cec, TEGRA_CEC_HW_CONTROL, state);
0261     return 0;
0262 }
0263
0264 static int tegra_cec_adap_monitor_all_enable(struct cec_adapter *adap,
0265                          bool enable)
0266 {
0267     struct tegra_cec *cec = adap->priv;
0268     u32 reg = cec_read(cec, TEGRA_CEC_HW_CONTROL);
0269
0270     if (enable)
0271         reg |= TEGRA_CEC_HWCTRL_RX_SNOOP;
0272     else
0273         reg &= ~TEGRA_CEC_HWCTRL_RX_SNOOP;
0274     cec_write(cec, TEGRA_CEC_HW_CONTROL, reg);
0275     return 0;
0276 }
0277
0278 static int tegra_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
0279                    u32 signal_free_time_ms, struct cec_msg *msg)
0280 {
0281     bool retry_xfer = signal_free_time_ms == CEC_SIGNAL_FREE_TIME_RETRY;
0282     struct tegra_cec *cec = adap->priv;
0283     unsigned int i;
0284     u32 mode = 0;
0285     u32 mask;
0286
0287     if (cec_msg_is_broadcast(msg))
0288         mode = TEGRA_CEC_TX_REG_BCAST;
0289
0290     cec->tx_buf_cur = 0;
0291     cec->tx_buf_cnt = msg->len;
0292
0293     for (i = 0; i < msg->len; i++) {
0294         cec->tx_buf[i] = mode | msg->msg[i];
0295         if (i == 0)
0296             cec->tx_buf[i] |= TEGRA_CEC_TX_REG_START_BIT;
0297         if (i == msg->len - 1)
0298             cec->tx_buf[i] |= TEGRA_CEC_TX_REG_EOM;
0299         if (i == 0 && retry_xfer)
0300             cec->tx_buf[i] |= TEGRA_CEC_TX_REG_RETRY;
0301     }
0302
0303     mask = cec_read(cec, TEGRA_CEC_INT_MASK);
0304     cec_write(cec, TEGRA_CEC_INT_MASK,
0305           mask | TEGRA_CEC_INT_MASK_TX_REGISTER_EMPTY);
0306
0307     return 0;
0308 }
0309
0310 static const struct cec_adap_ops tegra_cec_ops = {
0311     .adap_enable = tegra_cec_adap_enable,
0312     .adap_log_addr = tegra_cec_adap_log_addr,
0313     .adap_transmit = tegra_cec_adap_transmit,
0314     .adap_monitor_all_enable = tegra_cec_adap_monitor_all_enable,
0315 };
0316
0317 static int tegra_cec_probe(struct platform_device *pdev)
0318 {
0319     struct device *hdmi_dev;
0320     struct tegra_cec *cec;
0321     struct resource *res;
0322     int ret = 0;
0323
0324     hdmi_dev = cec_notifier_parse_hdmi_phandle(&pdev->dev);
0325
0326     if (IS_ERR(hdmi_dev))
0327         return PTR_ERR(hdmi_dev);
0328
0329     cec = devm_kzalloc(&pdev->dev, sizeof(struct tegra_cec), GFP_KERNEL);
0330
0331     if (!cec)
0332         return -ENOMEM;
0333
0334     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0335
0336     if (!res) {
0337         dev_err(&pdev->dev,
0338             "Unable to allocate resources for device\n");
0339         return -EBUSY;
0340     }
0341
0342     if (!devm_request_mem_region(&pdev->dev, res->start, resource_size(res),
0343         pdev->name)) {
0344         dev_err(&pdev->dev,
0345             "Unable to request mem region for device\n");
0346         return -EBUSY;
0347     }
0348
0349     cec->tegra_cec_irq = platform_get_irq(pdev, 0);
0350
0351     if (cec->tegra_cec_irq <= 0)
0352         return -EBUSY;
0353
0354     cec->cec_base = devm_ioremap(&pdev->dev, res->start,
0355                          resource_size(res));
0356
0357     if (!cec->cec_base) {
0358         dev_err(&pdev->dev, "Unable to grab IOs for device\n");
0359         return -EBUSY;
0360     }
0361
0362     cec->clk = devm_clk_get(&pdev->dev, "cec");
0363
0364     if (IS_ERR_OR_NULL(cec->clk)) {
0365         dev_err(&pdev->dev, "Can't get clock for CEC\n");
0366         return -ENOENT;
0367     }
0368
0369     ret = clk_prepare_enable(cec->clk);
0370     if (ret) {
0371         dev_err(&pdev->dev, "Unable to prepare clock for CEC\n");
0372         return ret;
0373     }
0374
0375     /* set context info. */
0376     cec->dev = &pdev->dev;
0377
0378     platform_set_drvdata(pdev, cec);
0379
0380     ret = devm_request_threaded_irq(&pdev->dev, cec->tegra_cec_irq,
0381         tegra_cec_irq_handler, tegra_cec_irq_thread_handler,
0382         0, "cec_irq", &pdev->dev);
0383
0384     if (ret) {
0385         dev_err(&pdev->dev,
0386             "Unable to request interrupt for device\n");
0387         goto err_clk;
0388     }
0389
0390     cec->adap = cec_allocate_adapter(&tegra_cec_ops, cec, TEGRA_CEC_NAME,
0391             CEC_CAP_DEFAULTS | CEC_CAP_MONITOR_ALL |
0392             CEC_CAP_CONNECTOR_INFO,
0393             CEC_MAX_LOG_ADDRS);
0394     if (IS_ERR(cec->adap)) {
0395         ret = -ENOMEM;
0396         dev_err(&pdev->dev, "Couldn't create cec adapter\n");
0397         goto err_clk;
0398     }
0399
0400     cec->notifier = cec_notifier_cec_adap_register(hdmi_dev, NULL,
0401                                cec->adap);
0402     if (!cec->notifier) {
0403         ret = -ENOMEM;
0404         goto err_adapter;
0405     }
0406
0407     ret = cec_register_adapter(cec->adap, &pdev->dev);
0408     if (ret) {
0409         dev_err(&pdev->dev, "Couldn't register device\n");
0410         goto err_notifier;
0411     }
0412
0413     return 0;
0414
0415 err_notifier:
0416     cec_notifier_cec_adap_unregister(cec->notifier, cec->adap);
0417 err_adapter:
0418     cec_delete_adapter(cec->adap);
0419 err_clk:
0420     clk_disable_unprepare(cec->clk);
0421     return ret;
0422 }
0423
0424 static int tegra_cec_remove(struct platform_device *pdev)
0425 {
0426     struct tegra_cec *cec = platform_get_drvdata(pdev);
0427
0428     clk_disable_unprepare(cec->clk);
0429
0430     cec_notifier_cec_adap_unregister(cec->notifier, cec->adap);
0431     cec_unregister_adapter(cec->adap);
0432
0433     return 0;
0434 }
0435
0436 #ifdef CONFIG_PM
0437 static int tegra_cec_suspend(struct platform_device *pdev, pm_message_t state)
0438 {
0439     struct tegra_cec *cec = platform_get_drvdata(pdev);
0440
0441     clk_disable_unprepare(cec->clk);
0442
0443     dev_notice(&pdev->dev, "suspended\n");
0444     return 0;
0445 }
0446
0447 static int tegra_cec_resume(struct platform_device *pdev)
0448 {
0449     struct tegra_cec *cec = platform_get_drvdata(pdev);
0450
0451     dev_notice(&pdev->dev, "Resuming\n");
0452
0453     return clk_prepare_enable(cec->clk);
0454 }
0455 #endif
0456
0457 static const struct of_device_id tegra_cec_of_match[] = {
0458     { .compatible = "nvidia,tegra114-cec", },
0459     { .compatible = "nvidia,tegra124-cec", },
0460     { .compatible = "nvidia,tegra210-cec", },
0461     {},
0462 };
0463
0464 static struct platform_driver tegra_cec_driver = {
0465     .driver = {
0466         .name = TEGRA_CEC_NAME,
0467         .of_match_table = of_match_ptr(tegra_cec_of_match),
0468     },
0469     .probe = tegra_cec_probe,
0470     .remove = tegra_cec_remove,
0471
0472 #ifdef CONFIG_PM
0473     .suspend = tegra_cec_suspend,
0474     .resume = tegra_cec_resume,
0475 #endif
0476 };
0477
0478 module_platform_driver(tegra_cec_driver);
0479
0480 MODULE_DESCRIPTION("Tegra HDMI CEC driver");
0481 MODULE_AUTHOR("NVIDIA CORPORATION");
0482 MODULE_AUTHOR("Cisco Systems, Inc. and/or its affiliates");
0483 MODULE_LICENSE("GPL v2");