platform/stm32/stm32-cec.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * STM32 CEC driver
0004  * Copyright (C) STMicroelectronics SA 2017
0005  *
0006  */
0007
0008 #include <linux/clk.h>
0009 #include <linux/interrupt.h>
0010 #include <linux/kernel.h>
0011 #include <linux/module.h>
0012 #include <linux/of.h>
0013 #include <linux/of_device.h>
0014 #include <linux/platform_device.h>
0015 #include <linux/regmap.h>
0016
0017 #include <media/cec.h>
0018
0019 #define CEC_NAME    "stm32-cec"
0020
0021 /* CEC registers  */
0022 #define CEC_CR      0x0000 /* Control Register */
0023 #define CEC_CFGR    0x0004 /* ConFiGuration Register */
0024 #define CEC_TXDR    0x0008 /* Rx data Register */
0025 #define CEC_RXDR    0x000C /* Rx data Register */
0026 #define CEC_ISR     0x0010 /* Interrupt and status Register */
0027 #define CEC_IER     0x0014 /* Interrupt enable Register */
0028
0029 #define TXEOM       BIT(2)
0030 #define TXSOM       BIT(1)
0031 #define CECEN       BIT(0)
0032
0033 #define LSTN        BIT(31)
0034 #define OAR     GENMASK(30, 16)
0035 #define SFTOP       BIT(8)
0036 #define BRDNOGEN    BIT(7)
0037 #define LBPEGEN     BIT(6)
0038 #define BREGEN      BIT(5)
0039 #define BRESTP      BIT(4)
0040 #define RXTOL       BIT(3)
0041 #define SFT     GENMASK(2, 0)
0042 #define FULL_CFG    (LSTN | SFTOP | BRDNOGEN | LBPEGEN | BREGEN | BRESTP \
0043              | RXTOL)
0044
0045 #define TXACKE      BIT(12)
0046 #define TXERR       BIT(11)
0047 #define TXUDR       BIT(10)
0048 #define TXEND       BIT(9)
0049 #define TXBR        BIT(8)
0050 #define ARBLST      BIT(7)
0051 #define RXACKE      BIT(6)
0052 #define RXOVR       BIT(2)
0053 #define RXEND       BIT(1)
0054 #define RXBR        BIT(0)
0055
0056 #define ALL_TX_IT   (TXEND | TXBR | TXACKE | TXERR | TXUDR | ARBLST)
0057 #define ALL_RX_IT   (RXEND | RXBR | RXACKE | RXOVR)
0058
0059 /*
0060  * 400 ms is the time it takes for one 16 byte message to be
0061  * transferred and 5 is the maximum number of retries. Add
0062  * another 100 ms as a margin.
0063  */
0064 #define CEC_XFER_TIMEOUT_MS (5 * 400 + 100)
0065
0066 struct stm32_cec {
0067     struct cec_adapter  *adap;
0068     struct device       *dev;
0069     struct clk      *clk_cec;
0070     struct clk      *clk_hdmi_cec;
0071     struct reset_control    *rstc;
0072     struct regmap       *regmap;
0073     int         irq;
0074     u32         irq_status;
0075     struct cec_msg      rx_msg;
0076     struct cec_msg      tx_msg;
0077     int         tx_cnt;
0078 };
0079
0080 static void cec_hw_init(struct stm32_cec *cec)
0081 {
0082     regmap_update_bits(cec->regmap, CEC_CR, TXEOM | TXSOM | CECEN, 0);
0083
0084     regmap_update_bits(cec->regmap, CEC_IER, ALL_TX_IT | ALL_RX_IT,
0085                ALL_TX_IT | ALL_RX_IT);
0086
0087     regmap_update_bits(cec->regmap, CEC_CFGR, FULL_CFG, FULL_CFG);
0088 }
0089
0090 static void stm32_tx_done(struct stm32_cec *cec, u32 status)
0091 {
0092     if (status & (TXERR | TXUDR)) {
0093         cec_transmit_done(cec->adap, CEC_TX_STATUS_ERROR,
0094                   0, 0, 0, 1);
0095         return;
0096     }
0097
0098     if (status & ARBLST) {
0099         cec_transmit_done(cec->adap, CEC_TX_STATUS_ARB_LOST,
0100                   1, 0, 0, 0);
0101         return;
0102     }
0103
0104     if (status & TXACKE) {
0105         cec_transmit_done(cec->adap, CEC_TX_STATUS_NACK,
0106                   0, 1, 0, 0);
0107         return;
0108     }
0109
0110     if (cec->irq_status & TXBR) {
0111         /* send next byte */
0112         if (cec->tx_cnt < cec->tx_msg.len)
0113             regmap_write(cec->regmap, CEC_TXDR,
0114                      cec->tx_msg.msg[cec->tx_cnt++]);
0115
0116         /* TXEOM is set to command transmission of the last byte */
0117         if (cec->tx_cnt == cec->tx_msg.len)
0118             regmap_update_bits(cec->regmap, CEC_CR, TXEOM, TXEOM);
0119     }
0120
0121     if (cec->irq_status & TXEND)
0122         cec_transmit_done(cec->adap, CEC_TX_STATUS_OK, 0, 0, 0, 0);
0123 }
0124
0125 static void stm32_rx_done(struct stm32_cec *cec, u32 status)
0126 {
0127     if (cec->irq_status & (RXACKE | RXOVR)) {
0128         cec->rx_msg.len = 0;
0129         return;
0130     }
0131
0132     if (cec->irq_status & RXBR) {
0133         u32 val;
0134
0135         regmap_read(cec->regmap, CEC_RXDR, &val);
0136         cec->rx_msg.msg[cec->rx_msg.len++] = val & 0xFF;
0137     }
0138
0139     if (cec->irq_status & RXEND) {
0140         cec_received_msg(cec->adap, &cec->rx_msg);
0141         cec->rx_msg.len = 0;
0142     }
0143 }
0144
0145 static irqreturn_t stm32_cec_irq_thread(int irq, void *arg)
0146 {
0147     struct stm32_cec *cec = arg;
0148
0149     if (cec->irq_status & ALL_TX_IT)
0150         stm32_tx_done(cec, cec->irq_status);
0151
0152     if (cec->irq_status & ALL_RX_IT)
0153         stm32_rx_done(cec, cec->irq_status);
0154
0155     cec->irq_status = 0;
0156
0157     return IRQ_HANDLED;
0158 }
0159
0160 static irqreturn_t stm32_cec_irq_handler(int irq, void *arg)
0161 {
0162     struct stm32_cec *cec = arg;
0163
0164     regmap_read(cec->regmap, CEC_ISR, &cec->irq_status);
0165
0166     regmap_update_bits(cec->regmap, CEC_ISR,
0167                ALL_TX_IT | ALL_RX_IT,
0168                ALL_TX_IT | ALL_RX_IT);
0169
0170     return IRQ_WAKE_THREAD;
0171 }
0172
0173 static int stm32_cec_adap_enable(struct cec_adapter *adap, bool enable)
0174 {
0175     struct stm32_cec *cec = adap->priv;
0176     int ret = 0;
0177
0178     if (enable) {
0179         ret = clk_enable(cec->clk_cec);
0180         if (ret)
0181             dev_err(cec->dev, "fail to enable cec clock\n");
0182
0183         clk_enable(cec->clk_hdmi_cec);
0184         regmap_update_bits(cec->regmap, CEC_CR, CECEN, CECEN);
0185     } else {
0186         clk_disable(cec->clk_cec);
0187         clk_disable(cec->clk_hdmi_cec);
0188         regmap_update_bits(cec->regmap, CEC_CR, CECEN, 0);
0189     }
0190
0191     return ret;
0192 }
0193
0194 static int stm32_cec_adap_log_addr(struct cec_adapter *adap, u8 logical_addr)
0195 {
0196     struct stm32_cec *cec = adap->priv;
0197     u32 oar = (1 << logical_addr) << 16;
0198     u32 val;
0199
0200     /* Poll every 100µs the register CEC_CR to wait end of transmission */
0201     regmap_read_poll_timeout(cec->regmap, CEC_CR, val, !(val & TXSOM),
0202                  100, CEC_XFER_TIMEOUT_MS * 1000);
0203     regmap_update_bits(cec->regmap, CEC_CR, CECEN, 0);
0204
0205     if (logical_addr == CEC_LOG_ADDR_INVALID)
0206         regmap_update_bits(cec->regmap, CEC_CFGR, OAR, 0);
0207     else
0208         regmap_update_bits(cec->regmap, CEC_CFGR, oar, oar);
0209
0210     regmap_update_bits(cec->regmap, CEC_CR, CECEN, CECEN);
0211
0212     return 0;
0213 }
0214
0215 static int stm32_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
0216                    u32 signal_free_time, struct cec_msg *msg)
0217 {
0218     struct stm32_cec *cec = adap->priv;
0219
0220     /* Copy message */
0221     cec->tx_msg = *msg;
0222     cec->tx_cnt = 0;
0223
0224     /*
0225      * If the CEC message consists of only one byte,
0226      * TXEOM must be set before of TXSOM.
0227      */
0228     if (cec->tx_msg.len == 1)
0229         regmap_update_bits(cec->regmap, CEC_CR, TXEOM, TXEOM);
0230
0231     /* TXSOM is set to command transmission of the first byte */
0232     regmap_update_bits(cec->regmap, CEC_CR, TXSOM, TXSOM);
0233
0234     /* Write the header (first byte of message) */
0235     regmap_write(cec->regmap, CEC_TXDR, cec->tx_msg.msg[0]);
0236     cec->tx_cnt++;
0237
0238     return 0;
0239 }
0240
0241 static const struct cec_adap_ops stm32_cec_adap_ops = {
0242     .adap_enable = stm32_cec_adap_enable,
0243     .adap_log_addr = stm32_cec_adap_log_addr,
0244     .adap_transmit = stm32_cec_adap_transmit,
0245 };
0246
0247 static const struct regmap_config stm32_cec_regmap_cfg = {
0248     .reg_bits = 32,
0249     .val_bits = 32,
0250     .reg_stride = sizeof(u32),
0251     .max_register = 0x14,
0252     .fast_io = true,
0253 };
0254
0255 static int stm32_cec_probe(struct platform_device *pdev)
0256 {
0257     u32 caps = CEC_CAP_DEFAULTS | CEC_CAP_PHYS_ADDR | CEC_MODE_MONITOR_ALL;
0258     struct stm32_cec *cec;
0259     void __iomem *mmio;
0260     int ret;
0261
0262     cec = devm_kzalloc(&pdev->dev, sizeof(*cec), GFP_KERNEL);
0263     if (!cec)
0264         return -ENOMEM;
0265
0266     cec->dev = &pdev->dev;
0267
0268     mmio = devm_platform_ioremap_resource(pdev, 0);
0269     if (IS_ERR(mmio))
0270         return PTR_ERR(mmio);
0271
0272     cec->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "cec", mmio,
0273                         &stm32_cec_regmap_cfg);
0274
0275     if (IS_ERR(cec->regmap))
0276         return PTR_ERR(cec->regmap);
0277
0278     cec->irq = platform_get_irq(pdev, 0);
0279     if (cec->irq < 0)
0280         return cec->irq;
0281
0282     ret = devm_request_threaded_irq(&pdev->dev, cec->irq,
0283                     stm32_cec_irq_handler,
0284                     stm32_cec_irq_thread,
0285                     0,
0286                     pdev->name, cec);
0287     if (ret)
0288         return ret;
0289
0290     cec->clk_cec = devm_clk_get(&pdev->dev, "cec");
0291     if (IS_ERR(cec->clk_cec)) {
0292         if (PTR_ERR(cec->clk_cec) != -EPROBE_DEFER)
0293             dev_err(&pdev->dev, "Cannot get cec clock\n");
0294
0295         return PTR_ERR(cec->clk_cec);
0296     }
0297
0298     ret = clk_prepare(cec->clk_cec);
0299     if (ret) {
0300         dev_err(&pdev->dev, "Unable to prepare cec clock\n");
0301         return ret;
0302     }
0303
0304     cec->clk_hdmi_cec = devm_clk_get(&pdev->dev, "hdmi-cec");
0305     if (IS_ERR(cec->clk_hdmi_cec) &&
0306         PTR_ERR(cec->clk_hdmi_cec) == -EPROBE_DEFER) {
0307         ret = -EPROBE_DEFER;
0308         goto err_unprepare_cec_clk;
0309     }
0310
0311     if (!IS_ERR(cec->clk_hdmi_cec)) {
0312         ret = clk_prepare(cec->clk_hdmi_cec);
0313         if (ret) {
0314             dev_err(&pdev->dev, "Can't prepare hdmi-cec clock\n");
0315             goto err_unprepare_cec_clk;
0316         }
0317     }
0318
0319     /*
0320      * CEC_CAP_PHYS_ADDR caps should be removed when a cec notifier is
0321      * available for example when a drm driver can provide edid
0322      */
0323     cec->adap = cec_allocate_adapter(&stm32_cec_adap_ops, cec,
0324             CEC_NAME, caps, CEC_MAX_LOG_ADDRS);
0325     ret = PTR_ERR_OR_ZERO(cec->adap);
0326     if (ret)
0327         goto err_unprepare_hdmi_cec_clk;
0328
0329     ret = cec_register_adapter(cec->adap, &pdev->dev);
0330     if (ret)
0331         goto err_delete_adapter;
0332
0333     cec_hw_init(cec);
0334
0335     platform_set_drvdata(pdev, cec);
0336
0337     return 0;
0338
0339 err_delete_adapter:
0340     cec_delete_adapter(cec->adap);
0341
0342 err_unprepare_hdmi_cec_clk:
0343     clk_unprepare(cec->clk_hdmi_cec);
0344
0345 err_unprepare_cec_clk:
0346     clk_unprepare(cec->clk_cec);
0347     return ret;
0348 }
0349
0350 static int stm32_cec_remove(struct platform_device *pdev)
0351 {
0352     struct stm32_cec *cec = platform_get_drvdata(pdev);
0353
0354     clk_unprepare(cec->clk_cec);
0355     clk_unprepare(cec->clk_hdmi_cec);
0356
0357     cec_unregister_adapter(cec->adap);
0358
0359     return 0;
0360 }
0361
0362 static const struct of_device_id stm32_cec_of_match[] = {
0363     { .compatible = "st,stm32-cec" },
0364     { /* end node */ }
0365 };
0366 MODULE_DEVICE_TABLE(of, stm32_cec_of_match);
0367
0368 static struct platform_driver stm32_cec_driver = {
0369     .probe  = stm32_cec_probe,
0370     .remove = stm32_cec_remove,
0371     .driver = {
0372         .name       = CEC_NAME,
0373         .of_match_table = stm32_cec_of_match,
0374     },
0375 };
0376
0377 module_platform_driver(stm32_cec_driver);
0378
0379 MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>");
0380 MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>");
0381 MODULE_DESCRIPTION("STMicroelectronics STM32 Consumer Electronics Control");
0382 MODULE_LICENSE("GPL v2");