platform/seco/seco-cec.h

0001 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
0002 /*
0003  * SECO X86 Boards CEC register defines
0004  *
0005  * Author:  Ettore Chimenti <ek5.chimenti@gmail.com>
0006  * Copyright (C) 2018, SECO Spa.
0007  * Copyright (C) 2018, Aidilab Srl.
0008  */
0009
0010 #ifndef __SECO_CEC_H__
0011 #define __SECO_CEC_H__
0012
0013 #define SECOCEC_MAX_ADDRS       1
0014 #define SECOCEC_DEV_NAME        "secocec"
0015 #define SECOCEC_LATEST_FW       0x0f0b
0016
0017 #define SMBTIMEOUT          0xfff
0018 #define SMB_POLL_UDELAY         10
0019
0020 #define SMBUS_WRITE         0
0021 #define SMBUS_READ          1
0022
0023 #define CMD_BYTE_DATA           0
0024 #define CMD_WORD_DATA           1
0025
0026 /*
0027  * SMBus definitons for Braswell
0028  */
0029
0030 #define BRA_DONE_STATUS         BIT(7)
0031 #define BRA_INUSE_STS           BIT(6)
0032 #define BRA_FAILED_OP           BIT(4)
0033 #define BRA_BUS_ERR         BIT(3)
0034 #define BRA_DEV_ERR         BIT(2)
0035 #define BRA_INTR            BIT(1)
0036 #define BRA_HOST_BUSY           BIT(0)
0037 #define BRA_HSTS_ERR_MASK   (BRA_FAILED_OP | BRA_BUS_ERR | BRA_DEV_ERR)
0038
0039 #define BRA_PEC_EN          BIT(7)
0040 #define BRA_START           BIT(6)
0041 #define BRA_LAST__BYTE          BIT(5)
0042 #define BRA_INTREN          BIT(0)
0043 #define BRA_SMB_CMD         (7 << 2)
0044 #define BRA_SMB_CMD_QUICK       (0 << 2)
0045 #define BRA_SMB_CMD_BYTE        (1 << 2)
0046 #define BRA_SMB_CMD_BYTE_DATA       (2 << 2)
0047 #define BRA_SMB_CMD_WORD_DATA       (3 << 2)
0048 #define BRA_SMB_CMD_PROCESS_CALL    (4 << 2)
0049 #define BRA_SMB_CMD_BLOCK       (5 << 2)
0050 #define BRA_SMB_CMD_I2CREAD     (6 << 2)
0051 #define BRA_SMB_CMD_BLOCK_PROCESS   (7 << 2)
0052
0053 #define BRA_SMB_BASE_ADDR  0x2040
0054 #define HSTS               (BRA_SMB_BASE_ADDR + 0)
0055 #define HCNT               (BRA_SMB_BASE_ADDR + 2)
0056 #define HCMD               (BRA_SMB_BASE_ADDR + 3)
0057 #define XMIT_SLVA          (BRA_SMB_BASE_ADDR + 4)
0058 #define HDAT0              (BRA_SMB_BASE_ADDR + 5)
0059 #define HDAT1              (BRA_SMB_BASE_ADDR + 6)
0060
0061 /*
0062  * Microcontroller Address
0063  */
0064
0065 #define SECOCEC_MICRO_ADDRESS       0x40
0066
0067 /*
0068  * STM32 SMBus Registers
0069  */
0070
0071 #define SECOCEC_VERSION         0x00
0072 #define SECOCEC_ENABLE_REG_1        0x01
0073 #define SECOCEC_ENABLE_REG_2        0x02
0074 #define SECOCEC_STATUS_REG_1        0x03
0075 #define SECOCEC_STATUS_REG_2        0x04
0076
0077 #define SECOCEC_STATUS          0x28
0078 #define SECOCEC_DEVICE_LA       0x29
0079 #define SECOCEC_READ_OPERATION_ID   0x2a
0080 #define SECOCEC_READ_DATA_LENGTH    0x2b
0081 #define SECOCEC_READ_DATA_00        0x2c
0082 #define SECOCEC_READ_DATA_02        0x2d
0083 #define SECOCEC_READ_DATA_04        0x2e
0084 #define SECOCEC_READ_DATA_06        0x2f
0085 #define SECOCEC_READ_DATA_08        0x30
0086 #define SECOCEC_READ_DATA_10        0x31
0087 #define SECOCEC_READ_DATA_12        0x32
0088 #define SECOCEC_READ_BYTE0      0x33
0089 #define SECOCEC_WRITE_OPERATION_ID  0x34
0090 #define SECOCEC_WRITE_DATA_LENGTH   0x35
0091 #define SECOCEC_WRITE_DATA_00       0x36
0092 #define SECOCEC_WRITE_DATA_02       0x37
0093 #define SECOCEC_WRITE_DATA_04       0x38
0094 #define SECOCEC_WRITE_DATA_06       0x39
0095 #define SECOCEC_WRITE_DATA_08       0x3a
0096 #define SECOCEC_WRITE_DATA_10       0x3b
0097 #define SECOCEC_WRITE_DATA_12       0x3c
0098 #define SECOCEC_WRITE_BYTE0     0x3d
0099
0100 #define SECOCEC_IR_READ_DATA        0x3e
0101
0102 /*
0103  * IR
0104  */
0105
0106 #define SECOCEC_IR_COMMAND_MASK     0x007F
0107 #define SECOCEC_IR_COMMAND_SHL      0
0108 #define SECOCEC_IR_ADDRESS_MASK     0x1F00
0109 #define SECOCEC_IR_ADDRESS_SHL      8
0110 #define SECOCEC_IR_TOGGLE_MASK      0x8000
0111 #define SECOCEC_IR_TOGGLE_SHL       15
0112
0113 /*
0114  * Enabling register
0115  */
0116
0117 #define SECOCEC_ENABLE_REG_1_CEC        0x1000
0118 #define SECOCEC_ENABLE_REG_1_IR         0x2000
0119 #define SECOCEC_ENABLE_REG_1_IR_PASSTHROUGH 0x4000
0120
0121 /*
0122  * Status register
0123  */
0124
0125 #define SECOCEC_STATUS_REG_1_CEC    SECOCEC_ENABLE_REG_1_CEC
0126 #define SECOCEC_STATUS_REG_1_IR     SECOCEC_ENABLE_REG_1_IR
0127 #define SECOCEC_STATUS_REG_1_IR_PASSTHR SECOCEC_ENABLE_REG_1_IR_PASSTHR
0128
0129 /*
0130  * Status data
0131  */
0132
0133 #define SECOCEC_STATUS_MSG_RECEIVED_MASK    BIT(0)
0134 #define SECOCEC_STATUS_RX_ERROR_MASK        BIT(1)
0135 #define SECOCEC_STATUS_MSG_SENT_MASK        BIT(2)
0136 #define SECOCEC_STATUS_TX_ERROR_MASK        BIT(3)
0137
0138 #define SECOCEC_STATUS_TX_NACK_ERROR        BIT(4)
0139 #define SECOCEC_STATUS_RX_OVERFLOW_MASK     BIT(5)
0140
0141 #endif /* __SECO_CEC_H__ */