drivers/mcb/mcb-internal.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef __MCB_INTERNAL
0003 #define __MCB_INTERNAL
0004
0005 #include <linux/types.h>
0006
0007 #define PCI_VENDOR_ID_MEN       0x1a88
0008 #define PCI_DEVICE_ID_MEN_CHAMELEON 0x4d45
0009 #define CHAMELEONV2_MAGIC       0xabce
0010 #define CHAM_HEADER_SIZE        0x200
0011
0012 enum chameleon_descriptor_type {
0013     CHAMELEON_DTYPE_GENERAL = 0x0,
0014     CHAMELEON_DTYPE_BRIDGE = 0x1,
0015     CHAMELEON_DTYPE_CPU = 0x2,
0016     CHAMELEON_DTYPE_BAR = 0x3,
0017     CHAMELEON_DTYPE_END = 0xf,
0018 };
0019
0020 enum chameleon_bus_type {
0021     CHAMELEON_BUS_WISHBONE,
0022     CHAMELEON_BUS_AVALON,
0023     CHAMELEON_BUS_LPC,
0024     CHAMELEON_BUS_ISA,
0025 };
0026
0027 /**
0028  * struct chameleon_fpga_header
0029  *
0030  * @revision:   Revison of Chameleon table in FPGA
0031  * @model:  Chameleon table model ASCII char
0032  * @minor:  Revision minor
0033  * @bus_type:   Bus type (usually %CHAMELEON_BUS_WISHBONE)
0034  * @magic:  Chameleon header magic number (0xabce for version 2)
0035  * @reserved:   Reserved
0036  * @filename:   Filename of FPGA bitstream
0037  */
0038 struct chameleon_fpga_header {
0039     u8 revision;
0040     char model;
0041     u8 minor;
0042     u8 bus_type;
0043     u16 magic;
0044     u16 reserved;
0045     /* This one has no '\0' at the end!!! */
0046     char filename[CHAMELEON_FILENAME_LEN];
0047 } __packed;
0048 #define HEADER_MAGIC_OFFSET 0x4
0049
0050 /**
0051  * struct chameleon_gdd - Chameleon General Device Descriptor
0052  *
0053  * @irq:    the position in the FPGA's IRQ controller vector
0054  * @rev:    the revision of the variant's implementation
0055  * @var:    the variant of the IP core
0056  * @dev:    the device  the IP core is
0057  * @dtype:  device descriptor type
0058  * @bar:    BAR offset that must be added to module offset
0059  * @inst:   the instance number of the device, 0 is first instance
0060  * @group:  the group the device belongs to (0 = no group)
0061  * @reserved:   reserved
0062  * @offset: beginning of the address window of desired module
0063  * @size:   size of the module's address window
0064  */
0065 struct chameleon_gdd {
0066     __le32 reg1;
0067     __le32 reg2;
0068     __le32 offset;
0069     __le32 size;
0070
0071 } __packed;
0072
0073 /* GDD Register 1 fields */
0074 #define GDD_IRQ(x) ((x) & 0x1f)
0075 #define GDD_REV(x) (((x) >> 5) & 0x3f)
0076 #define GDD_VAR(x) (((x) >> 11) & 0x3f)
0077 #define GDD_DEV(x) (((x) >> 18) & 0x3ff)
0078 #define GDD_DTY(x) (((x) >> 28) & 0xf)
0079
0080 /* GDD Register 2 fields */
0081 #define GDD_BAR(x) ((x) & 0x7)
0082 #define GDD_INS(x) (((x) >> 3) & 0x3f)
0083 #define GDD_GRP(x) (((x) >> 9) & 0x3f)
0084
0085 /**
0086  * struct chameleon_bdd - Chameleon Bridge Device Descriptor
0087  *
0088  * @irq:    the position in the FPGA's IRQ controller vector
0089  * @rev:    the revision of the variant's implementation
0090  * @var:    the variant of the IP core
0091  * @dev:    the device  the IP core is
0092  * @dtype:  device descriptor type
0093  * @bar:    BAR offset that must be added to module offset
0094  * @inst:   the instance number of the device, 0 is first instance
0095  * @dbar:   destination bar from the bus _behind_ the bridge
0096  * @chamoff:    offset within the BAR of the source bus
0097  * @offset:
0098  * @size:
0099  */
0100 struct chameleon_bdd {
0101     unsigned int irq:6;
0102     unsigned int rev:6;
0103     unsigned int var:6;
0104     unsigned int dev:10;
0105     unsigned int dtype:4;
0106     unsigned int bar:3;
0107     unsigned int inst:6;
0108     unsigned int dbar:3;
0109     unsigned int group:6;
0110     unsigned int reserved:14;
0111     u32 chamoff;
0112     u32 offset;
0113     u32 size;
0114 } __packed;
0115
0116 struct chameleon_bar {
0117     u32 addr;
0118     u32 size;
0119 };
0120
0121 #define BAR_CNT(x) ((x) & 0x07)
0122 #define CHAMELEON_BAR_MAX   6
0123 #define BAR_DESC_SIZE(x)    ((x) * sizeof(struct chameleon_bar) + sizeof(__le32))
0124
0125 int chameleon_parse_cells(struct mcb_bus *bus, phys_addr_t mapbase,
0126               void __iomem *base);
0127
0128 #endif