drivers/mailbox/stm32-ipcc.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
0004  * Authors: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
0005  *          Fabien Dessenne <fabien.dessenne@st.com> for STMicroelectronics.
0006  */
0007
0008 #include <linux/bitfield.h>
0009 #include <linux/clk.h>
0010 #include <linux/interrupt.h>
0011 #include <linux/io.h>
0012 #include <linux/mailbox_controller.h>
0013 #include <linux/module.h>
0014 #include <linux/platform_device.h>
0015 #include <linux/pm_wakeirq.h>
0016
0017 #define IPCC_XCR        0x000
0018 #define XCR_RXOIE       BIT(0)
0019 #define XCR_TXOIE       BIT(16)
0020
0021 #define IPCC_XMR        0x004
0022 #define IPCC_XSCR       0x008
0023 #define IPCC_XTOYSR     0x00c
0024
0025 #define IPCC_PROC_OFFST     0x010
0026
0027 #define IPCC_HWCFGR     0x3f0
0028 #define IPCFGR_CHAN_MASK    GENMASK(7, 0)
0029
0030 #define IPCC_VER        0x3f4
0031 #define VER_MINREV_MASK     GENMASK(3, 0)
0032 #define VER_MAJREV_MASK     GENMASK(7, 4)
0033
0034 #define RX_BIT_MASK     GENMASK(15, 0)
0035 #define RX_BIT_CHAN(chan)   BIT(chan)
0036 #define TX_BIT_SHIFT        16
0037 #define TX_BIT_MASK     GENMASK(31, 16)
0038 #define TX_BIT_CHAN(chan)   BIT(TX_BIT_SHIFT + (chan))
0039
0040 #define STM32_MAX_PROCS     2
0041
0042 enum {
0043     IPCC_IRQ_RX,
0044     IPCC_IRQ_TX,
0045     IPCC_IRQ_NUM,
0046 };
0047
0048 struct stm32_ipcc {
0049     struct mbox_controller controller;
0050     void __iomem *reg_base;
0051     void __iomem *reg_proc;
0052     struct clk *clk;
0053     spinlock_t lock; /* protect access to IPCC registers */
0054     int irqs[IPCC_IRQ_NUM];
0055     u32 proc_id;
0056     u32 n_chans;
0057     u32 xcr;
0058     u32 xmr;
0059 };
0060
0061 static inline void stm32_ipcc_set_bits(spinlock_t *lock, void __iomem *reg,
0062                        u32 mask)
0063 {
0064     unsigned long flags;
0065
0066     spin_lock_irqsave(lock, flags);
0067     writel_relaxed(readl_relaxed(reg) | mask, reg);
0068     spin_unlock_irqrestore(lock, flags);
0069 }
0070
0071 static inline void stm32_ipcc_clr_bits(spinlock_t *lock, void __iomem *reg,
0072                        u32 mask)
0073 {
0074     unsigned long flags;
0075
0076     spin_lock_irqsave(lock, flags);
0077     writel_relaxed(readl_relaxed(reg) & ~mask, reg);
0078     spin_unlock_irqrestore(lock, flags);
0079 }
0080
0081 static irqreturn_t stm32_ipcc_rx_irq(int irq, void *data)
0082 {
0083     struct stm32_ipcc *ipcc = data;
0084     struct device *dev = ipcc->controller.dev;
0085     u32 status, mr, tosr, chan;
0086     irqreturn_t ret = IRQ_NONE;
0087     int proc_offset;
0088
0089     /* read 'channel occupied' status from other proc */
0090     proc_offset = ipcc->proc_id ? -IPCC_PROC_OFFST : IPCC_PROC_OFFST;
0091     tosr = readl_relaxed(ipcc->reg_proc + proc_offset + IPCC_XTOYSR);
0092     mr = readl_relaxed(ipcc->reg_proc + IPCC_XMR);
0093
0094     /* search for unmasked 'channel occupied' */
0095     status = tosr & FIELD_GET(RX_BIT_MASK, ~mr);
0096
0097     for (chan = 0; chan < ipcc->n_chans; chan++) {
0098         if (!(status & (1 << chan)))
0099             continue;
0100
0101         dev_dbg(dev, "%s: chan:%d rx\n", __func__, chan);
0102
0103         mbox_chan_received_data(&ipcc->controller.chans[chan], NULL);
0104
0105         stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XSCR,
0106                     RX_BIT_CHAN(chan));
0107
0108         ret = IRQ_HANDLED;
0109     }
0110
0111     return ret;
0112 }
0113
0114 static irqreturn_t stm32_ipcc_tx_irq(int irq, void *data)
0115 {
0116     struct stm32_ipcc *ipcc = data;
0117     struct device *dev = ipcc->controller.dev;
0118     u32 status, mr, tosr, chan;
0119     irqreturn_t ret = IRQ_NONE;
0120
0121     tosr = readl_relaxed(ipcc->reg_proc + IPCC_XTOYSR);
0122     mr = readl_relaxed(ipcc->reg_proc + IPCC_XMR);
0123
0124     /* search for unmasked 'channel free' */
0125     status = ~tosr & FIELD_GET(TX_BIT_MASK, ~mr);
0126
0127     for (chan = 0; chan < ipcc->n_chans ; chan++) {
0128         if (!(status & (1 << chan)))
0129             continue;
0130
0131         dev_dbg(dev, "%s: chan:%d tx\n", __func__, chan);
0132
0133         /* mask 'tx channel free' interrupt */
0134         stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XMR,
0135                     TX_BIT_CHAN(chan));
0136
0137         mbox_chan_txdone(&ipcc->controller.chans[chan], 0);
0138
0139         ret = IRQ_HANDLED;
0140     }
0141
0142     return ret;
0143 }
0144
0145 static int stm32_ipcc_send_data(struct mbox_chan *link, void *data)
0146 {
0147     unsigned long chan = (unsigned long)link->con_priv;
0148     struct stm32_ipcc *ipcc = container_of(link->mbox, struct stm32_ipcc,
0149                            controller);
0150
0151     dev_dbg(ipcc->controller.dev, "%s: chan:%lu\n", __func__, chan);
0152
0153     /* set channel n occupied */
0154     stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XSCR,
0155                 TX_BIT_CHAN(chan));
0156
0157     /* unmask 'tx channel free' interrupt */
0158     stm32_ipcc_clr_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XMR,
0159                 TX_BIT_CHAN(chan));
0160
0161     return 0;
0162 }
0163
0164 static int stm32_ipcc_startup(struct mbox_chan *link)
0165 {
0166     unsigned long chan = (unsigned long)link->con_priv;
0167     struct stm32_ipcc *ipcc = container_of(link->mbox, struct stm32_ipcc,
0168                            controller);
0169     int ret;
0170
0171     ret = clk_prepare_enable(ipcc->clk);
0172     if (ret) {
0173         dev_err(ipcc->controller.dev, "can not enable the clock\n");
0174         return ret;
0175     }
0176
0177     /* unmask 'rx channel occupied' interrupt */
0178     stm32_ipcc_clr_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XMR,
0179                 RX_BIT_CHAN(chan));
0180
0181     return 0;
0182 }
0183
0184 static void stm32_ipcc_shutdown(struct mbox_chan *link)
0185 {
0186     unsigned long chan = (unsigned long)link->con_priv;
0187     struct stm32_ipcc *ipcc = container_of(link->mbox, struct stm32_ipcc,
0188                            controller);
0189
0190     /* mask rx/tx interrupt */
0191     stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XMR,
0192                 RX_BIT_CHAN(chan) | TX_BIT_CHAN(chan));
0193
0194     clk_disable_unprepare(ipcc->clk);
0195 }
0196
0197 static const struct mbox_chan_ops stm32_ipcc_ops = {
0198     .send_data  = stm32_ipcc_send_data,
0199     .startup    = stm32_ipcc_startup,
0200     .shutdown   = stm32_ipcc_shutdown,
0201 };
0202
0203 static int stm32_ipcc_probe(struct platform_device *pdev)
0204 {
0205     struct device *dev = &pdev->dev;
0206     struct device_node *np = dev->of_node;
0207     struct stm32_ipcc *ipcc;
0208     unsigned long i;
0209     int ret;
0210     u32 ip_ver;
0211     static const char * const irq_name[] = {"rx", "tx"};
0212     irq_handler_t irq_thread[] = {stm32_ipcc_rx_irq, stm32_ipcc_tx_irq};
0213
0214     if (!np) {
0215         dev_err(dev, "No DT found\n");
0216         return -ENODEV;
0217     }
0218
0219     ipcc = devm_kzalloc(dev, sizeof(*ipcc), GFP_KERNEL);
0220     if (!ipcc)
0221         return -ENOMEM;
0222
0223     spin_lock_init(&ipcc->lock);
0224
0225     /* proc_id */
0226     if (of_property_read_u32(np, "st,proc-id", &ipcc->proc_id)) {
0227         dev_err(dev, "Missing st,proc-id\n");
0228         return -ENODEV;
0229     }
0230
0231     if (ipcc->proc_id >= STM32_MAX_PROCS) {
0232         dev_err(dev, "Invalid proc_id (%d)\n", ipcc->proc_id);
0233         return -EINVAL;
0234     }
0235
0236     /* regs */
0237     ipcc->reg_base = devm_platform_ioremap_resource(pdev, 0);
0238     if (IS_ERR(ipcc->reg_base))
0239         return PTR_ERR(ipcc->reg_base);
0240
0241     ipcc->reg_proc = ipcc->reg_base + ipcc->proc_id * IPCC_PROC_OFFST;
0242
0243     /* clock */
0244     ipcc->clk = devm_clk_get(dev, NULL);
0245     if (IS_ERR(ipcc->clk))
0246         return PTR_ERR(ipcc->clk);
0247
0248     ret = clk_prepare_enable(ipcc->clk);
0249     if (ret) {
0250         dev_err(dev, "can not enable the clock\n");
0251         return ret;
0252     }
0253
0254     /* irq */
0255     for (i = 0; i < IPCC_IRQ_NUM; i++) {
0256         ipcc->irqs[i] = platform_get_irq_byname(pdev, irq_name[i]);
0257         if (ipcc->irqs[i] < 0) {
0258             ret = ipcc->irqs[i];
0259             goto err_clk;
0260         }
0261
0262         ret = devm_request_threaded_irq(dev, ipcc->irqs[i], NULL,
0263                         irq_thread[i], IRQF_ONESHOT,
0264                         dev_name(dev), ipcc);
0265         if (ret) {
0266             dev_err(dev, "failed to request irq %lu (%d)\n", i, ret);
0267             goto err_clk;
0268         }
0269     }
0270
0271     /* mask and enable rx/tx irq */
0272     stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XMR,
0273                 RX_BIT_MASK | TX_BIT_MASK);
0274     stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XCR,
0275                 XCR_RXOIE | XCR_TXOIE);
0276
0277     /* wakeup */
0278     if (of_property_read_bool(np, "wakeup-source")) {
0279         device_set_wakeup_capable(dev, true);
0280
0281         ret = dev_pm_set_wake_irq(dev, ipcc->irqs[IPCC_IRQ_RX]);
0282         if (ret) {
0283             dev_err(dev, "Failed to set wake up irq\n");
0284             goto err_init_wkp;
0285         }
0286     }
0287
0288     /* mailbox controller */
0289     ipcc->n_chans = readl_relaxed(ipcc->reg_base + IPCC_HWCFGR);
0290     ipcc->n_chans &= IPCFGR_CHAN_MASK;
0291
0292     ipcc->controller.dev = dev;
0293     ipcc->controller.txdone_irq = true;
0294     ipcc->controller.ops = &stm32_ipcc_ops;
0295     ipcc->controller.num_chans = ipcc->n_chans;
0296     ipcc->controller.chans = devm_kcalloc(dev, ipcc->controller.num_chans,
0297                           sizeof(*ipcc->controller.chans),
0298                           GFP_KERNEL);
0299     if (!ipcc->controller.chans) {
0300         ret = -ENOMEM;
0301         goto err_irq_wkp;
0302     }
0303
0304     for (i = 0; i < ipcc->controller.num_chans; i++)
0305         ipcc->controller.chans[i].con_priv = (void *)i;
0306
0307     ret = devm_mbox_controller_register(dev, &ipcc->controller);
0308     if (ret)
0309         goto err_irq_wkp;
0310
0311     platform_set_drvdata(pdev, ipcc);
0312
0313     ip_ver = readl_relaxed(ipcc->reg_base + IPCC_VER);
0314
0315     dev_info(dev, "ipcc rev:%ld.%ld enabled, %d chans, proc %d\n",
0316          FIELD_GET(VER_MAJREV_MASK, ip_ver),
0317          FIELD_GET(VER_MINREV_MASK, ip_ver),
0318          ipcc->controller.num_chans, ipcc->proc_id);
0319
0320     clk_disable_unprepare(ipcc->clk);
0321     return 0;
0322
0323 err_irq_wkp:
0324     if (of_property_read_bool(np, "wakeup-source"))
0325         dev_pm_clear_wake_irq(dev);
0326 err_init_wkp:
0327     device_set_wakeup_capable(dev, false);
0328 err_clk:
0329     clk_disable_unprepare(ipcc->clk);
0330     return ret;
0331 }
0332
0333 static int stm32_ipcc_remove(struct platform_device *pdev)
0334 {
0335     struct device *dev = &pdev->dev;
0336
0337     if (of_property_read_bool(dev->of_node, "wakeup-source"))
0338         dev_pm_clear_wake_irq(&pdev->dev);
0339
0340     device_set_wakeup_capable(dev, false);
0341
0342     return 0;
0343 }
0344
0345 #ifdef CONFIG_PM_SLEEP
0346 static int stm32_ipcc_suspend(struct device *dev)
0347 {
0348     struct stm32_ipcc *ipcc = dev_get_drvdata(dev);
0349
0350     ipcc->xmr = readl_relaxed(ipcc->reg_proc + IPCC_XMR);
0351     ipcc->xcr = readl_relaxed(ipcc->reg_proc + IPCC_XCR);
0352
0353     return 0;
0354 }
0355
0356 static int stm32_ipcc_resume(struct device *dev)
0357 {
0358     struct stm32_ipcc *ipcc = dev_get_drvdata(dev);
0359
0360     writel_relaxed(ipcc->xmr, ipcc->reg_proc + IPCC_XMR);
0361     writel_relaxed(ipcc->xcr, ipcc->reg_proc + IPCC_XCR);
0362
0363     return 0;
0364 }
0365 #endif
0366
0367 static SIMPLE_DEV_PM_OPS(stm32_ipcc_pm_ops,
0368              stm32_ipcc_suspend, stm32_ipcc_resume);
0369
0370 static const struct of_device_id stm32_ipcc_of_match[] = {
0371     { .compatible = "st,stm32mp1-ipcc" },
0372     {},
0373 };
0374 MODULE_DEVICE_TABLE(of, stm32_ipcc_of_match);
0375
0376 static struct platform_driver stm32_ipcc_driver = {
0377     .driver = {
0378         .name = "stm32-ipcc",
0379         .pm = &stm32_ipcc_pm_ops,
0380         .of_match_table = stm32_ipcc_of_match,
0381     },
0382     .probe      = stm32_ipcc_probe,
0383     .remove     = stm32_ipcc_remove,
0384 };
0385
0386 module_platform_driver(stm32_ipcc_driver);
0387
0388 MODULE_AUTHOR("Ludovic Barre <ludovic.barre@st.com>");
0389 MODULE_AUTHOR("Fabien Dessenne <fabien.dessenne@st.com>");
0390 MODULE_DESCRIPTION("STM32 IPCC driver");
0391 MODULE_LICENSE("GPL v2");