drivers/mailbox/qcom-ipcc.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
0004  */
0005
0006 #include <linux/bitfield.h>
0007 #include <linux/interrupt.h>
0008 #include <linux/irq.h>
0009 #include <linux/irqdomain.h>
0010 #include <linux/mailbox_controller.h>
0011 #include <linux/module.h>
0012 #include <linux/platform_device.h>
0013
0014 #include <dt-bindings/mailbox/qcom-ipcc.h>
0015
0016 /* IPCC Register offsets */
0017 #define IPCC_REG_SEND_ID        0x0c
0018 #define IPCC_REG_RECV_ID        0x10
0019 #define IPCC_REG_RECV_SIGNAL_ENABLE 0x14
0020 #define IPCC_REG_RECV_SIGNAL_DISABLE    0x18
0021 #define IPCC_REG_RECV_SIGNAL_CLEAR  0x1c
0022 #define IPCC_REG_CLIENT_CLEAR       0x38
0023
0024 #define IPCC_SIGNAL_ID_MASK     GENMASK(15, 0)
0025 #define IPCC_CLIENT_ID_MASK     GENMASK(31, 16)
0026
0027 #define IPCC_NO_PENDING_IRQ     GENMASK(31, 0)
0028
0029 /**
0030  * struct qcom_ipcc_chan_info - Per-mailbox-channel info
0031  * @client_id:  The client-id to which the interrupt has to be triggered
0032  * @signal_id:  The signal-id to which the interrupt has to be triggered
0033  */
0034 struct qcom_ipcc_chan_info {
0035     u16 client_id;
0036     u16 signal_id;
0037 };
0038
0039 /**
0040  * struct qcom_ipcc - Holder for the mailbox driver
0041  * @dev:        Device associated with this instance
0042  * @base:       Base address of the IPCC frame associated to APSS
0043  * @irq_domain:     The irq_domain associated with this instance
0044  * @chans:      The mailbox channels array
0045  * @mchan:      The per-mailbox channel info array
0046  * @mbox:       The mailbox controller
0047  * @num_chans:      Number of @chans elements
0048  * @irq:        Summary irq
0049  */
0050 struct qcom_ipcc {
0051     struct device *dev;
0052     void __iomem *base;
0053     struct irq_domain *irq_domain;
0054     struct mbox_chan *chans;
0055     struct qcom_ipcc_chan_info *mchan;
0056     struct mbox_controller mbox;
0057     int num_chans;
0058     int irq;
0059 };
0060
0061 static inline struct qcom_ipcc *to_qcom_ipcc(struct mbox_controller *mbox)
0062 {
0063     return container_of(mbox, struct qcom_ipcc, mbox);
0064 }
0065
0066 static inline u32 qcom_ipcc_get_hwirq(u16 client_id, u16 signal_id)
0067 {
0068     return FIELD_PREP(IPCC_CLIENT_ID_MASK, client_id) |
0069            FIELD_PREP(IPCC_SIGNAL_ID_MASK, signal_id);
0070 }
0071
0072 static irqreturn_t qcom_ipcc_irq_fn(int irq, void *data)
0073 {
0074     struct qcom_ipcc *ipcc = data;
0075     u32 hwirq;
0076     int virq;
0077
0078     for (;;) {
0079         hwirq = readl(ipcc->base + IPCC_REG_RECV_ID);
0080         if (hwirq == IPCC_NO_PENDING_IRQ)
0081             break;
0082
0083         virq = irq_find_mapping(ipcc->irq_domain, hwirq);
0084         writel(hwirq, ipcc->base + IPCC_REG_RECV_SIGNAL_CLEAR);
0085         generic_handle_irq(virq);
0086     }
0087
0088     return IRQ_HANDLED;
0089 }
0090
0091 static void qcom_ipcc_mask_irq(struct irq_data *irqd)
0092 {
0093     struct qcom_ipcc *ipcc = irq_data_get_irq_chip_data(irqd);
0094     irq_hw_number_t hwirq = irqd_to_hwirq(irqd);
0095
0096     writel(hwirq, ipcc->base + IPCC_REG_RECV_SIGNAL_DISABLE);
0097 }
0098
0099 static void qcom_ipcc_unmask_irq(struct irq_data *irqd)
0100 {
0101     struct qcom_ipcc *ipcc = irq_data_get_irq_chip_data(irqd);
0102     irq_hw_number_t hwirq = irqd_to_hwirq(irqd);
0103
0104     writel(hwirq, ipcc->base + IPCC_REG_RECV_SIGNAL_ENABLE);
0105 }
0106
0107 static struct irq_chip qcom_ipcc_irq_chip = {
0108     .name = "ipcc",
0109     .irq_mask = qcom_ipcc_mask_irq,
0110     .irq_unmask = qcom_ipcc_unmask_irq,
0111     .flags = IRQCHIP_SKIP_SET_WAKE,
0112 };
0113
0114 static int qcom_ipcc_domain_map(struct irq_domain *d, unsigned int irq,
0115                 irq_hw_number_t hw)
0116 {
0117     struct qcom_ipcc *ipcc = d->host_data;
0118
0119     irq_set_chip_and_handler(irq, &qcom_ipcc_irq_chip, handle_level_irq);
0120     irq_set_chip_data(irq, ipcc);
0121     irq_set_noprobe(irq);
0122
0123     return 0;
0124 }
0125
0126 static int qcom_ipcc_domain_xlate(struct irq_domain *d,
0127                   struct device_node *node, const u32 *intspec,
0128                   unsigned int intsize,
0129                   unsigned long *out_hwirq,
0130                   unsigned int *out_type)
0131 {
0132     if (intsize != 3)
0133         return -EINVAL;
0134
0135     *out_hwirq = qcom_ipcc_get_hwirq(intspec[0], intspec[1]);
0136     *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
0137
0138     return 0;
0139 }
0140
0141 static const struct irq_domain_ops qcom_ipcc_irq_ops = {
0142     .map = qcom_ipcc_domain_map,
0143     .xlate = qcom_ipcc_domain_xlate,
0144 };
0145
0146 static int qcom_ipcc_mbox_send_data(struct mbox_chan *chan, void *data)
0147 {
0148     struct qcom_ipcc *ipcc = to_qcom_ipcc(chan->mbox);
0149     struct qcom_ipcc_chan_info *mchan = chan->con_priv;
0150     u32 hwirq;
0151
0152     hwirq = qcom_ipcc_get_hwirq(mchan->client_id, mchan->signal_id);
0153     writel(hwirq, ipcc->base + IPCC_REG_SEND_ID);
0154
0155     return 0;
0156 }
0157
0158 static void qcom_ipcc_mbox_shutdown(struct mbox_chan *chan)
0159 {
0160     chan->con_priv = NULL;
0161 }
0162
0163 static struct mbox_chan *qcom_ipcc_mbox_xlate(struct mbox_controller *mbox,
0164                     const struct of_phandle_args *ph)
0165 {
0166     struct qcom_ipcc *ipcc = to_qcom_ipcc(mbox);
0167     struct qcom_ipcc_chan_info *mchan;
0168     struct mbox_chan *chan;
0169     struct device *dev;
0170     int chan_id;
0171
0172     dev = ipcc->dev;
0173
0174     if (ph->args_count != 2)
0175         return ERR_PTR(-EINVAL);
0176
0177     for (chan_id = 0; chan_id < mbox->num_chans; chan_id++) {
0178         chan = &ipcc->chans[chan_id];
0179         mchan = chan->con_priv;
0180
0181         if (!mchan)
0182             break;
0183         else if (mchan->client_id == ph->args[0] &&
0184                 mchan->signal_id == ph->args[1])
0185             return ERR_PTR(-EBUSY);
0186     }
0187
0188     if (chan_id >= mbox->num_chans)
0189         return ERR_PTR(-EBUSY);
0190
0191     mchan = devm_kzalloc(dev, sizeof(*mchan), GFP_KERNEL);
0192     if (!mchan)
0193         return ERR_PTR(-ENOMEM);
0194
0195     mchan->client_id = ph->args[0];
0196     mchan->signal_id = ph->args[1];
0197     chan->con_priv = mchan;
0198
0199     return chan;
0200 }
0201
0202 static const struct mbox_chan_ops ipcc_mbox_chan_ops = {
0203     .send_data = qcom_ipcc_mbox_send_data,
0204     .shutdown = qcom_ipcc_mbox_shutdown,
0205 };
0206
0207 static int qcom_ipcc_setup_mbox(struct qcom_ipcc *ipcc,
0208                 struct device_node *controller_dn)
0209 {
0210     struct of_phandle_args curr_ph;
0211     struct device_node *client_dn;
0212     struct mbox_controller *mbox;
0213     struct device *dev = ipcc->dev;
0214     int i, j, ret;
0215
0216     /*
0217      * Find out the number of clients interested in this mailbox
0218      * and create channels accordingly.
0219      */
0220     ipcc->num_chans = 0;
0221     for_each_node_with_property(client_dn, "mboxes") {
0222         if (!of_device_is_available(client_dn))
0223             continue;
0224         i = of_count_phandle_with_args(client_dn,
0225                         "mboxes", "#mbox-cells");
0226         for (j = 0; j < i; j++) {
0227             ret = of_parse_phandle_with_args(client_dn, "mboxes",
0228                         "#mbox-cells", j, &curr_ph);
0229             of_node_put(curr_ph.np);
0230             if (!ret && curr_ph.np == controller_dn) {
0231                 ipcc->num_chans++;
0232                 break;
0233             }
0234         }
0235     }
0236
0237     /* If no clients are found, skip registering as a mbox controller */
0238     if (!ipcc->num_chans)
0239         return 0;
0240
0241     ipcc->chans = devm_kcalloc(dev, ipcc->num_chans,
0242                     sizeof(struct mbox_chan), GFP_KERNEL);
0243     if (!ipcc->chans)
0244         return -ENOMEM;
0245
0246     mbox = &ipcc->mbox;
0247     mbox->dev = dev;
0248     mbox->num_chans = ipcc->num_chans;
0249     mbox->chans = ipcc->chans;
0250     mbox->ops = &ipcc_mbox_chan_ops;
0251     mbox->of_xlate = qcom_ipcc_mbox_xlate;
0252     mbox->txdone_irq = false;
0253     mbox->txdone_poll = false;
0254
0255     return devm_mbox_controller_register(dev, mbox);
0256 }
0257
0258 static int qcom_ipcc_pm_resume(struct device *dev)
0259 {
0260     struct qcom_ipcc *ipcc = dev_get_drvdata(dev);
0261     u32 hwirq;
0262     int virq;
0263
0264     hwirq = readl(ipcc->base + IPCC_REG_RECV_ID);
0265     if (hwirq == IPCC_NO_PENDING_IRQ)
0266         return 0;
0267
0268     virq = irq_find_mapping(ipcc->irq_domain, hwirq);
0269
0270     dev_dbg(dev, "virq: %d triggered client-id: %ld; signal-id: %ld\n", virq,
0271         FIELD_GET(IPCC_CLIENT_ID_MASK, hwirq), FIELD_GET(IPCC_SIGNAL_ID_MASK, hwirq));
0272
0273     return 0;
0274 }
0275
0276 static int qcom_ipcc_probe(struct platform_device *pdev)
0277 {
0278     struct qcom_ipcc *ipcc;
0279     static int id;
0280     char *name;
0281     int ret;
0282
0283     ipcc = devm_kzalloc(&pdev->dev, sizeof(*ipcc), GFP_KERNEL);
0284     if (!ipcc)
0285         return -ENOMEM;
0286
0287     ipcc->dev = &pdev->dev;
0288
0289     ipcc->base = devm_platform_ioremap_resource(pdev, 0);
0290     if (IS_ERR(ipcc->base))
0291         return PTR_ERR(ipcc->base);
0292
0293     ipcc->irq = platform_get_irq(pdev, 0);
0294     if (ipcc->irq < 0)
0295         return ipcc->irq;
0296
0297     name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "ipcc_%d", id++);
0298     if (!name)
0299         return -ENOMEM;
0300
0301     ipcc->irq_domain = irq_domain_add_tree(pdev->dev.of_node,
0302                            &qcom_ipcc_irq_ops, ipcc);
0303     if (!ipcc->irq_domain)
0304         return -ENOMEM;
0305
0306     ret = qcom_ipcc_setup_mbox(ipcc, pdev->dev.of_node);
0307     if (ret)
0308         goto err_mbox;
0309
0310     ret = devm_request_irq(&pdev->dev, ipcc->irq, qcom_ipcc_irq_fn,
0311                    IRQF_TRIGGER_HIGH | IRQF_NO_SUSPEND, name, ipcc);
0312     if (ret < 0) {
0313         dev_err(&pdev->dev, "Failed to register the irq: %d\n", ret);
0314         goto err_req_irq;
0315     }
0316
0317     platform_set_drvdata(pdev, ipcc);
0318
0319     return 0;
0320
0321 err_req_irq:
0322     if (ipcc->num_chans)
0323         mbox_controller_unregister(&ipcc->mbox);
0324 err_mbox:
0325     irq_domain_remove(ipcc->irq_domain);
0326
0327     return ret;
0328 }
0329
0330 static int qcom_ipcc_remove(struct platform_device *pdev)
0331 {
0332     struct qcom_ipcc *ipcc = platform_get_drvdata(pdev);
0333
0334     disable_irq_wake(ipcc->irq);
0335     irq_domain_remove(ipcc->irq_domain);
0336
0337     return 0;
0338 }
0339
0340 static const struct of_device_id qcom_ipcc_of_match[] = {
0341     { .compatible = "qcom,ipcc"},
0342     {}
0343 };
0344 MODULE_DEVICE_TABLE(of, qcom_ipcc_of_match);
0345
0346 static const struct dev_pm_ops qcom_ipcc_dev_pm_ops = {
0347     NOIRQ_SYSTEM_SLEEP_PM_OPS(NULL, qcom_ipcc_pm_resume)
0348 };
0349
0350 static struct platform_driver qcom_ipcc_driver = {
0351     .probe = qcom_ipcc_probe,
0352     .remove = qcom_ipcc_remove,
0353     .driver = {
0354         .name = "qcom-ipcc",
0355         .of_match_table = qcom_ipcc_of_match,
0356         .suppress_bind_attrs = true,
0357         .pm = pm_sleep_ptr(&qcom_ipcc_dev_pm_ops),
0358     },
0359 };
0360
0361 static int __init qcom_ipcc_init(void)
0362 {
0363     return platform_driver_register(&qcom_ipcc_driver);
0364 }
0365 arch_initcall(qcom_ipcc_init);
0366
0367 MODULE_AUTHOR("Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>");
0368 MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");
0369 MODULE_DESCRIPTION("Qualcomm Technologies, Inc. IPCC driver");
0370 MODULE_LICENSE("GPL v2");