drivers/mailbox/pl320-ipc.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright 2012 Calxeda, Inc.
0004  */
0005 #include <linux/types.h>
0006 #include <linux/err.h>
0007 #include <linux/delay.h>
0008 #include <linux/export.h>
0009 #include <linux/io.h>
0010 #include <linux/interrupt.h>
0011 #include <linux/completion.h>
0012 #include <linux/mutex.h>
0013 #include <linux/notifier.h>
0014 #include <linux/spinlock.h>
0015 #include <linux/device.h>
0016 #include <linux/amba/bus.h>
0017
0018 #include <linux/pl320-ipc.h>
0019
0020 #define IPCMxSOURCE(m)      ((m) * 0x40)
0021 #define IPCMxDSET(m)        (((m) * 0x40) + 0x004)
0022 #define IPCMxDCLEAR(m)      (((m) * 0x40) + 0x008)
0023 #define IPCMxDSTATUS(m)     (((m) * 0x40) + 0x00C)
0024 #define IPCMxMODE(m)        (((m) * 0x40) + 0x010)
0025 #define IPCMxMSET(m)        (((m) * 0x40) + 0x014)
0026 #define IPCMxMCLEAR(m)      (((m) * 0x40) + 0x018)
0027 #define IPCMxMSTATUS(m)     (((m) * 0x40) + 0x01C)
0028 #define IPCMxSEND(m)        (((m) * 0x40) + 0x020)
0029 #define IPCMxDR(m, dr)      (((m) * 0x40) + ((dr) * 4) + 0x024)
0030
0031 #define IPCMMIS(irq)        (((irq) * 8) + 0x800)
0032 #define IPCMRIS(irq)        (((irq) * 8) + 0x804)
0033
0034 #define MBOX_MASK(n)        (1 << (n))
0035 #define IPC_TX_MBOX     1
0036 #define IPC_RX_MBOX     2
0037
0038 #define CHAN_MASK(n)        (1 << (n))
0039 #define A9_SOURCE       1
0040 #define M3_SOURCE       0
0041
0042 static void __iomem *ipc_base;
0043 static int ipc_irq;
0044 static DEFINE_MUTEX(ipc_m1_lock);
0045 static DECLARE_COMPLETION(ipc_completion);
0046 static ATOMIC_NOTIFIER_HEAD(ipc_notifier);
0047
0048 static inline void set_destination(int source, int mbox)
0049 {
0050     writel_relaxed(CHAN_MASK(source), ipc_base + IPCMxDSET(mbox));
0051     writel_relaxed(CHAN_MASK(source), ipc_base + IPCMxMSET(mbox));
0052 }
0053
0054 static inline void clear_destination(int source, int mbox)
0055 {
0056     writel_relaxed(CHAN_MASK(source), ipc_base + IPCMxDCLEAR(mbox));
0057     writel_relaxed(CHAN_MASK(source), ipc_base + IPCMxMCLEAR(mbox));
0058 }
0059
0060 static void __ipc_send(int mbox, u32 *data)
0061 {
0062     int i;
0063     for (i = 0; i < 7; i++)
0064         writel_relaxed(data[i], ipc_base + IPCMxDR(mbox, i));
0065     writel_relaxed(0x1, ipc_base + IPCMxSEND(mbox));
0066 }
0067
0068 static u32 __ipc_rcv(int mbox, u32 *data)
0069 {
0070     int i;
0071     for (i = 0; i < 7; i++)
0072         data[i] = readl_relaxed(ipc_base + IPCMxDR(mbox, i));
0073     return data[1];
0074 }
0075
0076 /* blocking implementation from the A9 side, not usable in interrupts! */
0077 int pl320_ipc_transmit(u32 *data)
0078 {
0079     int ret;
0080
0081     mutex_lock(&ipc_m1_lock);
0082
0083     init_completion(&ipc_completion);
0084     __ipc_send(IPC_TX_MBOX, data);
0085     ret = wait_for_completion_timeout(&ipc_completion,
0086                       msecs_to_jiffies(1000));
0087     if (ret == 0) {
0088         ret = -ETIMEDOUT;
0089         goto out;
0090     }
0091
0092     ret = __ipc_rcv(IPC_TX_MBOX, data);
0093 out:
0094     mutex_unlock(&ipc_m1_lock);
0095     return ret;
0096 }
0097 EXPORT_SYMBOL_GPL(pl320_ipc_transmit);
0098
0099 static irqreturn_t ipc_handler(int irq, void *dev)
0100 {
0101     u32 irq_stat;
0102     u32 data[7];
0103
0104     irq_stat = readl_relaxed(ipc_base + IPCMMIS(1));
0105     if (irq_stat & MBOX_MASK(IPC_TX_MBOX)) {
0106         writel_relaxed(0, ipc_base + IPCMxSEND(IPC_TX_MBOX));
0107         complete(&ipc_completion);
0108     }
0109     if (irq_stat & MBOX_MASK(IPC_RX_MBOX)) {
0110         __ipc_rcv(IPC_RX_MBOX, data);
0111         atomic_notifier_call_chain(&ipc_notifier, data[0], data + 1);
0112         writel_relaxed(2, ipc_base + IPCMxSEND(IPC_RX_MBOX));
0113     }
0114
0115     return IRQ_HANDLED;
0116 }
0117
0118 int pl320_ipc_register_notifier(struct notifier_block *nb)
0119 {
0120     return atomic_notifier_chain_register(&ipc_notifier, nb);
0121 }
0122 EXPORT_SYMBOL_GPL(pl320_ipc_register_notifier);
0123
0124 int pl320_ipc_unregister_notifier(struct notifier_block *nb)
0125 {
0126     return atomic_notifier_chain_unregister(&ipc_notifier, nb);
0127 }
0128 EXPORT_SYMBOL_GPL(pl320_ipc_unregister_notifier);
0129
0130 static int pl320_probe(struct amba_device *adev, const struct amba_id *id)
0131 {
0132     int ret;
0133
0134     ipc_base = ioremap(adev->res.start, resource_size(&adev->res));
0135     if (ipc_base == NULL)
0136         return -ENOMEM;
0137
0138     writel_relaxed(0, ipc_base + IPCMxSEND(IPC_TX_MBOX));
0139
0140     ipc_irq = adev->irq[0];
0141     ret = request_irq(ipc_irq, ipc_handler, 0, dev_name(&adev->dev), NULL);
0142     if (ret < 0)
0143         goto err;
0144
0145     /* Init slow mailbox */
0146     writel_relaxed(CHAN_MASK(A9_SOURCE),
0147                ipc_base + IPCMxSOURCE(IPC_TX_MBOX));
0148     writel_relaxed(CHAN_MASK(M3_SOURCE),
0149                ipc_base + IPCMxDSET(IPC_TX_MBOX));
0150     writel_relaxed(CHAN_MASK(M3_SOURCE) | CHAN_MASK(A9_SOURCE),
0151                ipc_base + IPCMxMSET(IPC_TX_MBOX));
0152
0153     /* Init receive mailbox */
0154     writel_relaxed(CHAN_MASK(M3_SOURCE),
0155                ipc_base + IPCMxSOURCE(IPC_RX_MBOX));
0156     writel_relaxed(CHAN_MASK(A9_SOURCE),
0157                ipc_base + IPCMxDSET(IPC_RX_MBOX));
0158     writel_relaxed(CHAN_MASK(M3_SOURCE) | CHAN_MASK(A9_SOURCE),
0159                ipc_base + IPCMxMSET(IPC_RX_MBOX));
0160
0161     return 0;
0162 err:
0163     iounmap(ipc_base);
0164     return ret;
0165 }
0166
0167 static struct amba_id pl320_ids[] = {
0168     {
0169         .id = 0x00041320,
0170         .mask   = 0x000fffff,
0171     },
0172     { 0, 0 },
0173 };
0174
0175 static struct amba_driver pl320_driver = {
0176     .drv = {
0177         .name   = "pl320",
0178     },
0179     .id_table   = pl320_ids,
0180     .probe      = pl320_probe,
0181 };
0182
0183 static int __init ipc_init(void)
0184 {
0185     return amba_driver_register(&pl320_driver);
0186 }
0187 subsys_initcall(ipc_init);