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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * OMAP mailbox driver
0004  *
0005  * Copyright (C) 2006-2009 Nokia Corporation. All rights reserved.
0006  * Copyright (C) 2013-2021 Texas Instruments Incorporated - https://www.ti.com
0007  *
0008  * Contact: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
0009  *          Suman Anna <s-anna@ti.com>
0010  */
0011 
0012 #include <linux/interrupt.h>
0013 #include <linux/spinlock.h>
0014 #include <linux/mutex.h>
0015 #include <linux/slab.h>
0016 #include <linux/kfifo.h>
0017 #include <linux/err.h>
0018 #include <linux/module.h>
0019 #include <linux/of_device.h>
0020 #include <linux/platform_device.h>
0021 #include <linux/pm_runtime.h>
0022 #include <linux/omap-mailbox.h>
0023 #include <linux/mailbox_controller.h>
0024 #include <linux/mailbox_client.h>
0025 
0026 #include "mailbox.h"
0027 
0028 #define MAILBOX_REVISION        0x000
0029 #define MAILBOX_MESSAGE(m)      (0x040 + 4 * (m))
0030 #define MAILBOX_FIFOSTATUS(m)       (0x080 + 4 * (m))
0031 #define MAILBOX_MSGSTATUS(m)        (0x0c0 + 4 * (m))
0032 
0033 #define OMAP2_MAILBOX_IRQSTATUS(u)  (0x100 + 8 * (u))
0034 #define OMAP2_MAILBOX_IRQENABLE(u)  (0x104 + 8 * (u))
0035 
0036 #define OMAP4_MAILBOX_IRQSTATUS(u)  (0x104 + 0x10 * (u))
0037 #define OMAP4_MAILBOX_IRQENABLE(u)  (0x108 + 0x10 * (u))
0038 #define OMAP4_MAILBOX_IRQENABLE_CLR(u)  (0x10c + 0x10 * (u))
0039 
0040 #define MAILBOX_IRQSTATUS(type, u)  (type ? OMAP4_MAILBOX_IRQSTATUS(u) : \
0041                         OMAP2_MAILBOX_IRQSTATUS(u))
0042 #define MAILBOX_IRQENABLE(type, u)  (type ? OMAP4_MAILBOX_IRQENABLE(u) : \
0043                         OMAP2_MAILBOX_IRQENABLE(u))
0044 #define MAILBOX_IRQDISABLE(type, u) (type ? OMAP4_MAILBOX_IRQENABLE_CLR(u) \
0045                         : OMAP2_MAILBOX_IRQENABLE(u))
0046 
0047 #define MAILBOX_IRQ_NEWMSG(m)       (1 << (2 * (m)))
0048 #define MAILBOX_IRQ_NOTFULL(m)      (1 << (2 * (m) + 1))
0049 
0050 /* Interrupt register configuration types */
0051 #define MBOX_INTR_CFG_TYPE1     0
0052 #define MBOX_INTR_CFG_TYPE2     1
0053 
0054 struct omap_mbox_fifo {
0055     unsigned long msg;
0056     unsigned long fifo_stat;
0057     unsigned long msg_stat;
0058     unsigned long irqenable;
0059     unsigned long irqstatus;
0060     unsigned long irqdisable;
0061     u32 intr_bit;
0062 };
0063 
0064 struct omap_mbox_queue {
0065     spinlock_t      lock;
0066     struct kfifo        fifo;
0067     struct work_struct  work;
0068     struct omap_mbox    *mbox;
0069     bool full;
0070 };
0071 
0072 struct omap_mbox_match_data {
0073     u32 intr_type;
0074 };
0075 
0076 struct omap_mbox_device {
0077     struct device *dev;
0078     struct mutex cfg_lock;
0079     void __iomem *mbox_base;
0080     u32 *irq_ctx;
0081     u32 num_users;
0082     u32 num_fifos;
0083     u32 intr_type;
0084     struct omap_mbox **mboxes;
0085     struct mbox_controller controller;
0086     struct list_head elem;
0087 };
0088 
0089 struct omap_mbox_fifo_info {
0090     int tx_id;
0091     int tx_usr;
0092     int tx_irq;
0093 
0094     int rx_id;
0095     int rx_usr;
0096     int rx_irq;
0097 
0098     const char *name;
0099     bool send_no_irq;
0100 };
0101 
0102 struct omap_mbox {
0103     const char      *name;
0104     int         irq;
0105     struct omap_mbox_queue  *rxq;
0106     struct device       *dev;
0107     struct omap_mbox_device *parent;
0108     struct omap_mbox_fifo   tx_fifo;
0109     struct omap_mbox_fifo   rx_fifo;
0110     u32         intr_type;
0111     struct mbox_chan    *chan;
0112     bool            send_no_irq;
0113 };
0114 
0115 /* global variables for the mailbox devices */
0116 static DEFINE_MUTEX(omap_mbox_devices_lock);
0117 static LIST_HEAD(omap_mbox_devices);
0118 
0119 static unsigned int mbox_kfifo_size = CONFIG_OMAP_MBOX_KFIFO_SIZE;
0120 module_param(mbox_kfifo_size, uint, S_IRUGO);
0121 MODULE_PARM_DESC(mbox_kfifo_size, "Size of omap's mailbox kfifo (bytes)");
0122 
0123 static struct omap_mbox *mbox_chan_to_omap_mbox(struct mbox_chan *chan)
0124 {
0125     if (!chan || !chan->con_priv)
0126         return NULL;
0127 
0128     return (struct omap_mbox *)chan->con_priv;
0129 }
0130 
0131 static inline
0132 unsigned int mbox_read_reg(struct omap_mbox_device *mdev, size_t ofs)
0133 {
0134     return __raw_readl(mdev->mbox_base + ofs);
0135 }
0136 
0137 static inline
0138 void mbox_write_reg(struct omap_mbox_device *mdev, u32 val, size_t ofs)
0139 {
0140     __raw_writel(val, mdev->mbox_base + ofs);
0141 }
0142 
0143 /* Mailbox FIFO handle functions */
0144 static u32 mbox_fifo_read(struct omap_mbox *mbox)
0145 {
0146     struct omap_mbox_fifo *fifo = &mbox->rx_fifo;
0147 
0148     return mbox_read_reg(mbox->parent, fifo->msg);
0149 }
0150 
0151 static void mbox_fifo_write(struct omap_mbox *mbox, u32 msg)
0152 {
0153     struct omap_mbox_fifo *fifo = &mbox->tx_fifo;
0154 
0155     mbox_write_reg(mbox->parent, msg, fifo->msg);
0156 }
0157 
0158 static int mbox_fifo_empty(struct omap_mbox *mbox)
0159 {
0160     struct omap_mbox_fifo *fifo = &mbox->rx_fifo;
0161 
0162     return (mbox_read_reg(mbox->parent, fifo->msg_stat) == 0);
0163 }
0164 
0165 static int mbox_fifo_full(struct omap_mbox *mbox)
0166 {
0167     struct omap_mbox_fifo *fifo = &mbox->tx_fifo;
0168 
0169     return mbox_read_reg(mbox->parent, fifo->fifo_stat);
0170 }
0171 
0172 /* Mailbox IRQ handle functions */
0173 static void ack_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
0174 {
0175     struct omap_mbox_fifo *fifo = (irq == IRQ_TX) ?
0176                 &mbox->tx_fifo : &mbox->rx_fifo;
0177     u32 bit = fifo->intr_bit;
0178     u32 irqstatus = fifo->irqstatus;
0179 
0180     mbox_write_reg(mbox->parent, bit, irqstatus);
0181 
0182     /* Flush posted write for irq status to avoid spurious interrupts */
0183     mbox_read_reg(mbox->parent, irqstatus);
0184 }
0185 
0186 static int is_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
0187 {
0188     struct omap_mbox_fifo *fifo = (irq == IRQ_TX) ?
0189                 &mbox->tx_fifo : &mbox->rx_fifo;
0190     u32 bit = fifo->intr_bit;
0191     u32 irqenable = fifo->irqenable;
0192     u32 irqstatus = fifo->irqstatus;
0193 
0194     u32 enable = mbox_read_reg(mbox->parent, irqenable);
0195     u32 status = mbox_read_reg(mbox->parent, irqstatus);
0196 
0197     return (int)(enable & status & bit);
0198 }
0199 
0200 static void _omap_mbox_enable_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
0201 {
0202     u32 l;
0203     struct omap_mbox_fifo *fifo = (irq == IRQ_TX) ?
0204                 &mbox->tx_fifo : &mbox->rx_fifo;
0205     u32 bit = fifo->intr_bit;
0206     u32 irqenable = fifo->irqenable;
0207 
0208     l = mbox_read_reg(mbox->parent, irqenable);
0209     l |= bit;
0210     mbox_write_reg(mbox->parent, l, irqenable);
0211 }
0212 
0213 static void _omap_mbox_disable_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
0214 {
0215     struct omap_mbox_fifo *fifo = (irq == IRQ_TX) ?
0216                 &mbox->tx_fifo : &mbox->rx_fifo;
0217     u32 bit = fifo->intr_bit;
0218     u32 irqdisable = fifo->irqdisable;
0219 
0220     /*
0221      * Read and update the interrupt configuration register for pre-OMAP4.
0222      * OMAP4 and later SoCs have a dedicated interrupt disabling register.
0223      */
0224     if (!mbox->intr_type)
0225         bit = mbox_read_reg(mbox->parent, irqdisable) & ~bit;
0226 
0227     mbox_write_reg(mbox->parent, bit, irqdisable);
0228 }
0229 
0230 void omap_mbox_enable_irq(struct mbox_chan *chan, omap_mbox_irq_t irq)
0231 {
0232     struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan);
0233 
0234     if (WARN_ON(!mbox))
0235         return;
0236 
0237     _omap_mbox_enable_irq(mbox, irq);
0238 }
0239 EXPORT_SYMBOL(omap_mbox_enable_irq);
0240 
0241 void omap_mbox_disable_irq(struct mbox_chan *chan, omap_mbox_irq_t irq)
0242 {
0243     struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan);
0244 
0245     if (WARN_ON(!mbox))
0246         return;
0247 
0248     _omap_mbox_disable_irq(mbox, irq);
0249 }
0250 EXPORT_SYMBOL(omap_mbox_disable_irq);
0251 
0252 /*
0253  * Message receiver(workqueue)
0254  */
0255 static void mbox_rx_work(struct work_struct *work)
0256 {
0257     struct omap_mbox_queue *mq =
0258             container_of(work, struct omap_mbox_queue, work);
0259     mbox_msg_t data;
0260     u32 msg;
0261     int len;
0262 
0263     while (kfifo_len(&mq->fifo) >= sizeof(msg)) {
0264         len = kfifo_out(&mq->fifo, (unsigned char *)&msg, sizeof(msg));
0265         WARN_ON(len != sizeof(msg));
0266         data = msg;
0267 
0268         mbox_chan_received_data(mq->mbox->chan, (void *)data);
0269         spin_lock_irq(&mq->lock);
0270         if (mq->full) {
0271             mq->full = false;
0272             _omap_mbox_enable_irq(mq->mbox, IRQ_RX);
0273         }
0274         spin_unlock_irq(&mq->lock);
0275     }
0276 }
0277 
0278 /*
0279  * Mailbox interrupt handler
0280  */
0281 static void __mbox_tx_interrupt(struct omap_mbox *mbox)
0282 {
0283     _omap_mbox_disable_irq(mbox, IRQ_TX);
0284     ack_mbox_irq(mbox, IRQ_TX);
0285     mbox_chan_txdone(mbox->chan, 0);
0286 }
0287 
0288 static void __mbox_rx_interrupt(struct omap_mbox *mbox)
0289 {
0290     struct omap_mbox_queue *mq = mbox->rxq;
0291     u32 msg;
0292     int len;
0293 
0294     while (!mbox_fifo_empty(mbox)) {
0295         if (unlikely(kfifo_avail(&mq->fifo) < sizeof(msg))) {
0296             _omap_mbox_disable_irq(mbox, IRQ_RX);
0297             mq->full = true;
0298             goto nomem;
0299         }
0300 
0301         msg = mbox_fifo_read(mbox);
0302 
0303         len = kfifo_in(&mq->fifo, (unsigned char *)&msg, sizeof(msg));
0304         WARN_ON(len != sizeof(msg));
0305     }
0306 
0307     /* no more messages in the fifo. clear IRQ source. */
0308     ack_mbox_irq(mbox, IRQ_RX);
0309 nomem:
0310     schedule_work(&mbox->rxq->work);
0311 }
0312 
0313 static irqreturn_t mbox_interrupt(int irq, void *p)
0314 {
0315     struct omap_mbox *mbox = p;
0316 
0317     if (is_mbox_irq(mbox, IRQ_TX))
0318         __mbox_tx_interrupt(mbox);
0319 
0320     if (is_mbox_irq(mbox, IRQ_RX))
0321         __mbox_rx_interrupt(mbox);
0322 
0323     return IRQ_HANDLED;
0324 }
0325 
0326 static struct omap_mbox_queue *mbox_queue_alloc(struct omap_mbox *mbox,
0327                     void (*work)(struct work_struct *))
0328 {
0329     struct omap_mbox_queue *mq;
0330 
0331     if (!work)
0332         return NULL;
0333 
0334     mq = kzalloc(sizeof(*mq), GFP_KERNEL);
0335     if (!mq)
0336         return NULL;
0337 
0338     spin_lock_init(&mq->lock);
0339 
0340     if (kfifo_alloc(&mq->fifo, mbox_kfifo_size, GFP_KERNEL))
0341         goto error;
0342 
0343     INIT_WORK(&mq->work, work);
0344     return mq;
0345 
0346 error:
0347     kfree(mq);
0348     return NULL;
0349 }
0350 
0351 static void mbox_queue_free(struct omap_mbox_queue *q)
0352 {
0353     kfifo_free(&q->fifo);
0354     kfree(q);
0355 }
0356 
0357 static int omap_mbox_startup(struct omap_mbox *mbox)
0358 {
0359     int ret = 0;
0360     struct omap_mbox_queue *mq;
0361 
0362     mq = mbox_queue_alloc(mbox, mbox_rx_work);
0363     if (!mq)
0364         return -ENOMEM;
0365     mbox->rxq = mq;
0366     mq->mbox = mbox;
0367 
0368     ret = request_irq(mbox->irq, mbox_interrupt, IRQF_SHARED,
0369               mbox->name, mbox);
0370     if (unlikely(ret)) {
0371         pr_err("failed to register mailbox interrupt:%d\n", ret);
0372         goto fail_request_irq;
0373     }
0374 
0375     if (mbox->send_no_irq)
0376         mbox->chan->txdone_method = TXDONE_BY_ACK;
0377 
0378     _omap_mbox_enable_irq(mbox, IRQ_RX);
0379 
0380     return 0;
0381 
0382 fail_request_irq:
0383     mbox_queue_free(mbox->rxq);
0384     return ret;
0385 }
0386 
0387 static void omap_mbox_fini(struct omap_mbox *mbox)
0388 {
0389     _omap_mbox_disable_irq(mbox, IRQ_RX);
0390     free_irq(mbox->irq, mbox);
0391     flush_work(&mbox->rxq->work);
0392     mbox_queue_free(mbox->rxq);
0393 }
0394 
0395 static struct omap_mbox *omap_mbox_device_find(struct omap_mbox_device *mdev,
0396                            const char *mbox_name)
0397 {
0398     struct omap_mbox *_mbox, *mbox = NULL;
0399     struct omap_mbox **mboxes = mdev->mboxes;
0400     int i;
0401 
0402     if (!mboxes)
0403         return NULL;
0404 
0405     for (i = 0; (_mbox = mboxes[i]); i++) {
0406         if (!strcmp(_mbox->name, mbox_name)) {
0407             mbox = _mbox;
0408             break;
0409         }
0410     }
0411     return mbox;
0412 }
0413 
0414 struct mbox_chan *omap_mbox_request_channel(struct mbox_client *cl,
0415                         const char *chan_name)
0416 {
0417     struct device *dev = cl->dev;
0418     struct omap_mbox *mbox = NULL;
0419     struct omap_mbox_device *mdev;
0420     struct mbox_chan *chan;
0421     unsigned long flags;
0422     int ret;
0423 
0424     if (!dev)
0425         return ERR_PTR(-ENODEV);
0426 
0427     if (dev->of_node) {
0428         pr_err("%s: please use mbox_request_channel(), this API is supported only for OMAP non-DT usage\n",
0429                __func__);
0430         return ERR_PTR(-ENODEV);
0431     }
0432 
0433     mutex_lock(&omap_mbox_devices_lock);
0434     list_for_each_entry(mdev, &omap_mbox_devices, elem) {
0435         mbox = omap_mbox_device_find(mdev, chan_name);
0436         if (mbox)
0437             break;
0438     }
0439     mutex_unlock(&omap_mbox_devices_lock);
0440 
0441     if (!mbox || !mbox->chan)
0442         return ERR_PTR(-ENOENT);
0443 
0444     chan = mbox->chan;
0445     spin_lock_irqsave(&chan->lock, flags);
0446     chan->msg_free = 0;
0447     chan->msg_count = 0;
0448     chan->active_req = NULL;
0449     chan->cl = cl;
0450     init_completion(&chan->tx_complete);
0451     spin_unlock_irqrestore(&chan->lock, flags);
0452 
0453     ret = chan->mbox->ops->startup(chan);
0454     if (ret) {
0455         pr_err("Unable to startup the chan (%d)\n", ret);
0456         mbox_free_channel(chan);
0457         chan = ERR_PTR(ret);
0458     }
0459 
0460     return chan;
0461 }
0462 EXPORT_SYMBOL(omap_mbox_request_channel);
0463 
0464 static struct class omap_mbox_class = { .name = "mbox", };
0465 
0466 static int omap_mbox_register(struct omap_mbox_device *mdev)
0467 {
0468     int ret;
0469     int i;
0470     struct omap_mbox **mboxes;
0471 
0472     if (!mdev || !mdev->mboxes)
0473         return -EINVAL;
0474 
0475     mboxes = mdev->mboxes;
0476     for (i = 0; mboxes[i]; i++) {
0477         struct omap_mbox *mbox = mboxes[i];
0478 
0479         mbox->dev = device_create(&omap_mbox_class, mdev->dev,
0480                     0, mbox, "%s", mbox->name);
0481         if (IS_ERR(mbox->dev)) {
0482             ret = PTR_ERR(mbox->dev);
0483             goto err_out;
0484         }
0485     }
0486 
0487     mutex_lock(&omap_mbox_devices_lock);
0488     list_add(&mdev->elem, &omap_mbox_devices);
0489     mutex_unlock(&omap_mbox_devices_lock);
0490 
0491     ret = devm_mbox_controller_register(mdev->dev, &mdev->controller);
0492 
0493 err_out:
0494     if (ret) {
0495         while (i--)
0496             device_unregister(mboxes[i]->dev);
0497     }
0498     return ret;
0499 }
0500 
0501 static int omap_mbox_unregister(struct omap_mbox_device *mdev)
0502 {
0503     int i;
0504     struct omap_mbox **mboxes;
0505 
0506     if (!mdev || !mdev->mboxes)
0507         return -EINVAL;
0508 
0509     mutex_lock(&omap_mbox_devices_lock);
0510     list_del(&mdev->elem);
0511     mutex_unlock(&omap_mbox_devices_lock);
0512 
0513     mboxes = mdev->mboxes;
0514     for (i = 0; mboxes[i]; i++)
0515         device_unregister(mboxes[i]->dev);
0516     return 0;
0517 }
0518 
0519 static int omap_mbox_chan_startup(struct mbox_chan *chan)
0520 {
0521     struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan);
0522     struct omap_mbox_device *mdev = mbox->parent;
0523     int ret = 0;
0524 
0525     mutex_lock(&mdev->cfg_lock);
0526     pm_runtime_get_sync(mdev->dev);
0527     ret = omap_mbox_startup(mbox);
0528     if (ret)
0529         pm_runtime_put_sync(mdev->dev);
0530     mutex_unlock(&mdev->cfg_lock);
0531     return ret;
0532 }
0533 
0534 static void omap_mbox_chan_shutdown(struct mbox_chan *chan)
0535 {
0536     struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan);
0537     struct omap_mbox_device *mdev = mbox->parent;
0538 
0539     mutex_lock(&mdev->cfg_lock);
0540     omap_mbox_fini(mbox);
0541     pm_runtime_put_sync(mdev->dev);
0542     mutex_unlock(&mdev->cfg_lock);
0543 }
0544 
0545 static int omap_mbox_chan_send_noirq(struct omap_mbox *mbox, u32 msg)
0546 {
0547     int ret = -EBUSY;
0548 
0549     if (!mbox_fifo_full(mbox)) {
0550         _omap_mbox_enable_irq(mbox, IRQ_RX);
0551         mbox_fifo_write(mbox, msg);
0552         ret = 0;
0553         _omap_mbox_disable_irq(mbox, IRQ_RX);
0554 
0555         /* we must read and ack the interrupt directly from here */
0556         mbox_fifo_read(mbox);
0557         ack_mbox_irq(mbox, IRQ_RX);
0558     }
0559 
0560     return ret;
0561 }
0562 
0563 static int omap_mbox_chan_send(struct omap_mbox *mbox, u32 msg)
0564 {
0565     int ret = -EBUSY;
0566 
0567     if (!mbox_fifo_full(mbox)) {
0568         mbox_fifo_write(mbox, msg);
0569         ret = 0;
0570     }
0571 
0572     /* always enable the interrupt */
0573     _omap_mbox_enable_irq(mbox, IRQ_TX);
0574     return ret;
0575 }
0576 
0577 static int omap_mbox_chan_send_data(struct mbox_chan *chan, void *data)
0578 {
0579     struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan);
0580     int ret;
0581     u32 msg = omap_mbox_message(data);
0582 
0583     if (!mbox)
0584         return -EINVAL;
0585 
0586     if (mbox->send_no_irq)
0587         ret = omap_mbox_chan_send_noirq(mbox, msg);
0588     else
0589         ret = omap_mbox_chan_send(mbox, msg);
0590 
0591     return ret;
0592 }
0593 
0594 static const struct mbox_chan_ops omap_mbox_chan_ops = {
0595     .startup        = omap_mbox_chan_startup,
0596     .send_data      = omap_mbox_chan_send_data,
0597     .shutdown       = omap_mbox_chan_shutdown,
0598 };
0599 
0600 #ifdef CONFIG_PM_SLEEP
0601 static int omap_mbox_suspend(struct device *dev)
0602 {
0603     struct omap_mbox_device *mdev = dev_get_drvdata(dev);
0604     u32 usr, fifo, reg;
0605 
0606     if (pm_runtime_status_suspended(dev))
0607         return 0;
0608 
0609     for (fifo = 0; fifo < mdev->num_fifos; fifo++) {
0610         if (mbox_read_reg(mdev, MAILBOX_MSGSTATUS(fifo))) {
0611             dev_err(mdev->dev, "fifo %d has unexpected unread messages\n",
0612                 fifo);
0613             return -EBUSY;
0614         }
0615     }
0616 
0617     for (usr = 0; usr < mdev->num_users; usr++) {
0618         reg = MAILBOX_IRQENABLE(mdev->intr_type, usr);
0619         mdev->irq_ctx[usr] = mbox_read_reg(mdev, reg);
0620     }
0621 
0622     return 0;
0623 }
0624 
0625 static int omap_mbox_resume(struct device *dev)
0626 {
0627     struct omap_mbox_device *mdev = dev_get_drvdata(dev);
0628     u32 usr, reg;
0629 
0630     if (pm_runtime_status_suspended(dev))
0631         return 0;
0632 
0633     for (usr = 0; usr < mdev->num_users; usr++) {
0634         reg = MAILBOX_IRQENABLE(mdev->intr_type, usr);
0635         mbox_write_reg(mdev, mdev->irq_ctx[usr], reg);
0636     }
0637 
0638     return 0;
0639 }
0640 #endif
0641 
0642 static const struct dev_pm_ops omap_mbox_pm_ops = {
0643     SET_SYSTEM_SLEEP_PM_OPS(omap_mbox_suspend, omap_mbox_resume)
0644 };
0645 
0646 static const struct omap_mbox_match_data omap2_data = { MBOX_INTR_CFG_TYPE1 };
0647 static const struct omap_mbox_match_data omap4_data = { MBOX_INTR_CFG_TYPE2 };
0648 
0649 static const struct of_device_id omap_mailbox_of_match[] = {
0650     {
0651         .compatible = "ti,omap2-mailbox",
0652         .data       = &omap2_data,
0653     },
0654     {
0655         .compatible = "ti,omap3-mailbox",
0656         .data       = &omap2_data,
0657     },
0658     {
0659         .compatible = "ti,omap4-mailbox",
0660         .data       = &omap4_data,
0661     },
0662     {
0663         .compatible = "ti,am654-mailbox",
0664         .data       = &omap4_data,
0665     },
0666     {
0667         .compatible = "ti,am64-mailbox",
0668         .data       = &omap4_data,
0669     },
0670     {
0671         /* end */
0672     },
0673 };
0674 MODULE_DEVICE_TABLE(of, omap_mailbox_of_match);
0675 
0676 static struct mbox_chan *omap_mbox_of_xlate(struct mbox_controller *controller,
0677                         const struct of_phandle_args *sp)
0678 {
0679     phandle phandle = sp->args[0];
0680     struct device_node *node;
0681     struct omap_mbox_device *mdev;
0682     struct omap_mbox *mbox;
0683 
0684     mdev = container_of(controller, struct omap_mbox_device, controller);
0685     if (WARN_ON(!mdev))
0686         return ERR_PTR(-EINVAL);
0687 
0688     node = of_find_node_by_phandle(phandle);
0689     if (!node) {
0690         pr_err("%s: could not find node phandle 0x%x\n",
0691                __func__, phandle);
0692         return ERR_PTR(-ENODEV);
0693     }
0694 
0695     mbox = omap_mbox_device_find(mdev, node->name);
0696     of_node_put(node);
0697     return mbox ? mbox->chan : ERR_PTR(-ENOENT);
0698 }
0699 
0700 static int omap_mbox_probe(struct platform_device *pdev)
0701 {
0702     int ret;
0703     struct mbox_chan *chnls;
0704     struct omap_mbox **list, *mbox, *mboxblk;
0705     struct omap_mbox_fifo_info *finfo, *finfoblk;
0706     struct omap_mbox_device *mdev;
0707     struct omap_mbox_fifo *fifo;
0708     struct device_node *node = pdev->dev.of_node;
0709     struct device_node *child;
0710     const struct omap_mbox_match_data *match_data;
0711     u32 intr_type, info_count;
0712     u32 num_users, num_fifos;
0713     u32 tmp[3];
0714     u32 l;
0715     int i;
0716 
0717     if (!node) {
0718         pr_err("%s: only DT-based devices are supported\n", __func__);
0719         return -ENODEV;
0720     }
0721 
0722     match_data = of_device_get_match_data(&pdev->dev);
0723     if (!match_data)
0724         return -ENODEV;
0725     intr_type = match_data->intr_type;
0726 
0727     if (of_property_read_u32(node, "ti,mbox-num-users", &num_users))
0728         return -ENODEV;
0729 
0730     if (of_property_read_u32(node, "ti,mbox-num-fifos", &num_fifos))
0731         return -ENODEV;
0732 
0733     info_count = of_get_available_child_count(node);
0734     if (!info_count) {
0735         dev_err(&pdev->dev, "no available mbox devices found\n");
0736         return -ENODEV;
0737     }
0738 
0739     finfoblk = devm_kcalloc(&pdev->dev, info_count, sizeof(*finfoblk),
0740                 GFP_KERNEL);
0741     if (!finfoblk)
0742         return -ENOMEM;
0743 
0744     finfo = finfoblk;
0745     child = NULL;
0746     for (i = 0; i < info_count; i++, finfo++) {
0747         child = of_get_next_available_child(node, child);
0748         ret = of_property_read_u32_array(child, "ti,mbox-tx", tmp,
0749                          ARRAY_SIZE(tmp));
0750         if (ret)
0751             return ret;
0752         finfo->tx_id = tmp[0];
0753         finfo->tx_irq = tmp[1];
0754         finfo->tx_usr = tmp[2];
0755 
0756         ret = of_property_read_u32_array(child, "ti,mbox-rx", tmp,
0757                          ARRAY_SIZE(tmp));
0758         if (ret)
0759             return ret;
0760         finfo->rx_id = tmp[0];
0761         finfo->rx_irq = tmp[1];
0762         finfo->rx_usr = tmp[2];
0763 
0764         finfo->name = child->name;
0765 
0766         if (of_find_property(child, "ti,mbox-send-noirq", NULL))
0767             finfo->send_no_irq = true;
0768 
0769         if (finfo->tx_id >= num_fifos || finfo->rx_id >= num_fifos ||
0770             finfo->tx_usr >= num_users || finfo->rx_usr >= num_users)
0771             return -EINVAL;
0772     }
0773 
0774     mdev = devm_kzalloc(&pdev->dev, sizeof(*mdev), GFP_KERNEL);
0775     if (!mdev)
0776         return -ENOMEM;
0777 
0778     mdev->mbox_base = devm_platform_ioremap_resource(pdev, 0);
0779     if (IS_ERR(mdev->mbox_base))
0780         return PTR_ERR(mdev->mbox_base);
0781 
0782     mdev->irq_ctx = devm_kcalloc(&pdev->dev, num_users, sizeof(u32),
0783                      GFP_KERNEL);
0784     if (!mdev->irq_ctx)
0785         return -ENOMEM;
0786 
0787     /* allocate one extra for marking end of list */
0788     list = devm_kcalloc(&pdev->dev, info_count + 1, sizeof(*list),
0789                 GFP_KERNEL);
0790     if (!list)
0791         return -ENOMEM;
0792 
0793     chnls = devm_kcalloc(&pdev->dev, info_count + 1, sizeof(*chnls),
0794                  GFP_KERNEL);
0795     if (!chnls)
0796         return -ENOMEM;
0797 
0798     mboxblk = devm_kcalloc(&pdev->dev, info_count, sizeof(*mbox),
0799                    GFP_KERNEL);
0800     if (!mboxblk)
0801         return -ENOMEM;
0802 
0803     mbox = mboxblk;
0804     finfo = finfoblk;
0805     for (i = 0; i < info_count; i++, finfo++) {
0806         fifo = &mbox->tx_fifo;
0807         fifo->msg = MAILBOX_MESSAGE(finfo->tx_id);
0808         fifo->fifo_stat = MAILBOX_FIFOSTATUS(finfo->tx_id);
0809         fifo->intr_bit = MAILBOX_IRQ_NOTFULL(finfo->tx_id);
0810         fifo->irqenable = MAILBOX_IRQENABLE(intr_type, finfo->tx_usr);
0811         fifo->irqstatus = MAILBOX_IRQSTATUS(intr_type, finfo->tx_usr);
0812         fifo->irqdisable = MAILBOX_IRQDISABLE(intr_type, finfo->tx_usr);
0813 
0814         fifo = &mbox->rx_fifo;
0815         fifo->msg = MAILBOX_MESSAGE(finfo->rx_id);
0816         fifo->msg_stat =  MAILBOX_MSGSTATUS(finfo->rx_id);
0817         fifo->intr_bit = MAILBOX_IRQ_NEWMSG(finfo->rx_id);
0818         fifo->irqenable = MAILBOX_IRQENABLE(intr_type, finfo->rx_usr);
0819         fifo->irqstatus = MAILBOX_IRQSTATUS(intr_type, finfo->rx_usr);
0820         fifo->irqdisable = MAILBOX_IRQDISABLE(intr_type, finfo->rx_usr);
0821 
0822         mbox->send_no_irq = finfo->send_no_irq;
0823         mbox->intr_type = intr_type;
0824 
0825         mbox->parent = mdev;
0826         mbox->name = finfo->name;
0827         mbox->irq = platform_get_irq(pdev, finfo->tx_irq);
0828         if (mbox->irq < 0)
0829             return mbox->irq;
0830         mbox->chan = &chnls[i];
0831         chnls[i].con_priv = mbox;
0832         list[i] = mbox++;
0833     }
0834 
0835     mutex_init(&mdev->cfg_lock);
0836     mdev->dev = &pdev->dev;
0837     mdev->num_users = num_users;
0838     mdev->num_fifos = num_fifos;
0839     mdev->intr_type = intr_type;
0840     mdev->mboxes = list;
0841 
0842     /*
0843      * OMAP/K3 Mailbox IP does not have a Tx-Done IRQ, but rather a Tx-Ready
0844      * IRQ and is needed to run the Tx state machine
0845      */
0846     mdev->controller.txdone_irq = true;
0847     mdev->controller.dev = mdev->dev;
0848     mdev->controller.ops = &omap_mbox_chan_ops;
0849     mdev->controller.chans = chnls;
0850     mdev->controller.num_chans = info_count;
0851     mdev->controller.of_xlate = omap_mbox_of_xlate;
0852     ret = omap_mbox_register(mdev);
0853     if (ret)
0854         return ret;
0855 
0856     platform_set_drvdata(pdev, mdev);
0857     pm_runtime_enable(mdev->dev);
0858 
0859     ret = pm_runtime_resume_and_get(mdev->dev);
0860     if (ret < 0)
0861         goto unregister;
0862 
0863     /*
0864      * just print the raw revision register, the format is not
0865      * uniform across all SoCs
0866      */
0867     l = mbox_read_reg(mdev, MAILBOX_REVISION);
0868     dev_info(mdev->dev, "omap mailbox rev 0x%x\n", l);
0869 
0870     ret = pm_runtime_put_sync(mdev->dev);
0871     if (ret < 0 && ret != -ENOSYS)
0872         goto unregister;
0873 
0874     devm_kfree(&pdev->dev, finfoblk);
0875     return 0;
0876 
0877 unregister:
0878     pm_runtime_disable(mdev->dev);
0879     omap_mbox_unregister(mdev);
0880     return ret;
0881 }
0882 
0883 static int omap_mbox_remove(struct platform_device *pdev)
0884 {
0885     struct omap_mbox_device *mdev = platform_get_drvdata(pdev);
0886 
0887     pm_runtime_disable(mdev->dev);
0888     omap_mbox_unregister(mdev);
0889 
0890     return 0;
0891 }
0892 
0893 static struct platform_driver omap_mbox_driver = {
0894     .probe  = omap_mbox_probe,
0895     .remove = omap_mbox_remove,
0896     .driver = {
0897         .name = "omap-mailbox",
0898         .pm = &omap_mbox_pm_ops,
0899         .of_match_table = of_match_ptr(omap_mailbox_of_match),
0900     },
0901 };
0902 
0903 static int __init omap_mbox_init(void)
0904 {
0905     int err;
0906 
0907     err = class_register(&omap_mbox_class);
0908     if (err)
0909         return err;
0910 
0911     /* kfifo size sanity check: alignment and minimal size */
0912     mbox_kfifo_size = ALIGN(mbox_kfifo_size, sizeof(u32));
0913     mbox_kfifo_size = max_t(unsigned int, mbox_kfifo_size, sizeof(u32));
0914 
0915     err = platform_driver_register(&omap_mbox_driver);
0916     if (err)
0917         class_unregister(&omap_mbox_class);
0918 
0919     return err;
0920 }
0921 subsys_initcall(omap_mbox_init);
0922 
0923 static void __exit omap_mbox_exit(void)
0924 {
0925     platform_driver_unregister(&omap_mbox_driver);
0926     class_unregister(&omap_mbox_class);
0927 }
0928 module_exit(omap_mbox_exit);
0929 
0930 MODULE_LICENSE("GPL v2");
0931 MODULE_DESCRIPTION("omap mailbox: interrupt driven messaging");
0932 MODULE_AUTHOR("Toshihiro Kobayashi");
0933 MODULE_AUTHOR("Hiroshi DOYU");
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