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0001 // SPDX-License-Identifier: GPL-2.0
0002 //
0003 // Copyright (c) 2018 MediaTek Inc.
0004 
0005 #include <linux/bitops.h>
0006 #include <linux/clk.h>
0007 #include <linux/clk-provider.h>
0008 #include <linux/dma-mapping.h>
0009 #include <linux/errno.h>
0010 #include <linux/interrupt.h>
0011 #include <linux/io.h>
0012 #include <linux/iopoll.h>
0013 #include <linux/kernel.h>
0014 #include <linux/module.h>
0015 #include <linux/platform_device.h>
0016 #include <linux/mailbox_controller.h>
0017 #include <linux/mailbox/mtk-cmdq-mailbox.h>
0018 #include <linux/of_device.h>
0019 
0020 #define CMDQ_OP_CODE_MASK       (0xff << CMDQ_OP_CODE_SHIFT)
0021 #define CMDQ_NUM_CMD(t)         (t->cmd_buf_size / CMDQ_INST_SIZE)
0022 #define CMDQ_GCE_NUM_MAX        (2)
0023 
0024 #define CMDQ_CURR_IRQ_STATUS        0x10
0025 #define CMDQ_SYNC_TOKEN_UPDATE      0x68
0026 #define CMDQ_THR_SLOT_CYCLES        0x30
0027 #define CMDQ_THR_BASE           0x100
0028 #define CMDQ_THR_SIZE           0x80
0029 #define CMDQ_THR_WARM_RESET     0x00
0030 #define CMDQ_THR_ENABLE_TASK        0x04
0031 #define CMDQ_THR_SUSPEND_TASK       0x08
0032 #define CMDQ_THR_CURR_STATUS        0x0c
0033 #define CMDQ_THR_IRQ_STATUS     0x10
0034 #define CMDQ_THR_IRQ_ENABLE     0x14
0035 #define CMDQ_THR_CURR_ADDR      0x20
0036 #define CMDQ_THR_END_ADDR       0x24
0037 #define CMDQ_THR_WAIT_TOKEN     0x30
0038 #define CMDQ_THR_PRIORITY       0x40
0039 
0040 #define GCE_GCTL_VALUE          0x48
0041 
0042 #define CMDQ_THR_ACTIVE_SLOT_CYCLES 0x3200
0043 #define CMDQ_THR_ENABLED        0x1
0044 #define CMDQ_THR_DISABLED       0x0
0045 #define CMDQ_THR_SUSPEND        0x1
0046 #define CMDQ_THR_RESUME         0x0
0047 #define CMDQ_THR_STATUS_SUSPENDED   BIT(1)
0048 #define CMDQ_THR_DO_WARM_RESET      BIT(0)
0049 #define CMDQ_THR_IRQ_DONE       0x1
0050 #define CMDQ_THR_IRQ_ERROR      0x12
0051 #define CMDQ_THR_IRQ_EN         (CMDQ_THR_IRQ_ERROR | CMDQ_THR_IRQ_DONE)
0052 #define CMDQ_THR_IS_WAITING     BIT(31)
0053 
0054 #define CMDQ_JUMP_BY_OFFSET     0x10000000
0055 #define CMDQ_JUMP_BY_PA         0x10000001
0056 
0057 struct cmdq_thread {
0058     struct mbox_chan    *chan;
0059     void __iomem        *base;
0060     struct list_head    task_busy_list;
0061     u32         priority;
0062 };
0063 
0064 struct cmdq_task {
0065     struct cmdq     *cmdq;
0066     struct list_head    list_entry;
0067     dma_addr_t      pa_base;
0068     struct cmdq_thread  *thread;
0069     struct cmdq_pkt     *pkt; /* the packet sent from mailbox client */
0070 };
0071 
0072 struct cmdq {
0073     struct mbox_controller  mbox;
0074     void __iomem        *base;
0075     int         irq;
0076     u32         thread_nr;
0077     u32         irq_mask;
0078     struct cmdq_thread  *thread;
0079     struct clk_bulk_data    clocks[CMDQ_GCE_NUM_MAX];
0080     bool            suspended;
0081     u8          shift_pa;
0082     bool            control_by_sw;
0083     u32         gce_num;
0084 };
0085 
0086 struct gce_plat {
0087     u32 thread_nr;
0088     u8 shift;
0089     bool control_by_sw;
0090     u32 gce_num;
0091 };
0092 
0093 u8 cmdq_get_shift_pa(struct mbox_chan *chan)
0094 {
0095     struct cmdq *cmdq = container_of(chan->mbox, struct cmdq, mbox);
0096 
0097     return cmdq->shift_pa;
0098 }
0099 EXPORT_SYMBOL(cmdq_get_shift_pa);
0100 
0101 static int cmdq_thread_suspend(struct cmdq *cmdq, struct cmdq_thread *thread)
0102 {
0103     u32 status;
0104 
0105     writel(CMDQ_THR_SUSPEND, thread->base + CMDQ_THR_SUSPEND_TASK);
0106 
0107     /* If already disabled, treat as suspended successful. */
0108     if (!(readl(thread->base + CMDQ_THR_ENABLE_TASK) & CMDQ_THR_ENABLED))
0109         return 0;
0110 
0111     if (readl_poll_timeout_atomic(thread->base + CMDQ_THR_CURR_STATUS,
0112             status, status & CMDQ_THR_STATUS_SUSPENDED, 0, 10)) {
0113         dev_err(cmdq->mbox.dev, "suspend GCE thread 0x%x failed\n",
0114             (u32)(thread->base - cmdq->base));
0115         return -EFAULT;
0116     }
0117 
0118     return 0;
0119 }
0120 
0121 static void cmdq_thread_resume(struct cmdq_thread *thread)
0122 {
0123     writel(CMDQ_THR_RESUME, thread->base + CMDQ_THR_SUSPEND_TASK);
0124 }
0125 
0126 static void cmdq_init(struct cmdq *cmdq)
0127 {
0128     int i;
0129 
0130     WARN_ON(clk_bulk_enable(cmdq->gce_num, cmdq->clocks));
0131     if (cmdq->control_by_sw)
0132         writel(0x7, cmdq->base + GCE_GCTL_VALUE);
0133     writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base + CMDQ_THR_SLOT_CYCLES);
0134     for (i = 0; i <= CMDQ_MAX_EVENT; i++)
0135         writel(i, cmdq->base + CMDQ_SYNC_TOKEN_UPDATE);
0136     clk_bulk_disable(cmdq->gce_num, cmdq->clocks);
0137 }
0138 
0139 static int cmdq_thread_reset(struct cmdq *cmdq, struct cmdq_thread *thread)
0140 {
0141     u32 warm_reset;
0142 
0143     writel(CMDQ_THR_DO_WARM_RESET, thread->base + CMDQ_THR_WARM_RESET);
0144     if (readl_poll_timeout_atomic(thread->base + CMDQ_THR_WARM_RESET,
0145             warm_reset, !(warm_reset & CMDQ_THR_DO_WARM_RESET),
0146             0, 10)) {
0147         dev_err(cmdq->mbox.dev, "reset GCE thread 0x%x failed\n",
0148             (u32)(thread->base - cmdq->base));
0149         return -EFAULT;
0150     }
0151 
0152     return 0;
0153 }
0154 
0155 static void cmdq_thread_disable(struct cmdq *cmdq, struct cmdq_thread *thread)
0156 {
0157     cmdq_thread_reset(cmdq, thread);
0158     writel(CMDQ_THR_DISABLED, thread->base + CMDQ_THR_ENABLE_TASK);
0159 }
0160 
0161 /* notify GCE to re-fetch commands by setting GCE thread PC */
0162 static void cmdq_thread_invalidate_fetched_data(struct cmdq_thread *thread)
0163 {
0164     writel(readl(thread->base + CMDQ_THR_CURR_ADDR),
0165            thread->base + CMDQ_THR_CURR_ADDR);
0166 }
0167 
0168 static void cmdq_task_insert_into_thread(struct cmdq_task *task)
0169 {
0170     struct device *dev = task->cmdq->mbox.dev;
0171     struct cmdq_thread *thread = task->thread;
0172     struct cmdq_task *prev_task = list_last_entry(
0173             &thread->task_busy_list, typeof(*task), list_entry);
0174     u64 *prev_task_base = prev_task->pkt->va_base;
0175 
0176     /* let previous task jump to this task */
0177     dma_sync_single_for_cpu(dev, prev_task->pa_base,
0178                 prev_task->pkt->cmd_buf_size, DMA_TO_DEVICE);
0179     prev_task_base[CMDQ_NUM_CMD(prev_task->pkt) - 1] =
0180         (u64)CMDQ_JUMP_BY_PA << 32 |
0181         (task->pa_base >> task->cmdq->shift_pa);
0182     dma_sync_single_for_device(dev, prev_task->pa_base,
0183                    prev_task->pkt->cmd_buf_size, DMA_TO_DEVICE);
0184 
0185     cmdq_thread_invalidate_fetched_data(thread);
0186 }
0187 
0188 static bool cmdq_thread_is_in_wfe(struct cmdq_thread *thread)
0189 {
0190     return readl(thread->base + CMDQ_THR_WAIT_TOKEN) & CMDQ_THR_IS_WAITING;
0191 }
0192 
0193 static void cmdq_task_exec_done(struct cmdq_task *task, int sta)
0194 {
0195     struct cmdq_cb_data data;
0196 
0197     data.sta = sta;
0198     data.pkt = task->pkt;
0199     mbox_chan_received_data(task->thread->chan, &data);
0200 
0201     list_del(&task->list_entry);
0202 }
0203 
0204 static void cmdq_task_handle_error(struct cmdq_task *task)
0205 {
0206     struct cmdq_thread *thread = task->thread;
0207     struct cmdq_task *next_task;
0208     struct cmdq *cmdq = task->cmdq;
0209 
0210     dev_err(cmdq->mbox.dev, "task 0x%p error\n", task);
0211     WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0);
0212     next_task = list_first_entry_or_null(&thread->task_busy_list,
0213             struct cmdq_task, list_entry);
0214     if (next_task)
0215         writel(next_task->pa_base >> cmdq->shift_pa,
0216                thread->base + CMDQ_THR_CURR_ADDR);
0217     cmdq_thread_resume(thread);
0218 }
0219 
0220 static void cmdq_thread_irq_handler(struct cmdq *cmdq,
0221                     struct cmdq_thread *thread)
0222 {
0223     struct cmdq_task *task, *tmp, *curr_task = NULL;
0224     u32 curr_pa, irq_flag, task_end_pa;
0225     bool err;
0226 
0227     irq_flag = readl(thread->base + CMDQ_THR_IRQ_STATUS);
0228     writel(~irq_flag, thread->base + CMDQ_THR_IRQ_STATUS);
0229 
0230     /*
0231      * When ISR call this function, another CPU core could run
0232      * "release task" right before we acquire the spin lock, and thus
0233      * reset / disable this GCE thread, so we need to check the enable
0234      * bit of this GCE thread.
0235      */
0236     if (!(readl(thread->base + CMDQ_THR_ENABLE_TASK) & CMDQ_THR_ENABLED))
0237         return;
0238 
0239     if (irq_flag & CMDQ_THR_IRQ_ERROR)
0240         err = true;
0241     else if (irq_flag & CMDQ_THR_IRQ_DONE)
0242         err = false;
0243     else
0244         return;
0245 
0246     curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR) << cmdq->shift_pa;
0247 
0248     list_for_each_entry_safe(task, tmp, &thread->task_busy_list,
0249                  list_entry) {
0250         task_end_pa = task->pa_base + task->pkt->cmd_buf_size;
0251         if (curr_pa >= task->pa_base && curr_pa < task_end_pa)
0252             curr_task = task;
0253 
0254         if (!curr_task || curr_pa == task_end_pa - CMDQ_INST_SIZE) {
0255             cmdq_task_exec_done(task, 0);
0256             kfree(task);
0257         } else if (err) {
0258             cmdq_task_exec_done(task, -ENOEXEC);
0259             cmdq_task_handle_error(curr_task);
0260             kfree(task);
0261         }
0262 
0263         if (curr_task)
0264             break;
0265     }
0266 
0267     if (list_empty(&thread->task_busy_list)) {
0268         cmdq_thread_disable(cmdq, thread);
0269         clk_bulk_disable(cmdq->gce_num, cmdq->clocks);
0270     }
0271 }
0272 
0273 static irqreturn_t cmdq_irq_handler(int irq, void *dev)
0274 {
0275     struct cmdq *cmdq = dev;
0276     unsigned long irq_status, flags = 0L;
0277     int bit;
0278 
0279     irq_status = readl(cmdq->base + CMDQ_CURR_IRQ_STATUS) & cmdq->irq_mask;
0280     if (!(irq_status ^ cmdq->irq_mask))
0281         return IRQ_NONE;
0282 
0283     for_each_clear_bit(bit, &irq_status, cmdq->thread_nr) {
0284         struct cmdq_thread *thread = &cmdq->thread[bit];
0285 
0286         spin_lock_irqsave(&thread->chan->lock, flags);
0287         cmdq_thread_irq_handler(cmdq, thread);
0288         spin_unlock_irqrestore(&thread->chan->lock, flags);
0289     }
0290 
0291     return IRQ_HANDLED;
0292 }
0293 
0294 static int cmdq_suspend(struct device *dev)
0295 {
0296     struct cmdq *cmdq = dev_get_drvdata(dev);
0297     struct cmdq_thread *thread;
0298     int i;
0299     bool task_running = false;
0300 
0301     cmdq->suspended = true;
0302 
0303     for (i = 0; i < cmdq->thread_nr; i++) {
0304         thread = &cmdq->thread[i];
0305         if (!list_empty(&thread->task_busy_list)) {
0306             task_running = true;
0307             break;
0308         }
0309     }
0310 
0311     if (task_running)
0312         dev_warn(dev, "exist running task(s) in suspend\n");
0313 
0314     clk_bulk_unprepare(cmdq->gce_num, cmdq->clocks);
0315 
0316     return 0;
0317 }
0318 
0319 static int cmdq_resume(struct device *dev)
0320 {
0321     struct cmdq *cmdq = dev_get_drvdata(dev);
0322 
0323     WARN_ON(clk_bulk_prepare(cmdq->gce_num, cmdq->clocks));
0324     cmdq->suspended = false;
0325     return 0;
0326 }
0327 
0328 static int cmdq_remove(struct platform_device *pdev)
0329 {
0330     struct cmdq *cmdq = platform_get_drvdata(pdev);
0331 
0332     clk_bulk_unprepare(cmdq->gce_num, cmdq->clocks);
0333     return 0;
0334 }
0335 
0336 static int cmdq_mbox_send_data(struct mbox_chan *chan, void *data)
0337 {
0338     struct cmdq_pkt *pkt = (struct cmdq_pkt *)data;
0339     struct cmdq_thread *thread = (struct cmdq_thread *)chan->con_priv;
0340     struct cmdq *cmdq = dev_get_drvdata(chan->mbox->dev);
0341     struct cmdq_task *task;
0342     unsigned long curr_pa, end_pa;
0343 
0344     /* Client should not flush new tasks if suspended. */
0345     WARN_ON(cmdq->suspended);
0346 
0347     task = kzalloc(sizeof(*task), GFP_ATOMIC);
0348     if (!task)
0349         return -ENOMEM;
0350 
0351     task->cmdq = cmdq;
0352     INIT_LIST_HEAD(&task->list_entry);
0353     task->pa_base = pkt->pa_base;
0354     task->thread = thread;
0355     task->pkt = pkt;
0356 
0357     if (list_empty(&thread->task_busy_list)) {
0358         WARN_ON(clk_bulk_enable(cmdq->gce_num, cmdq->clocks));
0359 
0360         /*
0361          * The thread reset will clear thread related register to 0,
0362          * including pc, end, priority, irq, suspend and enable. Thus
0363          * set CMDQ_THR_ENABLED to CMDQ_THR_ENABLE_TASK will enable
0364          * thread and make it running.
0365          */
0366         WARN_ON(cmdq_thread_reset(cmdq, thread) < 0);
0367 
0368         writel(task->pa_base >> cmdq->shift_pa,
0369                thread->base + CMDQ_THR_CURR_ADDR);
0370         writel((task->pa_base + pkt->cmd_buf_size) >> cmdq->shift_pa,
0371                thread->base + CMDQ_THR_END_ADDR);
0372 
0373         writel(thread->priority, thread->base + CMDQ_THR_PRIORITY);
0374         writel(CMDQ_THR_IRQ_EN, thread->base + CMDQ_THR_IRQ_ENABLE);
0375         writel(CMDQ_THR_ENABLED, thread->base + CMDQ_THR_ENABLE_TASK);
0376     } else {
0377         WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0);
0378         curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR) <<
0379             cmdq->shift_pa;
0380         end_pa = readl(thread->base + CMDQ_THR_END_ADDR) <<
0381             cmdq->shift_pa;
0382         /* check boundary */
0383         if (curr_pa == end_pa - CMDQ_INST_SIZE ||
0384             curr_pa == end_pa) {
0385             /* set to this task directly */
0386             writel(task->pa_base >> cmdq->shift_pa,
0387                    thread->base + CMDQ_THR_CURR_ADDR);
0388         } else {
0389             cmdq_task_insert_into_thread(task);
0390             smp_mb(); /* modify jump before enable thread */
0391         }
0392         writel((task->pa_base + pkt->cmd_buf_size) >> cmdq->shift_pa,
0393                thread->base + CMDQ_THR_END_ADDR);
0394         cmdq_thread_resume(thread);
0395     }
0396     list_move_tail(&task->list_entry, &thread->task_busy_list);
0397 
0398     return 0;
0399 }
0400 
0401 static int cmdq_mbox_startup(struct mbox_chan *chan)
0402 {
0403     return 0;
0404 }
0405 
0406 static void cmdq_mbox_shutdown(struct mbox_chan *chan)
0407 {
0408     struct cmdq_thread *thread = (struct cmdq_thread *)chan->con_priv;
0409     struct cmdq *cmdq = dev_get_drvdata(chan->mbox->dev);
0410     struct cmdq_task *task, *tmp;
0411     unsigned long flags;
0412 
0413     spin_lock_irqsave(&thread->chan->lock, flags);
0414     if (list_empty(&thread->task_busy_list))
0415         goto done;
0416 
0417     WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0);
0418 
0419     /* make sure executed tasks have success callback */
0420     cmdq_thread_irq_handler(cmdq, thread);
0421     if (list_empty(&thread->task_busy_list))
0422         goto done;
0423 
0424     list_for_each_entry_safe(task, tmp, &thread->task_busy_list,
0425                  list_entry) {
0426         cmdq_task_exec_done(task, -ECONNABORTED);
0427         kfree(task);
0428     }
0429 
0430     cmdq_thread_disable(cmdq, thread);
0431     clk_bulk_disable(cmdq->gce_num, cmdq->clocks);
0432 
0433 done:
0434     /*
0435      * The thread->task_busy_list empty means thread already disable. The
0436      * cmdq_mbox_send_data() always reset thread which clear disable and
0437      * suspend statue when first pkt send to channel, so there is no need
0438      * to do any operation here, only unlock and leave.
0439      */
0440     spin_unlock_irqrestore(&thread->chan->lock, flags);
0441 }
0442 
0443 static int cmdq_mbox_flush(struct mbox_chan *chan, unsigned long timeout)
0444 {
0445     struct cmdq_thread *thread = (struct cmdq_thread *)chan->con_priv;
0446     struct cmdq_cb_data data;
0447     struct cmdq *cmdq = dev_get_drvdata(chan->mbox->dev);
0448     struct cmdq_task *task, *tmp;
0449     unsigned long flags;
0450     u32 enable;
0451 
0452     spin_lock_irqsave(&thread->chan->lock, flags);
0453     if (list_empty(&thread->task_busy_list))
0454         goto out;
0455 
0456     WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0);
0457     if (!cmdq_thread_is_in_wfe(thread))
0458         goto wait;
0459 
0460     list_for_each_entry_safe(task, tmp, &thread->task_busy_list,
0461                  list_entry) {
0462         data.sta = -ECONNABORTED;
0463         data.pkt = task->pkt;
0464         mbox_chan_received_data(task->thread->chan, &data);
0465         list_del(&task->list_entry);
0466         kfree(task);
0467     }
0468 
0469     cmdq_thread_resume(thread);
0470     cmdq_thread_disable(cmdq, thread);
0471     clk_bulk_disable(cmdq->gce_num, cmdq->clocks);
0472 
0473 out:
0474     spin_unlock_irqrestore(&thread->chan->lock, flags);
0475     return 0;
0476 
0477 wait:
0478     cmdq_thread_resume(thread);
0479     spin_unlock_irqrestore(&thread->chan->lock, flags);
0480     if (readl_poll_timeout_atomic(thread->base + CMDQ_THR_ENABLE_TASK,
0481                       enable, enable == 0, 1, timeout)) {
0482         dev_err(cmdq->mbox.dev, "Fail to wait GCE thread 0x%x done\n",
0483             (u32)(thread->base - cmdq->base));
0484 
0485         return -EFAULT;
0486     }
0487     return 0;
0488 }
0489 
0490 static const struct mbox_chan_ops cmdq_mbox_chan_ops = {
0491     .send_data = cmdq_mbox_send_data,
0492     .startup = cmdq_mbox_startup,
0493     .shutdown = cmdq_mbox_shutdown,
0494     .flush = cmdq_mbox_flush,
0495 };
0496 
0497 static struct mbox_chan *cmdq_xlate(struct mbox_controller *mbox,
0498         const struct of_phandle_args *sp)
0499 {
0500     int ind = sp->args[0];
0501     struct cmdq_thread *thread;
0502 
0503     if (ind >= mbox->num_chans)
0504         return ERR_PTR(-EINVAL);
0505 
0506     thread = (struct cmdq_thread *)mbox->chans[ind].con_priv;
0507     thread->priority = sp->args[1];
0508     thread->chan = &mbox->chans[ind];
0509 
0510     return &mbox->chans[ind];
0511 }
0512 
0513 static int cmdq_probe(struct platform_device *pdev)
0514 {
0515     struct device *dev = &pdev->dev;
0516     struct cmdq *cmdq;
0517     int err, i;
0518     struct gce_plat *plat_data;
0519     struct device_node *phandle = dev->of_node;
0520     struct device_node *node;
0521     int alias_id = 0;
0522     static const char * const clk_name = "gce";
0523     static const char * const clk_names[] = { "gce0", "gce1" };
0524 
0525     cmdq = devm_kzalloc(dev, sizeof(*cmdq), GFP_KERNEL);
0526     if (!cmdq)
0527         return -ENOMEM;
0528 
0529     cmdq->base = devm_platform_ioremap_resource(pdev, 0);
0530     if (IS_ERR(cmdq->base))
0531         return PTR_ERR(cmdq->base);
0532 
0533     cmdq->irq = platform_get_irq(pdev, 0);
0534     if (cmdq->irq < 0)
0535         return cmdq->irq;
0536 
0537     plat_data = (struct gce_plat *)of_device_get_match_data(dev);
0538     if (!plat_data) {
0539         dev_err(dev, "failed to get match data\n");
0540         return -EINVAL;
0541     }
0542 
0543     cmdq->thread_nr = plat_data->thread_nr;
0544     cmdq->shift_pa = plat_data->shift;
0545     cmdq->control_by_sw = plat_data->control_by_sw;
0546     cmdq->gce_num = plat_data->gce_num;
0547     cmdq->irq_mask = GENMASK(cmdq->thread_nr - 1, 0);
0548     err = devm_request_irq(dev, cmdq->irq, cmdq_irq_handler, IRQF_SHARED,
0549                    "mtk_cmdq", cmdq);
0550     if (err < 0) {
0551         dev_err(dev, "failed to register ISR (%d)\n", err);
0552         return err;
0553     }
0554 
0555     dev_dbg(dev, "cmdq device: addr:0x%p, va:0x%p, irq:%d\n",
0556         dev, cmdq->base, cmdq->irq);
0557 
0558     if (cmdq->gce_num > 1) {
0559         for_each_child_of_node(phandle->parent, node) {
0560             alias_id = of_alias_get_id(node, clk_name);
0561             if (alias_id >= 0 && alias_id < cmdq->gce_num) {
0562                 cmdq->clocks[alias_id].id = clk_names[alias_id];
0563                 cmdq->clocks[alias_id].clk = of_clk_get(node, 0);
0564                 if (IS_ERR(cmdq->clocks[alias_id].clk)) {
0565                     of_node_put(node);
0566                     return dev_err_probe(dev,
0567                                  PTR_ERR(cmdq->clocks[alias_id].clk),
0568                                  "failed to get gce clk: %d\n",
0569                                  alias_id);
0570                 }
0571             }
0572         }
0573     } else {
0574         cmdq->clocks[alias_id].id = clk_name;
0575         cmdq->clocks[alias_id].clk = devm_clk_get(&pdev->dev, clk_name);
0576         if (IS_ERR(cmdq->clocks[alias_id].clk)) {
0577             return dev_err_probe(dev, PTR_ERR(cmdq->clocks[alias_id].clk),
0578                          "failed to get gce clk\n");
0579         }
0580     }
0581 
0582     cmdq->mbox.dev = dev;
0583     cmdq->mbox.chans = devm_kcalloc(dev, cmdq->thread_nr,
0584                     sizeof(*cmdq->mbox.chans), GFP_KERNEL);
0585     if (!cmdq->mbox.chans)
0586         return -ENOMEM;
0587 
0588     cmdq->mbox.num_chans = cmdq->thread_nr;
0589     cmdq->mbox.ops = &cmdq_mbox_chan_ops;
0590     cmdq->mbox.of_xlate = cmdq_xlate;
0591 
0592     /* make use of TXDONE_BY_ACK */
0593     cmdq->mbox.txdone_irq = false;
0594     cmdq->mbox.txdone_poll = false;
0595 
0596     cmdq->thread = devm_kcalloc(dev, cmdq->thread_nr,
0597                     sizeof(*cmdq->thread), GFP_KERNEL);
0598     if (!cmdq->thread)
0599         return -ENOMEM;
0600 
0601     for (i = 0; i < cmdq->thread_nr; i++) {
0602         cmdq->thread[i].base = cmdq->base + CMDQ_THR_BASE +
0603                 CMDQ_THR_SIZE * i;
0604         INIT_LIST_HEAD(&cmdq->thread[i].task_busy_list);
0605         cmdq->mbox.chans[i].con_priv = (void *)&cmdq->thread[i];
0606     }
0607 
0608     err = devm_mbox_controller_register(dev, &cmdq->mbox);
0609     if (err < 0) {
0610         dev_err(dev, "failed to register mailbox: %d\n", err);
0611         return err;
0612     }
0613 
0614     platform_set_drvdata(pdev, cmdq);
0615 
0616     WARN_ON(clk_bulk_prepare(cmdq->gce_num, cmdq->clocks));
0617 
0618     cmdq_init(cmdq);
0619 
0620     return 0;
0621 }
0622 
0623 static const struct dev_pm_ops cmdq_pm_ops = {
0624     .suspend = cmdq_suspend,
0625     .resume = cmdq_resume,
0626 };
0627 
0628 static const struct gce_plat gce_plat_v2 = {
0629     .thread_nr = 16,
0630     .shift = 0,
0631     .control_by_sw = false,
0632     .gce_num = 1
0633 };
0634 
0635 static const struct gce_plat gce_plat_v3 = {
0636     .thread_nr = 24,
0637     .shift = 0,
0638     .control_by_sw = false,
0639     .gce_num = 1
0640 };
0641 
0642 static const struct gce_plat gce_plat_v4 = {
0643     .thread_nr = 24,
0644     .shift = 3,
0645     .control_by_sw = false,
0646     .gce_num = 1
0647 };
0648 
0649 static const struct gce_plat gce_plat_v5 = {
0650     .thread_nr = 24,
0651     .shift = 3,
0652     .control_by_sw = true,
0653     .gce_num = 1
0654 };
0655 
0656 static const struct gce_plat gce_plat_v6 = {
0657     .thread_nr = 24,
0658     .shift = 3,
0659     .control_by_sw = true,
0660     .gce_num = 2
0661 };
0662 
0663 static const struct of_device_id cmdq_of_ids[] = {
0664     {.compatible = "mediatek,mt8173-gce", .data = (void *)&gce_plat_v2},
0665     {.compatible = "mediatek,mt8183-gce", .data = (void *)&gce_plat_v3},
0666     {.compatible = "mediatek,mt6779-gce", .data = (void *)&gce_plat_v4},
0667     {.compatible = "mediatek,mt8192-gce", .data = (void *)&gce_plat_v5},
0668     {.compatible = "mediatek,mt8195-gce", .data = (void *)&gce_plat_v6},
0669     {}
0670 };
0671 
0672 static struct platform_driver cmdq_drv = {
0673     .probe = cmdq_probe,
0674     .remove = cmdq_remove,
0675     .driver = {
0676         .name = "mtk_cmdq",
0677         .pm = &cmdq_pm_ops,
0678         .of_match_table = cmdq_of_ids,
0679     }
0680 };
0681 
0682 static int __init cmdq_drv_init(void)
0683 {
0684     return platform_driver_register(&cmdq_drv);
0685 }
0686 
0687 static void __exit cmdq_drv_exit(void)
0688 {
0689     platform_driver_unregister(&cmdq_drv);
0690 }
0691 
0692 subsys_initcall(cmdq_drv_init);
0693 module_exit(cmdq_drv_exit);
0694 
0695 MODULE_LICENSE("GPL v2");
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