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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (c) 2018 Pengutronix, Oleksij Rempel <o.rempel@pengutronix.de>
0004  * Copyright 2022 NXP, Peng Fan <peng.fan@nxp.com>
0005  */
0006 
0007 #include <linux/clk.h>
0008 #include <linux/firmware/imx/ipc.h>
0009 #include <linux/firmware/imx/s4.h>
0010 #include <linux/interrupt.h>
0011 #include <linux/io.h>
0012 #include <linux/iopoll.h>
0013 #include <linux/jiffies.h>
0014 #include <linux/kernel.h>
0015 #include <linux/mailbox_controller.h>
0016 #include <linux/module.h>
0017 #include <linux/of_device.h>
0018 #include <linux/pm_runtime.h>
0019 #include <linux/suspend.h>
0020 #include <linux/slab.h>
0021 
0022 #define IMX_MU_CHANS        17
0023 /* TX0/RX0/RXDB[0-3] */
0024 #define IMX_MU_SCU_CHANS    6
0025 /* TX0/RX0 */
0026 #define IMX_MU_S4_CHANS     2
0027 #define IMX_MU_CHAN_NAME_SIZE   20
0028 
0029 #define IMX_MU_NUM_RR       4
0030 
0031 #define IMX_MU_SECO_TX_TOUT (msecs_to_jiffies(3000))
0032 #define IMX_MU_SECO_RX_TOUT (msecs_to_jiffies(3000))
0033 
0034 /* Please not change TX & RX */
0035 enum imx_mu_chan_type {
0036     IMX_MU_TYPE_TX      = 0, /* Tx */
0037     IMX_MU_TYPE_RX      = 1, /* Rx */
0038     IMX_MU_TYPE_TXDB    = 2, /* Tx doorbell */
0039     IMX_MU_TYPE_RXDB    = 3, /* Rx doorbell */
0040     IMX_MU_TYPE_RST     = 4, /* Reset */
0041 };
0042 
0043 enum imx_mu_xcr {
0044     IMX_MU_CR,
0045     IMX_MU_GIER,
0046     IMX_MU_GCR,
0047     IMX_MU_TCR,
0048     IMX_MU_RCR,
0049     IMX_MU_xCR_MAX,
0050 };
0051 
0052 enum imx_mu_xsr {
0053     IMX_MU_SR,
0054     IMX_MU_GSR,
0055     IMX_MU_TSR,
0056     IMX_MU_RSR,
0057     IMX_MU_xSR_MAX,
0058 };
0059 
0060 struct imx_sc_rpc_msg_max {
0061     struct imx_sc_rpc_msg hdr;
0062     u32 data[30];
0063 };
0064 
0065 struct imx_s4_rpc_msg_max {
0066     struct imx_s4_rpc_msg hdr;
0067     u32 data[254];
0068 };
0069 
0070 struct imx_mu_con_priv {
0071     unsigned int        idx;
0072     char            irq_desc[IMX_MU_CHAN_NAME_SIZE];
0073     enum imx_mu_chan_type   type;
0074     struct mbox_chan    *chan;
0075     struct tasklet_struct   txdb_tasklet;
0076 };
0077 
0078 struct imx_mu_priv {
0079     struct device       *dev;
0080     void __iomem        *base;
0081     void            *msg;
0082     spinlock_t      xcr_lock; /* control register lock */
0083 
0084     struct mbox_controller  mbox;
0085     struct mbox_chan    mbox_chans[IMX_MU_CHANS];
0086 
0087     struct imx_mu_con_priv  con_priv[IMX_MU_CHANS];
0088     const struct imx_mu_dcfg    *dcfg;
0089     struct clk      *clk;
0090     int         irq[IMX_MU_CHANS];
0091     bool            suspend;
0092 
0093     u32 xcr[IMX_MU_xCR_MAX];
0094 
0095     bool            side_b;
0096 };
0097 
0098 enum imx_mu_type {
0099     IMX_MU_V1,
0100     IMX_MU_V2 = BIT(1),
0101     IMX_MU_V2_S4 = BIT(15),
0102     IMX_MU_V2_IRQ = BIT(16),
0103 };
0104 
0105 struct imx_mu_dcfg {
0106     int (*tx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, void *data);
0107     int (*rx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp);
0108     int (*rxdb)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp);
0109     void (*init)(struct imx_mu_priv *priv);
0110     enum imx_mu_type type;
0111     u32 xTR;        /* Transmit Register0 */
0112     u32 xRR;        /* Receive Register0 */
0113     u32 xSR[IMX_MU_xSR_MAX];    /* Status Registers */
0114     u32 xCR[IMX_MU_xCR_MAX];    /* Control Registers */
0115 };
0116 
0117 #define IMX_MU_xSR_GIPn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x))))
0118 #define IMX_MU_xSR_RFn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
0119 #define IMX_MU_xSR_TEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x))))
0120 
0121 /* General Purpose Interrupt Enable */
0122 #define IMX_MU_xCR_GIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x))))
0123 /* Receive Interrupt Enable */
0124 #define IMX_MU_xCR_RIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
0125 /* Transmit Interrupt Enable */
0126 #define IMX_MU_xCR_TIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x))))
0127 /* General Purpose Interrupt Request */
0128 #define IMX_MU_xCR_GIRn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(16 + (3 - (x))))
0129 /* MU reset */
0130 #define IMX_MU_xCR_RST(type)    (type & IMX_MU_V2 ? BIT(0) : BIT(5))
0131 #define IMX_MU_xSR_RST(type)    (type & IMX_MU_V2 ? BIT(0) : BIT(7))
0132 
0133 
0134 static struct imx_mu_priv *to_imx_mu_priv(struct mbox_controller *mbox)
0135 {
0136     return container_of(mbox, struct imx_mu_priv, mbox);
0137 }
0138 
0139 static void imx_mu_write(struct imx_mu_priv *priv, u32 val, u32 offs)
0140 {
0141     iowrite32(val, priv->base + offs);
0142 }
0143 
0144 static u32 imx_mu_read(struct imx_mu_priv *priv, u32 offs)
0145 {
0146     return ioread32(priv->base + offs);
0147 }
0148 
0149 static int imx_mu_tx_waiting_write(struct imx_mu_priv *priv, u32 val, u32 idx)
0150 {
0151     u64 timeout_time = get_jiffies_64() + IMX_MU_SECO_TX_TOUT;
0152     u32 status;
0153     u32 can_write;
0154 
0155     dev_dbg(priv->dev, "Trying to write %.8x to idx %d\n", val, idx);
0156 
0157     do {
0158         status = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_TSR]);
0159         can_write = status & IMX_MU_xSR_TEn(priv->dcfg->type, idx % 4);
0160     } while (!can_write && time_is_after_jiffies64(timeout_time));
0161 
0162     if (!can_write) {
0163         dev_err(priv->dev, "timeout trying to write %.8x at %d(%.8x)\n",
0164             val, idx, status);
0165         return -ETIME;
0166     }
0167 
0168     imx_mu_write(priv, val, priv->dcfg->xTR + (idx % 4) * 4);
0169 
0170     return 0;
0171 }
0172 
0173 static int imx_mu_rx_waiting_read(struct imx_mu_priv *priv, u32 *val, u32 idx)
0174 {
0175     u64 timeout_time = get_jiffies_64() + IMX_MU_SECO_RX_TOUT;
0176     u32 status;
0177     u32 can_read;
0178 
0179     dev_dbg(priv->dev, "Trying to read from idx %d\n", idx);
0180 
0181     do {
0182         status = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_RSR]);
0183         can_read = status & IMX_MU_xSR_RFn(priv->dcfg->type, idx % 4);
0184     } while (!can_read && time_is_after_jiffies64(timeout_time));
0185 
0186     if (!can_read) {
0187         dev_err(priv->dev, "timeout trying to read idx %d (%.8x)\n",
0188             idx, status);
0189         return -ETIME;
0190     }
0191 
0192     *val = imx_mu_read(priv, priv->dcfg->xRR + (idx % 4) * 4);
0193     dev_dbg(priv->dev, "Read %.8x\n", *val);
0194 
0195     return 0;
0196 }
0197 
0198 static u32 imx_mu_xcr_rmw(struct imx_mu_priv *priv, enum imx_mu_xcr type, u32 set, u32 clr)
0199 {
0200     unsigned long flags;
0201     u32 val;
0202 
0203     spin_lock_irqsave(&priv->xcr_lock, flags);
0204     val = imx_mu_read(priv, priv->dcfg->xCR[type]);
0205     val &= ~clr;
0206     val |= set;
0207     imx_mu_write(priv, val, priv->dcfg->xCR[type]);
0208     spin_unlock_irqrestore(&priv->xcr_lock, flags);
0209 
0210     return val;
0211 }
0212 
0213 static int imx_mu_generic_tx(struct imx_mu_priv *priv,
0214                  struct imx_mu_con_priv *cp,
0215                  void *data)
0216 {
0217     u32 *arg = data;
0218 
0219     switch (cp->type) {
0220     case IMX_MU_TYPE_TX:
0221         imx_mu_write(priv, *arg, priv->dcfg->xTR + cp->idx * 4);
0222         imx_mu_xcr_rmw(priv, IMX_MU_TCR, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx), 0);
0223         break;
0224     case IMX_MU_TYPE_TXDB:
0225         imx_mu_xcr_rmw(priv, IMX_MU_GCR, IMX_MU_xCR_GIRn(priv->dcfg->type, cp->idx), 0);
0226         tasklet_schedule(&cp->txdb_tasklet);
0227         break;
0228     default:
0229         dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type);
0230         return -EINVAL;
0231     }
0232 
0233     return 0;
0234 }
0235 
0236 static int imx_mu_generic_rx(struct imx_mu_priv *priv,
0237                  struct imx_mu_con_priv *cp)
0238 {
0239     u32 dat;
0240 
0241     dat = imx_mu_read(priv, priv->dcfg->xRR + (cp->idx) * 4);
0242     mbox_chan_received_data(cp->chan, (void *)&dat);
0243 
0244     return 0;
0245 }
0246 
0247 static int imx_mu_generic_rxdb(struct imx_mu_priv *priv,
0248                    struct imx_mu_con_priv *cp)
0249 {
0250     imx_mu_write(priv, IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx),
0251              priv->dcfg->xSR[IMX_MU_GSR]);
0252     mbox_chan_received_data(cp->chan, NULL);
0253 
0254     return 0;
0255 }
0256 
0257 static int imx_mu_specific_tx(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, void *data)
0258 {
0259     u32 *arg = data;
0260     int i, ret;
0261     u32 xsr;
0262     u32 size, max_size, num_tr;
0263 
0264     if (priv->dcfg->type & IMX_MU_V2_S4) {
0265         size = ((struct imx_s4_rpc_msg_max *)data)->hdr.size;
0266         max_size = sizeof(struct imx_s4_rpc_msg_max);
0267         num_tr = 8;
0268     } else {
0269         size = ((struct imx_sc_rpc_msg_max *)data)->hdr.size;
0270         max_size = sizeof(struct imx_sc_rpc_msg_max);
0271         num_tr = 4;
0272     }
0273 
0274     switch (cp->type) {
0275     case IMX_MU_TYPE_TX:
0276         /*
0277          * msg->hdr.size specifies the number of u32 words while
0278          * sizeof yields bytes.
0279          */
0280 
0281         if (size > max_size / 4) {
0282             /*
0283              * The real message size can be different to
0284              * struct imx_sc_rpc_msg_max/imx_s4_rpc_msg_max size
0285              */
0286             dev_err(priv->dev, "Maximal message size (%u bytes) exceeded on TX; got: %i bytes\n", max_size, size << 2);
0287             return -EINVAL;
0288         }
0289 
0290         for (i = 0; i < num_tr && i < size; i++)
0291             imx_mu_write(priv, *arg++, priv->dcfg->xTR + (i % num_tr) * 4);
0292         for (; i < size; i++) {
0293             ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_TSR],
0294                          xsr,
0295                          xsr & IMX_MU_xSR_TEn(priv->dcfg->type, i % num_tr),
0296                          0, 5 * USEC_PER_SEC);
0297             if (ret) {
0298                 dev_err(priv->dev, "Send data index: %d timeout\n", i);
0299                 return ret;
0300             }
0301             imx_mu_write(priv, *arg++, priv->dcfg->xTR + (i % num_tr) * 4);
0302         }
0303 
0304         imx_mu_xcr_rmw(priv, IMX_MU_TCR, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx), 0);
0305         break;
0306     default:
0307         dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type);
0308         return -EINVAL;
0309     }
0310 
0311     return 0;
0312 }
0313 
0314 static int imx_mu_specific_rx(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp)
0315 {
0316     u32 *data;
0317     int i, ret;
0318     u32 xsr;
0319     u32 size, max_size;
0320 
0321     data = (u32 *)priv->msg;
0322 
0323     imx_mu_xcr_rmw(priv, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(priv->dcfg->type, 0));
0324     *data++ = imx_mu_read(priv, priv->dcfg->xRR);
0325 
0326     if (priv->dcfg->type & IMX_MU_V2_S4) {
0327         size = ((struct imx_s4_rpc_msg_max *)priv->msg)->hdr.size;
0328         max_size = sizeof(struct imx_s4_rpc_msg_max);
0329     } else {
0330         size = ((struct imx_sc_rpc_msg_max *)priv->msg)->hdr.size;
0331         max_size = sizeof(struct imx_sc_rpc_msg_max);
0332     }
0333 
0334     if (size > max_size / 4) {
0335         dev_err(priv->dev, "Maximal message size (%u bytes) exceeded on RX; got: %i bytes\n", max_size, size << 2);
0336         return -EINVAL;
0337     }
0338 
0339     for (i = 1; i < size; i++) {
0340         ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_RSR], xsr,
0341                      xsr & IMX_MU_xSR_RFn(priv->dcfg->type, i % 4), 0,
0342                      5 * USEC_PER_SEC);
0343         if (ret) {
0344             dev_err(priv->dev, "timeout read idx %d\n", i);
0345             return ret;
0346         }
0347         *data++ = imx_mu_read(priv, priv->dcfg->xRR + (i % 4) * 4);
0348     }
0349 
0350     imx_mu_xcr_rmw(priv, IMX_MU_RCR, IMX_MU_xCR_RIEn(priv->dcfg->type, 0), 0);
0351     mbox_chan_received_data(cp->chan, (void *)priv->msg);
0352 
0353     return 0;
0354 }
0355 
0356 static int imx_mu_seco_tx(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp,
0357               void *data)
0358 {
0359     struct imx_sc_rpc_msg_max *msg = data;
0360     u32 *arg = data;
0361     u32 byte_size;
0362     int err;
0363     int i;
0364 
0365     dev_dbg(priv->dev, "Sending message\n");
0366 
0367     switch (cp->type) {
0368     case IMX_MU_TYPE_TXDB:
0369         byte_size = msg->hdr.size * sizeof(u32);
0370         if (byte_size > sizeof(*msg)) {
0371             /*
0372              * The real message size can be different to
0373              * struct imx_sc_rpc_msg_max size
0374              */
0375             dev_err(priv->dev,
0376                 "Exceed max msg size (%zu) on TX, got: %i\n",
0377                 sizeof(*msg), byte_size);
0378             return -EINVAL;
0379         }
0380 
0381         print_hex_dump_debug("from client ", DUMP_PREFIX_OFFSET, 4, 4,
0382                      data, byte_size, false);
0383 
0384         /* Send first word */
0385         dev_dbg(priv->dev, "Sending header\n");
0386         imx_mu_write(priv, *arg++, priv->dcfg->xTR);
0387 
0388         /* Send signaling */
0389         dev_dbg(priv->dev, "Sending signaling\n");
0390         imx_mu_xcr_rmw(priv, IMX_MU_GCR,
0391                    IMX_MU_xCR_GIRn(priv->dcfg->type, cp->idx), 0);
0392 
0393         /* Send words to fill the mailbox */
0394         for (i = 1; i < 4 && i < msg->hdr.size; i++) {
0395             dev_dbg(priv->dev, "Sending word %d\n", i);
0396             imx_mu_write(priv, *arg++,
0397                      priv->dcfg->xTR + (i % 4) * 4);
0398         }
0399 
0400         /* Send rest of message waiting for remote read */
0401         for (; i < msg->hdr.size; i++) {
0402             dev_dbg(priv->dev, "Sending word %d\n", i);
0403             err = imx_mu_tx_waiting_write(priv, *arg++, i);
0404             if (err) {
0405                 dev_err(priv->dev, "Timeout tx %d\n", i);
0406                 return err;
0407             }
0408         }
0409 
0410         /* Simulate hack for mbox framework */
0411         tasklet_schedule(&cp->txdb_tasklet);
0412 
0413         break;
0414     default:
0415         dev_warn_ratelimited(priv->dev,
0416                      "Send data on wrong channel type: %d\n",
0417                      cp->type);
0418         return -EINVAL;
0419     }
0420 
0421     return 0;
0422 }
0423 
0424 static int imx_mu_seco_rxdb(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp)
0425 {
0426     struct imx_sc_rpc_msg_max msg;
0427     u32 *data = (u32 *)&msg;
0428     u32 byte_size;
0429     int err = 0;
0430     int i;
0431 
0432     dev_dbg(priv->dev, "Receiving message\n");
0433 
0434     /* Read header */
0435     dev_dbg(priv->dev, "Receiving header\n");
0436     *data++ = imx_mu_read(priv, priv->dcfg->xRR);
0437     byte_size = msg.hdr.size * sizeof(u32);
0438     if (byte_size > sizeof(msg)) {
0439         dev_err(priv->dev, "Exceed max msg size (%zu) on RX, got: %i\n",
0440             sizeof(msg), byte_size);
0441         err = -EINVAL;
0442         goto error;
0443     }
0444 
0445     /* Read message waiting they are written */
0446     for (i = 1; i < msg.hdr.size; i++) {
0447         dev_dbg(priv->dev, "Receiving word %d\n", i);
0448         err = imx_mu_rx_waiting_read(priv, data++, i);
0449         if (err) {
0450             dev_err(priv->dev, "Timeout rx %d\n", i);
0451             goto error;
0452         }
0453     }
0454 
0455     /* Clear GIP */
0456     imx_mu_write(priv, IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx),
0457              priv->dcfg->xSR[IMX_MU_GSR]);
0458 
0459     print_hex_dump_debug("to client ", DUMP_PREFIX_OFFSET, 4, 4,
0460                  &msg, byte_size, false);
0461 
0462     /* send data to client */
0463     dev_dbg(priv->dev, "Sending message to client\n");
0464     mbox_chan_received_data(cp->chan, (void *)&msg);
0465 
0466     goto exit;
0467 
0468 error:
0469     mbox_chan_received_data(cp->chan, ERR_PTR(err));
0470 
0471 exit:
0472     return err;
0473 }
0474 
0475 static void imx_mu_txdb_tasklet(unsigned long data)
0476 {
0477     struct imx_mu_con_priv *cp = (struct imx_mu_con_priv *)data;
0478 
0479     mbox_chan_txdone(cp->chan, 0);
0480 }
0481 
0482 static irqreturn_t imx_mu_isr(int irq, void *p)
0483 {
0484     struct mbox_chan *chan = p;
0485     struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
0486     struct imx_mu_con_priv *cp = chan->con_priv;
0487     u32 val, ctrl;
0488 
0489     switch (cp->type) {
0490     case IMX_MU_TYPE_TX:
0491         ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_TCR]);
0492         val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_TSR]);
0493         val &= IMX_MU_xSR_TEn(priv->dcfg->type, cp->idx) &
0494             (ctrl & IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx));
0495         break;
0496     case IMX_MU_TYPE_RX:
0497         ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_RCR]);
0498         val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_RSR]);
0499         val &= IMX_MU_xSR_RFn(priv->dcfg->type, cp->idx) &
0500             (ctrl & IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx));
0501         break;
0502     case IMX_MU_TYPE_RXDB:
0503         ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_GIER]);
0504         val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_GSR]);
0505         val &= IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx) &
0506             (ctrl & IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx));
0507         break;
0508     case IMX_MU_TYPE_RST:
0509         return IRQ_NONE;
0510     default:
0511         dev_warn_ratelimited(priv->dev, "Unhandled channel type %d\n",
0512                      cp->type);
0513         return IRQ_NONE;
0514     }
0515 
0516     if (!val)
0517         return IRQ_NONE;
0518 
0519     if ((val == IMX_MU_xSR_TEn(priv->dcfg->type, cp->idx)) &&
0520         (cp->type == IMX_MU_TYPE_TX)) {
0521         imx_mu_xcr_rmw(priv, IMX_MU_TCR, 0, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx));
0522         mbox_chan_txdone(chan, 0);
0523     } else if ((val == IMX_MU_xSR_RFn(priv->dcfg->type, cp->idx)) &&
0524            (cp->type == IMX_MU_TYPE_RX)) {
0525         priv->dcfg->rx(priv, cp);
0526     } else if ((val == IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx)) &&
0527            (cp->type == IMX_MU_TYPE_RXDB)) {
0528         priv->dcfg->rxdb(priv, cp);
0529     } else {
0530         dev_warn_ratelimited(priv->dev, "Not handled interrupt\n");
0531         return IRQ_NONE;
0532     }
0533 
0534     if (priv->suspend)
0535         pm_system_wakeup();
0536 
0537     return IRQ_HANDLED;
0538 }
0539 
0540 static int imx_mu_send_data(struct mbox_chan *chan, void *data)
0541 {
0542     struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
0543     struct imx_mu_con_priv *cp = chan->con_priv;
0544 
0545     return priv->dcfg->tx(priv, cp, data);
0546 }
0547 
0548 static int imx_mu_startup(struct mbox_chan *chan)
0549 {
0550     struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
0551     struct imx_mu_con_priv *cp = chan->con_priv;
0552     unsigned long irq_flag = 0;
0553     int ret;
0554 
0555     pm_runtime_get_sync(priv->dev);
0556     if (cp->type == IMX_MU_TYPE_TXDB) {
0557         /* Tx doorbell don't have ACK support */
0558         tasklet_init(&cp->txdb_tasklet, imx_mu_txdb_tasklet,
0559                  (unsigned long)cp);
0560         return 0;
0561     }
0562 
0563     /* IPC MU should be with IRQF_NO_SUSPEND set */
0564     if (!priv->dev->pm_domain)
0565         irq_flag |= IRQF_NO_SUSPEND;
0566 
0567     if (!(priv->dcfg->type & IMX_MU_V2_IRQ))
0568         irq_flag |= IRQF_SHARED;
0569 
0570     ret = request_irq(priv->irq[cp->type], imx_mu_isr, irq_flag, cp->irq_desc, chan);
0571     if (ret) {
0572         dev_err(priv->dev, "Unable to acquire IRQ %d\n", priv->irq[cp->type]);
0573         return ret;
0574     }
0575 
0576     switch (cp->type) {
0577     case IMX_MU_TYPE_RX:
0578         imx_mu_xcr_rmw(priv, IMX_MU_RCR, IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx), 0);
0579         break;
0580     case IMX_MU_TYPE_RXDB:
0581         imx_mu_xcr_rmw(priv, IMX_MU_GIER, IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx), 0);
0582         break;
0583     default:
0584         break;
0585     }
0586 
0587     return 0;
0588 }
0589 
0590 static void imx_mu_shutdown(struct mbox_chan *chan)
0591 {
0592     struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
0593     struct imx_mu_con_priv *cp = chan->con_priv;
0594     int ret;
0595     u32 sr;
0596 
0597     if (cp->type == IMX_MU_TYPE_TXDB) {
0598         tasklet_kill(&cp->txdb_tasklet);
0599         pm_runtime_put_sync(priv->dev);
0600         return;
0601     }
0602 
0603     switch (cp->type) {
0604     case IMX_MU_TYPE_TX:
0605         imx_mu_xcr_rmw(priv, IMX_MU_TCR, 0, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx));
0606         break;
0607     case IMX_MU_TYPE_RX:
0608         imx_mu_xcr_rmw(priv, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx));
0609         break;
0610     case IMX_MU_TYPE_RXDB:
0611         imx_mu_xcr_rmw(priv, IMX_MU_GIER, 0, IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx));
0612         break;
0613     case IMX_MU_TYPE_RST:
0614         imx_mu_xcr_rmw(priv, IMX_MU_CR, IMX_MU_xCR_RST(priv->dcfg->type), 0);
0615         ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_SR], sr,
0616                      !(sr & IMX_MU_xSR_RST(priv->dcfg->type)), 1, 5);
0617         if (ret)
0618             dev_warn(priv->dev, "RST channel timeout\n");
0619         break;
0620     default:
0621         break;
0622     }
0623 
0624     free_irq(priv->irq[cp->type], chan);
0625     pm_runtime_put_sync(priv->dev);
0626 }
0627 
0628 static const struct mbox_chan_ops imx_mu_ops = {
0629     .send_data = imx_mu_send_data,
0630     .startup = imx_mu_startup,
0631     .shutdown = imx_mu_shutdown,
0632 };
0633 
0634 static struct mbox_chan *imx_mu_specific_xlate(struct mbox_controller *mbox,
0635                            const struct of_phandle_args *sp)
0636 {
0637     u32 type, idx, chan;
0638 
0639     if (sp->args_count != 2) {
0640         dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count);
0641         return ERR_PTR(-EINVAL);
0642     }
0643 
0644     type = sp->args[0]; /* channel type */
0645     idx = sp->args[1]; /* index */
0646 
0647     switch (type) {
0648     case IMX_MU_TYPE_TX:
0649     case IMX_MU_TYPE_RX:
0650         if (idx != 0)
0651             dev_err(mbox->dev, "Invalid chan idx: %d\n", idx);
0652         chan = type;
0653         break;
0654     case IMX_MU_TYPE_RXDB:
0655         chan = 2 + idx;
0656         break;
0657     default:
0658         dev_err(mbox->dev, "Invalid chan type: %d\n", type);
0659         return ERR_PTR(-EINVAL);
0660     }
0661 
0662     if (chan >= mbox->num_chans) {
0663         dev_err(mbox->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n", chan, type, idx);
0664         return ERR_PTR(-EINVAL);
0665     }
0666 
0667     return &mbox->chans[chan];
0668 }
0669 
0670 static struct mbox_chan * imx_mu_xlate(struct mbox_controller *mbox,
0671                        const struct of_phandle_args *sp)
0672 {
0673     u32 type, idx, chan;
0674 
0675     if (sp->args_count != 2) {
0676         dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count);
0677         return ERR_PTR(-EINVAL);
0678     }
0679 
0680     type = sp->args[0]; /* channel type */
0681     idx = sp->args[1]; /* index */
0682     chan = type * 4 + idx;
0683 
0684     if (chan >= mbox->num_chans) {
0685         dev_err(mbox->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n", chan, type, idx);
0686         return ERR_PTR(-EINVAL);
0687     }
0688 
0689     return &mbox->chans[chan];
0690 }
0691 
0692 static struct mbox_chan *imx_mu_seco_xlate(struct mbox_controller *mbox,
0693                        const struct of_phandle_args *sp)
0694 {
0695     u32 type;
0696 
0697     if (sp->args_count < 1) {
0698         dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count);
0699         return ERR_PTR(-EINVAL);
0700     }
0701 
0702     type = sp->args[0]; /* channel type */
0703 
0704     /* Only supports TXDB and RXDB */
0705     if (type == IMX_MU_TYPE_TX || type == IMX_MU_TYPE_RX) {
0706         dev_err(mbox->dev, "Invalid type: %d\n", type);
0707         return ERR_PTR(-EINVAL);
0708     }
0709 
0710     return imx_mu_xlate(mbox, sp);
0711 }
0712 
0713 static void imx_mu_init_generic(struct imx_mu_priv *priv)
0714 {
0715     unsigned int i;
0716     unsigned int val;
0717 
0718     for (i = 0; i < IMX_MU_CHANS; i++) {
0719         struct imx_mu_con_priv *cp = &priv->con_priv[i];
0720 
0721         cp->idx = i % 4;
0722         cp->type = i >> 2;
0723         cp->chan = &priv->mbox_chans[i];
0724         priv->mbox_chans[i].con_priv = cp;
0725         snprintf(cp->irq_desc, sizeof(cp->irq_desc),
0726              "imx_mu_chan[%i-%i]", cp->type, cp->idx);
0727     }
0728 
0729     priv->mbox.num_chans = IMX_MU_CHANS;
0730     priv->mbox.of_xlate = imx_mu_xlate;
0731 
0732     if (priv->side_b)
0733         return;
0734 
0735     /* Set default MU configuration */
0736     for (i = 0; i < IMX_MU_xCR_MAX; i++)
0737         imx_mu_write(priv, 0, priv->dcfg->xCR[i]);
0738 
0739     /* Clear any pending GIP */
0740     val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_GSR]);
0741     imx_mu_write(priv, val, priv->dcfg->xSR[IMX_MU_GSR]);
0742 
0743     /* Clear any pending RSR */
0744     for (i = 0; i < IMX_MU_NUM_RR; i++)
0745         imx_mu_read(priv, priv->dcfg->xRR + (i % 4) * 4);
0746 }
0747 
0748 static void imx_mu_init_specific(struct imx_mu_priv *priv)
0749 {
0750     unsigned int i;
0751     int num_chans = priv->dcfg->type & IMX_MU_V2_S4 ? IMX_MU_S4_CHANS : IMX_MU_SCU_CHANS;
0752 
0753     for (i = 0; i < num_chans; i++) {
0754         struct imx_mu_con_priv *cp = &priv->con_priv[i];
0755 
0756         cp->idx = i < 2 ? 0 : i - 2;
0757         cp->type = i < 2 ? i : IMX_MU_TYPE_RXDB;
0758         cp->chan = &priv->mbox_chans[i];
0759         priv->mbox_chans[i].con_priv = cp;
0760         snprintf(cp->irq_desc, sizeof(cp->irq_desc),
0761              "imx_mu_chan[%i-%i]", cp->type, cp->idx);
0762     }
0763 
0764     priv->mbox.num_chans = num_chans;
0765     priv->mbox.of_xlate = imx_mu_specific_xlate;
0766 
0767     /* Set default MU configuration */
0768     for (i = 0; i < IMX_MU_xCR_MAX; i++)
0769         imx_mu_write(priv, 0, priv->dcfg->xCR[i]);
0770 }
0771 
0772 static void imx_mu_init_seco(struct imx_mu_priv *priv)
0773 {
0774     imx_mu_init_generic(priv);
0775     priv->mbox.of_xlate = imx_mu_seco_xlate;
0776 }
0777 
0778 static int imx_mu_probe(struct platform_device *pdev)
0779 {
0780     struct device *dev = &pdev->dev;
0781     struct device_node *np = dev->of_node;
0782     struct imx_mu_priv *priv;
0783     const struct imx_mu_dcfg *dcfg;
0784     int i, ret;
0785     u32 size;
0786 
0787     priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
0788     if (!priv)
0789         return -ENOMEM;
0790 
0791     priv->dev = dev;
0792 
0793     priv->base = devm_platform_ioremap_resource(pdev, 0);
0794     if (IS_ERR(priv->base))
0795         return PTR_ERR(priv->base);
0796 
0797     dcfg = of_device_get_match_data(dev);
0798     if (!dcfg)
0799         return -EINVAL;
0800     priv->dcfg = dcfg;
0801     if (priv->dcfg->type & IMX_MU_V2_IRQ) {
0802         priv->irq[IMX_MU_TYPE_TX] = platform_get_irq_byname(pdev, "tx");
0803         if (priv->irq[IMX_MU_TYPE_TX] < 0)
0804             return priv->irq[IMX_MU_TYPE_TX];
0805         priv->irq[IMX_MU_TYPE_RX] = platform_get_irq_byname(pdev, "rx");
0806         if (priv->irq[IMX_MU_TYPE_RX] < 0)
0807             return priv->irq[IMX_MU_TYPE_RX];
0808     } else {
0809         ret = platform_get_irq(pdev, 0);
0810         if (ret < 0)
0811             return ret;
0812 
0813         for (i = 0; i < IMX_MU_CHANS; i++)
0814             priv->irq[i] = ret;
0815     }
0816 
0817     if (priv->dcfg->type & IMX_MU_V2_S4)
0818         size = sizeof(struct imx_s4_rpc_msg_max);
0819     else
0820         size = sizeof(struct imx_sc_rpc_msg_max);
0821 
0822     priv->msg = devm_kzalloc(dev, size, GFP_KERNEL);
0823     if (!priv->msg)
0824         return -ENOMEM;
0825 
0826     priv->clk = devm_clk_get(dev, NULL);
0827     if (IS_ERR(priv->clk)) {
0828         if (PTR_ERR(priv->clk) != -ENOENT)
0829             return PTR_ERR(priv->clk);
0830 
0831         priv->clk = NULL;
0832     }
0833 
0834     ret = clk_prepare_enable(priv->clk);
0835     if (ret) {
0836         dev_err(dev, "Failed to enable clock\n");
0837         return ret;
0838     }
0839 
0840     priv->side_b = of_property_read_bool(np, "fsl,mu-side-b");
0841 
0842     priv->dcfg->init(priv);
0843 
0844     spin_lock_init(&priv->xcr_lock);
0845 
0846     priv->mbox.dev = dev;
0847     priv->mbox.ops = &imx_mu_ops;
0848     priv->mbox.chans = priv->mbox_chans;
0849     priv->mbox.txdone_irq = true;
0850 
0851     platform_set_drvdata(pdev, priv);
0852 
0853     ret = devm_mbox_controller_register(dev, &priv->mbox);
0854     if (ret) {
0855         clk_disable_unprepare(priv->clk);
0856         return ret;
0857     }
0858 
0859     pm_runtime_enable(dev);
0860 
0861     ret = pm_runtime_resume_and_get(dev);
0862     if (ret < 0)
0863         goto disable_runtime_pm;
0864 
0865     ret = pm_runtime_put_sync(dev);
0866     if (ret < 0)
0867         goto disable_runtime_pm;
0868 
0869     clk_disable_unprepare(priv->clk);
0870 
0871     return 0;
0872 
0873 disable_runtime_pm:
0874     pm_runtime_disable(dev);
0875     clk_disable_unprepare(priv->clk);
0876     return ret;
0877 }
0878 
0879 static int imx_mu_remove(struct platform_device *pdev)
0880 {
0881     struct imx_mu_priv *priv = platform_get_drvdata(pdev);
0882 
0883     pm_runtime_disable(priv->dev);
0884 
0885     return 0;
0886 }
0887 
0888 static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = {
0889     .tx = imx_mu_generic_tx,
0890     .rx = imx_mu_generic_rx,
0891     .rxdb   = imx_mu_generic_rxdb,
0892     .init   = imx_mu_init_generic,
0893     .xTR    = 0x0,
0894     .xRR    = 0x10,
0895     .xSR    = {0x20, 0x20, 0x20, 0x20},
0896     .xCR    = {0x24, 0x24, 0x24, 0x24, 0x24},
0897 };
0898 
0899 static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = {
0900     .tx = imx_mu_generic_tx,
0901     .rx = imx_mu_generic_rx,
0902     .rxdb   = imx_mu_generic_rxdb,
0903     .init   = imx_mu_init_generic,
0904     .xTR    = 0x20,
0905     .xRR    = 0x40,
0906     .xSR    = {0x60, 0x60, 0x60, 0x60},
0907     .xCR    = {0x64, 0x64, 0x64, 0x64},
0908 };
0909 
0910 static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp = {
0911     .tx = imx_mu_generic_tx,
0912     .rx = imx_mu_generic_rx,
0913     .rxdb   = imx_mu_generic_rxdb,
0914     .init   = imx_mu_init_generic,
0915     .type   = IMX_MU_V2,
0916     .xTR    = 0x200,
0917     .xRR    = 0x280,
0918     .xSR    = {0xC, 0x118, 0x124, 0x12C},
0919     .xCR    = {0x8, 0x110, 0x114, 0x120, 0x128},
0920 };
0921 
0922 static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp_s4 = {
0923     .tx = imx_mu_specific_tx,
0924     .rx = imx_mu_specific_rx,
0925     .init   = imx_mu_init_specific,
0926     .type   = IMX_MU_V2 | IMX_MU_V2_S4,
0927     .xTR    = 0x200,
0928     .xRR    = 0x280,
0929     .xSR    = {0xC, 0x118, 0x124, 0x12C},
0930     .xCR    = {0x110, 0x114, 0x120, 0x128},
0931 };
0932 
0933 static const struct imx_mu_dcfg imx_mu_cfg_imx93_s4 = {
0934     .tx = imx_mu_specific_tx,
0935     .rx = imx_mu_specific_rx,
0936     .init   = imx_mu_init_specific,
0937     .type   = IMX_MU_V2 | IMX_MU_V2_S4 | IMX_MU_V2_IRQ,
0938     .xTR    = 0x200,
0939     .xRR    = 0x280,
0940     .xSR    = {0xC, 0x118, 0x124, 0x12C},
0941     .xCR    = {0x110, 0x114, 0x120, 0x128},
0942 };
0943 
0944 static const struct imx_mu_dcfg imx_mu_cfg_imx8_scu = {
0945     .tx = imx_mu_specific_tx,
0946     .rx = imx_mu_specific_rx,
0947     .init   = imx_mu_init_specific,
0948     .rxdb   = imx_mu_generic_rxdb,
0949     .xTR    = 0x0,
0950     .xRR    = 0x10,
0951     .xSR    = {0x20, 0x20, 0x20, 0x20},
0952     .xCR    = {0x24, 0x24, 0x24, 0x24},
0953 };
0954 
0955 static const struct imx_mu_dcfg imx_mu_cfg_imx8_seco = {
0956     .tx = imx_mu_seco_tx,
0957     .rx = imx_mu_generic_rx,
0958     .rxdb   = imx_mu_seco_rxdb,
0959     .init   = imx_mu_init_seco,
0960     .xTR    = 0x0,
0961     .xRR    = 0x10,
0962     .xSR    = {0x20, 0x20, 0x20, 0x20},
0963     .xCR    = {0x24, 0x24, 0x24, 0x24},
0964 };
0965 
0966 static const struct of_device_id imx_mu_dt_ids[] = {
0967     { .compatible = "fsl,imx7ulp-mu", .data = &imx_mu_cfg_imx7ulp },
0968     { .compatible = "fsl,imx6sx-mu", .data = &imx_mu_cfg_imx6sx },
0969     { .compatible = "fsl,imx8ulp-mu", .data = &imx_mu_cfg_imx8ulp },
0970     { .compatible = "fsl,imx8ulp-mu-s4", .data = &imx_mu_cfg_imx8ulp_s4 },
0971     { .compatible = "fsl,imx93-mu-s4", .data = &imx_mu_cfg_imx93_s4 },
0972     { .compatible = "fsl,imx8-mu-scu", .data = &imx_mu_cfg_imx8_scu },
0973     { .compatible = "fsl,imx8-mu-seco", .data = &imx_mu_cfg_imx8_seco },
0974     { },
0975 };
0976 MODULE_DEVICE_TABLE(of, imx_mu_dt_ids);
0977 
0978 static int __maybe_unused imx_mu_suspend_noirq(struct device *dev)
0979 {
0980     struct imx_mu_priv *priv = dev_get_drvdata(dev);
0981     int i;
0982 
0983     if (!priv->clk) {
0984         for (i = 0; i < IMX_MU_xCR_MAX; i++)
0985             priv->xcr[i] = imx_mu_read(priv, priv->dcfg->xCR[i]);
0986     }
0987 
0988     priv->suspend = true;
0989 
0990     return 0;
0991 }
0992 
0993 static int __maybe_unused imx_mu_resume_noirq(struct device *dev)
0994 {
0995     struct imx_mu_priv *priv = dev_get_drvdata(dev);
0996     int i;
0997 
0998     /*
0999      * ONLY restore MU when context lost, the TIE could
1000      * be set during noirq resume as there is MU data
1001      * communication going on, and restore the saved
1002      * value will overwrite the TIE and cause MU data
1003      * send failed, may lead to system freeze. This issue
1004      * is observed by testing freeze mode suspend.
1005      */
1006     if (!priv->clk && !imx_mu_read(priv, priv->dcfg->xCR[0])) {
1007         for (i = 0; i < IMX_MU_xCR_MAX; i++)
1008             imx_mu_write(priv, priv->xcr[i], priv->dcfg->xCR[i]);
1009     }
1010 
1011     priv->suspend = false;
1012 
1013     return 0;
1014 }
1015 
1016 static int __maybe_unused imx_mu_runtime_suspend(struct device *dev)
1017 {
1018     struct imx_mu_priv *priv = dev_get_drvdata(dev);
1019 
1020     clk_disable_unprepare(priv->clk);
1021 
1022     return 0;
1023 }
1024 
1025 static int __maybe_unused imx_mu_runtime_resume(struct device *dev)
1026 {
1027     struct imx_mu_priv *priv = dev_get_drvdata(dev);
1028     int ret;
1029 
1030     ret = clk_prepare_enable(priv->clk);
1031     if (ret)
1032         dev_err(dev, "failed to enable clock\n");
1033 
1034     return ret;
1035 }
1036 
1037 static const struct dev_pm_ops imx_mu_pm_ops = {
1038     SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(imx_mu_suspend_noirq,
1039                       imx_mu_resume_noirq)
1040     SET_RUNTIME_PM_OPS(imx_mu_runtime_suspend,
1041                imx_mu_runtime_resume, NULL)
1042 };
1043 
1044 static struct platform_driver imx_mu_driver = {
1045     .probe      = imx_mu_probe,
1046     .remove     = imx_mu_remove,
1047     .driver = {
1048         .name   = "imx_mu",
1049         .of_match_table = imx_mu_dt_ids,
1050         .pm = &imx_mu_pm_ops,
1051     },
1052 };
1053 module_platform_driver(imx_mu_driver);
1054 
1055 MODULE_AUTHOR("Oleksij Rempel <o.rempel@pengutronix.de>");
1056 MODULE_DESCRIPTION("Message Unit driver for i.MX");
1057 MODULE_LICENSE("GPL v2");
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