drivers/mailbox/armada-37xx-rwtm-mailbox.c

0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * rWTM BIU Mailbox driver for Armada 37xx
0004  *
0005  * Author: Marek Behún <kabel@kernel.org>
0006  */
0007
0008 #include <linux/device.h>
0009 #include <linux/interrupt.h>
0010 #include <linux/io.h>
0011 #include <linux/kernel.h>
0012 #include <linux/mailbox_controller.h>
0013 #include <linux/module.h>
0014 #include <linux/of.h>
0015 #include <linux/platform_device.h>
0016 #include <linux/armada-37xx-rwtm-mailbox.h>
0017
0018 #define DRIVER_NAME "armada-37xx-rwtm-mailbox"
0019
0020 /* relative to rWTM BIU Mailbox Registers */
0021 #define RWTM_MBOX_PARAM(i)      (0x0 + ((i) << 2))
0022 #define RWTM_MBOX_COMMAND       0x40
0023 #define RWTM_MBOX_RETURN_STATUS     0x80
0024 #define RWTM_MBOX_STATUS(i)     (0x84 + ((i) << 2))
0025 #define RWTM_MBOX_FIFO_STATUS       0xc4
0026 #define FIFO_STS_RDY            0x100
0027 #define FIFO_STS_CNTR_MASK      0x7
0028 #define FIFO_STS_CNTR_MAX       4
0029
0030 #define RWTM_HOST_INT_RESET     0xc8
0031 #define RWTM_HOST_INT_MASK      0xcc
0032 #define SP_CMD_COMPLETE         BIT(0)
0033 #define SP_CMD_QUEUE_FULL_ACCESS    BIT(17)
0034 #define SP_CMD_QUEUE_FULL       BIT(18)
0035
0036 struct a37xx_mbox {
0037     struct device *dev;
0038     struct mbox_controller controller;
0039     void __iomem *base;
0040     int irq;
0041 };
0042
0043 static void a37xx_mbox_receive(struct mbox_chan *chan)
0044 {
0045     struct a37xx_mbox *mbox = chan->con_priv;
0046     struct armada_37xx_rwtm_rx_msg rx_msg;
0047     int i;
0048
0049     rx_msg.retval = readl(mbox->base + RWTM_MBOX_RETURN_STATUS);
0050     for (i = 0; i < 16; ++i)
0051         rx_msg.status[i] = readl(mbox->base + RWTM_MBOX_STATUS(i));
0052
0053     mbox_chan_received_data(chan, &rx_msg);
0054 }
0055
0056 static irqreturn_t a37xx_mbox_irq_handler(int irq, void *data)
0057 {
0058     struct mbox_chan *chan = data;
0059     struct a37xx_mbox *mbox = chan->con_priv;
0060     u32 reg;
0061
0062     reg = readl(mbox->base + RWTM_HOST_INT_RESET);
0063
0064     if (reg & SP_CMD_COMPLETE)
0065         a37xx_mbox_receive(chan);
0066
0067     if (reg & (SP_CMD_QUEUE_FULL_ACCESS | SP_CMD_QUEUE_FULL))
0068         dev_err(mbox->dev, "Secure processor command queue full\n");
0069
0070     writel(reg, mbox->base + RWTM_HOST_INT_RESET);
0071     if (reg)
0072         mbox_chan_txdone(chan, 0);
0073
0074     return reg ? IRQ_HANDLED : IRQ_NONE;
0075 }
0076
0077 static int a37xx_mbox_send_data(struct mbox_chan *chan, void *data)
0078 {
0079     struct a37xx_mbox *mbox = chan->con_priv;
0080     struct armada_37xx_rwtm_tx_msg *msg = data;
0081     int i;
0082     u32 reg;
0083
0084     if (!data)
0085         return -EINVAL;
0086
0087     reg = readl(mbox->base + RWTM_MBOX_FIFO_STATUS);
0088     if (!(reg & FIFO_STS_RDY))
0089         dev_warn(mbox->dev, "Secure processor not ready\n");
0090
0091     if ((reg & FIFO_STS_CNTR_MASK) >= FIFO_STS_CNTR_MAX) {
0092         dev_err(mbox->dev, "Secure processor command queue full\n");
0093         return -EBUSY;
0094     }
0095
0096     for (i = 0; i < 16; ++i)
0097         writel(msg->args[i], mbox->base + RWTM_MBOX_PARAM(i));
0098     writel(msg->command, mbox->base + RWTM_MBOX_COMMAND);
0099
0100     return 0;
0101 }
0102
0103 static int a37xx_mbox_startup(struct mbox_chan *chan)
0104 {
0105     struct a37xx_mbox *mbox = chan->con_priv;
0106     u32 reg;
0107     int ret;
0108
0109     ret = devm_request_irq(mbox->dev, mbox->irq, a37xx_mbox_irq_handler, 0,
0110                    DRIVER_NAME, chan);
0111     if (ret < 0) {
0112         dev_err(mbox->dev, "Cannot request irq\n");
0113         return ret;
0114     }
0115
0116     /* enable IRQ generation */
0117     reg = readl(mbox->base + RWTM_HOST_INT_MASK);
0118     reg &= ~(SP_CMD_COMPLETE | SP_CMD_QUEUE_FULL_ACCESS | SP_CMD_QUEUE_FULL);
0119     writel(reg, mbox->base + RWTM_HOST_INT_MASK);
0120
0121     return 0;
0122 }
0123
0124 static void a37xx_mbox_shutdown(struct mbox_chan *chan)
0125 {
0126     u32 reg;
0127     struct a37xx_mbox *mbox = chan->con_priv;
0128
0129     /* disable interrupt generation */
0130     reg = readl(mbox->base + RWTM_HOST_INT_MASK);
0131     reg |= SP_CMD_COMPLETE | SP_CMD_QUEUE_FULL_ACCESS | SP_CMD_QUEUE_FULL;
0132     writel(reg, mbox->base + RWTM_HOST_INT_MASK);
0133
0134     devm_free_irq(mbox->dev, mbox->irq, chan);
0135 }
0136
0137 static const struct mbox_chan_ops a37xx_mbox_ops = {
0138     .send_data  = a37xx_mbox_send_data,
0139     .startup    = a37xx_mbox_startup,
0140     .shutdown   = a37xx_mbox_shutdown,
0141 };
0142
0143 static int armada_37xx_mbox_probe(struct platform_device *pdev)
0144 {
0145     struct a37xx_mbox *mbox;
0146     struct mbox_chan *chans;
0147     int ret;
0148
0149     mbox = devm_kzalloc(&pdev->dev, sizeof(*mbox), GFP_KERNEL);
0150     if (!mbox)
0151         return -ENOMEM;
0152
0153     /* Allocated one channel */
0154     chans = devm_kzalloc(&pdev->dev, sizeof(*chans), GFP_KERNEL);
0155     if (!chans)
0156         return -ENOMEM;
0157
0158     mbox->base = devm_platform_ioremap_resource(pdev, 0);
0159     if (IS_ERR(mbox->base))
0160         return PTR_ERR(mbox->base);
0161
0162     mbox->irq = platform_get_irq(pdev, 0);
0163     if (mbox->irq < 0)
0164         return mbox->irq;
0165
0166     mbox->dev = &pdev->dev;
0167
0168     /* Hardware supports only one channel. */
0169     chans[0].con_priv = mbox;
0170     mbox->controller.dev = mbox->dev;
0171     mbox->controller.num_chans = 1;
0172     mbox->controller.chans = chans;
0173     mbox->controller.ops = &a37xx_mbox_ops;
0174     mbox->controller.txdone_irq = true;
0175
0176     ret = devm_mbox_controller_register(mbox->dev, &mbox->controller);
0177     if (ret) {
0178         dev_err(&pdev->dev, "Could not register mailbox controller\n");
0179         return ret;
0180     }
0181
0182     platform_set_drvdata(pdev, mbox);
0183     return ret;
0184 }
0185
0186
0187 static const struct of_device_id armada_37xx_mbox_match[] = {
0188     { .compatible = "marvell,armada-3700-rwtm-mailbox" },
0189     { },
0190 };
0191
0192 MODULE_DEVICE_TABLE(of, armada_37xx_mbox_match);
0193
0194 static struct platform_driver armada_37xx_mbox_driver = {
0195     .probe  = armada_37xx_mbox_probe,
0196     .driver = {
0197         .name       = DRIVER_NAME,
0198         .of_match_table = armada_37xx_mbox_match,
0199     },
0200 };
0201
0202 module_platform_driver(armada_37xx_mbox_driver);
0203
0204 MODULE_LICENSE("GPL v2");
0205 MODULE_DESCRIPTION("rWTM BIU Mailbox driver for Armada 37xx");
0206 MODULE_AUTHOR("Marek Behun <kabel@kernel.org>");