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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * ARM Message Handling Unit Version 2 (MHUv2) driver.
0004  *
0005  * Copyright (C) 2020 ARM Ltd.
0006  * Copyright (C) 2020 Linaro Ltd.
0007  *
0008  * An MHUv2 mailbox controller can provide up to 124 channel windows (each 32
0009  * bit long) and the driver allows any combination of both the transport
0010  * protocol modes: data-transfer and doorbell, to be used on those channel
0011  * windows.
0012  *
0013  * The transport protocols should be specified in the device tree entry for the
0014  * device. The transport protocols determine how the underlying hardware
0015  * resources of the device are utilized when transmitting data. Refer to the
0016  * device tree bindings of the ARM MHUv2 controller for more details.
0017  *
0018  * The number of registered mailbox channels is dependent on both the underlying
0019  * hardware - mainly the number of channel windows implemented by the platform,
0020  * as well as the selected transport protocols.
0021  *
0022  * The MHUv2 controller can work both as a sender and receiver, but the driver
0023  * and the DT bindings support unidirectional transfers for better allocation of
0024  * the channels. That is, this driver will be probed for two separate devices
0025  * for each mailbox controller, a sender device and a receiver device.
0026  */
0027 
0028 #include <linux/amba/bus.h>
0029 #include <linux/interrupt.h>
0030 #include <linux/mailbox_controller.h>
0031 #include <linux/mailbox/arm_mhuv2_message.h>
0032 #include <linux/module.h>
0033 #include <linux/of_address.h>
0034 #include <linux/spinlock.h>
0035 
0036 /* ====== MHUv2 Registers ====== */
0037 
0038 /* Maximum number of channel windows */
0039 #define MHUV2_CH_WN_MAX         124
0040 /* Number of combined interrupt status registers */
0041 #define MHUV2_CMB_INT_ST_REG_CNT    4
0042 #define MHUV2_STAT_BYTES        (sizeof(u32))
0043 #define MHUV2_STAT_BITS         (MHUV2_STAT_BYTES * __CHAR_BIT__)
0044 
0045 #define LSB_MASK(n)         ((1 << (n * __CHAR_BIT__)) - 1)
0046 #define MHUV2_PROTOCOL_PROP     "arm,mhuv2-protocols"
0047 
0048 /* Register Message Handling Unit Configuration fields */
0049 struct mhu_cfg_t {
0050     u32 num_ch : 7;
0051     u32 pad : 25;
0052 } __packed;
0053 
0054 /* register Interrupt Status fields */
0055 struct int_st_t {
0056     u32 nr2r : 1;
0057     u32 r2nr : 1;
0058     u32 pad : 30;
0059 } __packed;
0060 
0061 /* Register Interrupt Clear fields */
0062 struct int_clr_t {
0063     u32 nr2r : 1;
0064     u32 r2nr : 1;
0065     u32 pad : 30;
0066 } __packed;
0067 
0068 /* Register Interrupt Enable fields */
0069 struct int_en_t {
0070     u32 r2nr : 1;
0071     u32 nr2r : 1;
0072     u32 chcomb : 1;
0073     u32 pad : 29;
0074 } __packed;
0075 
0076 /* Register Implementer Identification fields */
0077 struct iidr_t {
0078     u32 implementer : 12;
0079     u32 revision : 4;
0080     u32 variant : 4;
0081     u32 product_id : 12;
0082 } __packed;
0083 
0084 /* Register Architecture Identification Register fields */
0085 struct aidr_t {
0086     u32 arch_minor_rev : 4;
0087     u32 arch_major_rev : 4;
0088     u32 pad : 24;
0089 } __packed;
0090 
0091 /* Sender Channel Window fields */
0092 struct mhu2_send_ch_wn_reg {
0093     u32 stat;
0094     u8 pad1[0x0C - 0x04];
0095     u32 stat_set;
0096     u32 int_st;
0097     u32 int_clr;
0098     u32 int_en;
0099     u8 pad2[0x20 - 0x1C];
0100 } __packed;
0101 
0102 /* Sender frame register fields */
0103 struct mhu2_send_frame_reg {
0104     struct mhu2_send_ch_wn_reg ch_wn[MHUV2_CH_WN_MAX];
0105     struct mhu_cfg_t mhu_cfg;
0106     u32 resp_cfg;
0107     u32 access_request;
0108     u32 access_ready;
0109     struct int_st_t int_st;
0110     struct int_clr_t int_clr;
0111     struct int_en_t int_en;
0112     u32 reserved0;
0113     u32 chcomb_int_st[MHUV2_CMB_INT_ST_REG_CNT];
0114     u8 pad[0xFC8 - 0xFB0];
0115     struct iidr_t iidr;
0116     struct aidr_t aidr;
0117 } __packed;
0118 
0119 /* Receiver Channel Window fields */
0120 struct mhu2_recv_ch_wn_reg {
0121     u32 stat;
0122     u32 stat_masked;
0123     u32 stat_clear;
0124     u8 reserved0[0x10 - 0x0C];
0125     u32 mask;
0126     u32 mask_set;
0127     u32 mask_clear;
0128     u8 pad[0x20 - 0x1C];
0129 } __packed;
0130 
0131 /* Receiver frame register fields */
0132 struct mhu2_recv_frame_reg {
0133     struct mhu2_recv_ch_wn_reg ch_wn[MHUV2_CH_WN_MAX];
0134     struct mhu_cfg_t mhu_cfg;
0135     u8 reserved0[0xF90 - 0xF84];
0136     struct int_st_t int_st;
0137     struct int_clr_t int_clr;
0138     struct int_en_t int_en;
0139     u32 pad;
0140     u32 chcomb_int_st[MHUV2_CMB_INT_ST_REG_CNT];
0141     u8 reserved2[0xFC8 - 0xFB0];
0142     struct iidr_t iidr;
0143     struct aidr_t aidr;
0144 } __packed;
0145 
0146 
0147 /* ====== MHUv2 data structures ====== */
0148 
0149 enum mhuv2_transport_protocol {
0150     DOORBELL = 0,
0151     DATA_TRANSFER = 1
0152 };
0153 
0154 enum mhuv2_frame {
0155     RECEIVER_FRAME,
0156     SENDER_FRAME
0157 };
0158 
0159 /**
0160  * struct mhuv2 - MHUv2 mailbox controller data
0161  *
0162  * @mbox:   Mailbox controller belonging to the MHU frame.
0163  * @send:   Base address of the register mapping region.
0164  * @recv:   Base address of the register mapping region.
0165  * @frame:  Frame type: RECEIVER_FRAME or SENDER_FRAME.
0166  * @irq:    Interrupt.
0167  * @windows:    Channel windows implemented by the platform.
0168  * @minor:  Minor version of the controller.
0169  * @length: Length of the protocols array in bytes.
0170  * @protocols:  Raw protocol information, derived from device tree.
0171  * @doorbell_pending_lock: spinlock required for correct operation of Tx
0172  *      interrupt for doorbells.
0173  */
0174 struct mhuv2 {
0175     struct mbox_controller mbox;
0176     union {
0177         struct mhu2_send_frame_reg __iomem *send;
0178         struct mhu2_recv_frame_reg __iomem *recv;
0179     };
0180     enum mhuv2_frame frame;
0181     unsigned int irq;
0182     unsigned int windows;
0183     unsigned int minor;
0184     unsigned int length;
0185     u32 *protocols;
0186 
0187     spinlock_t doorbell_pending_lock;
0188 };
0189 
0190 #define mhu_from_mbox(_mbox) container_of(_mbox, struct mhuv2, mbox)
0191 
0192 /**
0193  * struct mhuv2_protocol_ops - MHUv2 operations
0194  *
0195  * Each transport protocol must provide an implementation of the operations
0196  * provided here.
0197  *
0198  * @rx_startup: Startup callback for receiver.
0199  * @rx_shutdown: Shutdown callback for receiver.
0200  * @read_data: Reads and clears newly available data.
0201  * @tx_startup: Startup callback for receiver.
0202  * @tx_shutdown: Shutdown callback for receiver.
0203  * @last_tx_done: Report back if the last tx is completed or not.
0204  * @send_data: Send data to the receiver.
0205  */
0206 struct mhuv2_protocol_ops {
0207     int (*rx_startup)(struct mhuv2 *mhu, struct mbox_chan *chan);
0208     void (*rx_shutdown)(struct mhuv2 *mhu, struct mbox_chan *chan);
0209     void *(*read_data)(struct mhuv2 *mhu, struct mbox_chan *chan);
0210 
0211     void (*tx_startup)(struct mhuv2 *mhu, struct mbox_chan *chan);
0212     void (*tx_shutdown)(struct mhuv2 *mhu, struct mbox_chan *chan);
0213     int (*last_tx_done)(struct mhuv2 *mhu, struct mbox_chan *chan);
0214     int (*send_data)(struct mhuv2 *mhu, struct mbox_chan *chan, void *arg);
0215 };
0216 
0217 /*
0218  * MHUv2 mailbox channel's private information
0219  *
0220  * @ops:    protocol specific ops for the channel.
0221  * @ch_wn_idx:  Channel window index allocated to the channel.
0222  * @windows:    Total number of windows consumed by the channel, only relevant
0223  *      in DATA_TRANSFER protocol.
0224  * @doorbell:   Doorbell bit number within the ch_wn_idx window, only relevant
0225  *      in DOORBELL protocol.
0226  * @pending:    Flag indicating pending doorbell interrupt, only relevant in
0227  *      DOORBELL protocol.
0228  */
0229 struct mhuv2_mbox_chan_priv {
0230     const struct mhuv2_protocol_ops *ops;
0231     u32 ch_wn_idx;
0232     union {
0233         u32 windows;
0234         struct {
0235             u32 doorbell;
0236             u32 pending;
0237         };
0238     };
0239 };
0240 
0241 /* Macro for reading a bitfield within a physically mapped packed struct */
0242 #define readl_relaxed_bitfield(_regptr, _type, _field)          \
0243     ({                              \
0244         u32 _regval;                        \
0245         _regval = readl_relaxed((_regptr));         \
0246         (*(_type *)(&_regval))._field;              \
0247     })
0248 
0249 /* Macro for writing a bitfield within a physically mapped packed struct */
0250 #define writel_relaxed_bitfield(_value, _regptr, _type, _field)     \
0251     ({                              \
0252         u32 _regval;                        \
0253         _regval = readl_relaxed(_regptr);           \
0254         (*(_type *)(&_regval))._field = _value;         \
0255         writel_relaxed(_regval, _regptr);           \
0256     })
0257 
0258 
0259 /* =================== Doorbell transport protocol operations =============== */
0260 
0261 static int mhuv2_doorbell_rx_startup(struct mhuv2 *mhu, struct mbox_chan *chan)
0262 {
0263     struct mhuv2_mbox_chan_priv *priv = chan->con_priv;
0264 
0265     writel_relaxed(BIT(priv->doorbell),
0266                &mhu->recv->ch_wn[priv->ch_wn_idx].mask_clear);
0267     return 0;
0268 }
0269 
0270 static void mhuv2_doorbell_rx_shutdown(struct mhuv2 *mhu,
0271                        struct mbox_chan *chan)
0272 {
0273     struct mhuv2_mbox_chan_priv *priv = chan->con_priv;
0274 
0275     writel_relaxed(BIT(priv->doorbell),
0276                &mhu->recv->ch_wn[priv->ch_wn_idx].mask_set);
0277 }
0278 
0279 static void *mhuv2_doorbell_read_data(struct mhuv2 *mhu, struct mbox_chan *chan)
0280 {
0281     struct mhuv2_mbox_chan_priv *priv = chan->con_priv;
0282 
0283     writel_relaxed(BIT(priv->doorbell),
0284                &mhu->recv->ch_wn[priv->ch_wn_idx].stat_clear);
0285     return NULL;
0286 }
0287 
0288 static int mhuv2_doorbell_last_tx_done(struct mhuv2 *mhu,
0289                        struct mbox_chan *chan)
0290 {
0291     struct mhuv2_mbox_chan_priv *priv = chan->con_priv;
0292 
0293     return !(readl_relaxed(&mhu->send->ch_wn[priv->ch_wn_idx].stat) &
0294          BIT(priv->doorbell));
0295 }
0296 
0297 static int mhuv2_doorbell_send_data(struct mhuv2 *mhu, struct mbox_chan *chan,
0298                     void *arg)
0299 {
0300     struct mhuv2_mbox_chan_priv *priv = chan->con_priv;
0301     unsigned long flags;
0302 
0303     spin_lock_irqsave(&mhu->doorbell_pending_lock, flags);
0304 
0305     priv->pending = 1;
0306     writel_relaxed(BIT(priv->doorbell),
0307                &mhu->send->ch_wn[priv->ch_wn_idx].stat_set);
0308 
0309     spin_unlock_irqrestore(&mhu->doorbell_pending_lock, flags);
0310 
0311     return 0;
0312 }
0313 
0314 static const struct mhuv2_protocol_ops mhuv2_doorbell_ops = {
0315     .rx_startup = mhuv2_doorbell_rx_startup,
0316     .rx_shutdown = mhuv2_doorbell_rx_shutdown,
0317     .read_data = mhuv2_doorbell_read_data,
0318     .last_tx_done = mhuv2_doorbell_last_tx_done,
0319     .send_data = mhuv2_doorbell_send_data,
0320 };
0321 #define IS_PROTOCOL_DOORBELL(_priv) (_priv->ops == &mhuv2_doorbell_ops)
0322 
0323 /* ============= Data transfer transport protocol operations ================ */
0324 
0325 static int mhuv2_data_transfer_rx_startup(struct mhuv2 *mhu,
0326                       struct mbox_chan *chan)
0327 {
0328     struct mhuv2_mbox_chan_priv *priv = chan->con_priv;
0329     int i = priv->ch_wn_idx + priv->windows - 1;
0330 
0331     /*
0332      * The protocol mandates that all but the last status register must be
0333      * masked.
0334      */
0335     writel_relaxed(0xFFFFFFFF, &mhu->recv->ch_wn[i].mask_clear);
0336     return 0;
0337 }
0338 
0339 static void mhuv2_data_transfer_rx_shutdown(struct mhuv2 *mhu,
0340                         struct mbox_chan *chan)
0341 {
0342     struct mhuv2_mbox_chan_priv *priv = chan->con_priv;
0343     int i = priv->ch_wn_idx + priv->windows - 1;
0344 
0345     writel_relaxed(0xFFFFFFFF, &mhu->recv->ch_wn[i].mask_set);
0346 }
0347 
0348 static void *mhuv2_data_transfer_read_data(struct mhuv2 *mhu,
0349                        struct mbox_chan *chan)
0350 {
0351     struct mhuv2_mbox_chan_priv *priv = chan->con_priv;
0352     const int windows = priv->windows;
0353     struct arm_mhuv2_mbox_msg *msg;
0354     u32 *data;
0355     int i, idx;
0356 
0357     msg = kzalloc(sizeof(*msg) + windows * MHUV2_STAT_BYTES, GFP_KERNEL);
0358     if (!msg)
0359         return ERR_PTR(-ENOMEM);
0360 
0361     data = msg->data = msg + 1;
0362     msg->len = windows * MHUV2_STAT_BYTES;
0363 
0364     /*
0365      * Messages are expected in order of most significant word to least
0366      * significant word. Refer mhuv2_data_transfer_send_data() for more
0367      * details.
0368      *
0369      * We also need to read the stat register instead of stat_masked, as we
0370      * masked all but the last window.
0371      *
0372      * Last channel window must be cleared as the final operation. Upon
0373      * clearing the last channel window register, which is unmasked in
0374      * data-transfer protocol, the interrupt is de-asserted.
0375      */
0376     for (i = 0; i < windows; i++) {
0377         idx = priv->ch_wn_idx + i;
0378         data[windows - 1 - i] = readl_relaxed(&mhu->recv->ch_wn[idx].stat);
0379         writel_relaxed(0xFFFFFFFF, &mhu->recv->ch_wn[idx].stat_clear);
0380     }
0381 
0382     return msg;
0383 }
0384 
0385 static void mhuv2_data_transfer_tx_startup(struct mhuv2 *mhu,
0386                        struct mbox_chan *chan)
0387 {
0388     struct mhuv2_mbox_chan_priv *priv = chan->con_priv;
0389     int i = priv->ch_wn_idx + priv->windows - 1;
0390 
0391     /* Enable interrupts only for the last window */
0392     if (mhu->minor) {
0393         writel_relaxed(0x1, &mhu->send->ch_wn[i].int_clr);
0394         writel_relaxed(0x1, &mhu->send->ch_wn[i].int_en);
0395     }
0396 }
0397 
0398 static void mhuv2_data_transfer_tx_shutdown(struct mhuv2 *mhu,
0399                         struct mbox_chan *chan)
0400 {
0401     struct mhuv2_mbox_chan_priv *priv = chan->con_priv;
0402     int i = priv->ch_wn_idx + priv->windows - 1;
0403 
0404     if (mhu->minor)
0405         writel_relaxed(0x0, &mhu->send->ch_wn[i].int_en);
0406 }
0407 
0408 static int mhuv2_data_transfer_last_tx_done(struct mhuv2 *mhu,
0409                         struct mbox_chan *chan)
0410 {
0411     struct mhuv2_mbox_chan_priv *priv = chan->con_priv;
0412     int i = priv->ch_wn_idx + priv->windows - 1;
0413 
0414     /* Just checking the last channel window should be enough */
0415     return !readl_relaxed(&mhu->send->ch_wn[i].stat);
0416 }
0417 
0418 /*
0419  * Message will be transmitted from most significant to least significant word.
0420  * This is to allow for messages shorter than channel windows to still trigger
0421  * the receiver interrupt which gets activated when the last stat register is
0422  * written. As an example, a 6-word message is to be written on a 4-channel MHU
0423  * connection: Registers marked with '*' are masked, and will not generate an
0424  * interrupt on the receiver side once written.
0425  *
0426  * u32 *data =  [0x00000001], [0x00000002], [0x00000003], [0x00000004],
0427  *      [0x00000005], [0x00000006]
0428  *
0429  * ROUND 1:
0430  * stat reg     To write    Write sequence
0431  * [ stat 3 ]   <-  [0x00000001]    4 <- triggers interrupt on receiver
0432  * [ stat 2 ]   <-  [0x00000002]    3
0433  * [ stat 1 ]   <-  [0x00000003]    2
0434  * [ stat 0 ]   <-  [0x00000004]    1
0435  *
0436  * data += 4 // Increment data pointer by number of stat regs
0437  *
0438  * ROUND 2:
0439  * stat reg     To write    Write sequence
0440  * [ stat 3 ]   <-  [0x00000005]    2 <- triggers interrupt on receiver
0441  * [ stat 2 ]   <-  [0x00000006]    1
0442  * [ stat 1 ]   <-  [0x00000000]
0443  * [ stat 0 ]   <-  [0x00000000]
0444  */
0445 static int mhuv2_data_transfer_send_data(struct mhuv2 *mhu,
0446                      struct mbox_chan *chan, void *arg)
0447 {
0448     const struct arm_mhuv2_mbox_msg *msg = arg;
0449     int bytes_left = msg->len, bytes_to_send, bytes_in_round, i;
0450     struct mhuv2_mbox_chan_priv *priv = chan->con_priv;
0451     int windows = priv->windows;
0452     u32 *data = msg->data, word;
0453 
0454     while (bytes_left) {
0455         if (!data[0]) {
0456             dev_err(mhu->mbox.dev, "Data aligned at first window can't be zero to guarantee interrupt generation at receiver");
0457             return -EINVAL;
0458         }
0459 
0460         while(!mhuv2_data_transfer_last_tx_done(mhu, chan))
0461             continue;
0462 
0463         bytes_in_round = min(bytes_left, (int)(windows * MHUV2_STAT_BYTES));
0464 
0465         for (i = windows - 1; i >= 0; i--) {
0466             /* Data less than windows can transfer ? */
0467             if (unlikely(bytes_in_round <= i * MHUV2_STAT_BYTES))
0468                 continue;
0469 
0470             word = data[i];
0471             bytes_to_send = bytes_in_round & (MHUV2_STAT_BYTES - 1);
0472             if (unlikely(bytes_to_send))
0473                 word &= LSB_MASK(bytes_to_send);
0474             else
0475                 bytes_to_send = MHUV2_STAT_BYTES;
0476 
0477             writel_relaxed(word, &mhu->send->ch_wn[priv->ch_wn_idx + windows - 1 - i].stat_set);
0478             bytes_left -= bytes_to_send;
0479             bytes_in_round -= bytes_to_send;
0480         }
0481 
0482         data += windows;
0483     }
0484 
0485     return 0;
0486 }
0487 
0488 static const struct mhuv2_protocol_ops mhuv2_data_transfer_ops = {
0489     .rx_startup = mhuv2_data_transfer_rx_startup,
0490     .rx_shutdown = mhuv2_data_transfer_rx_shutdown,
0491     .read_data = mhuv2_data_transfer_read_data,
0492     .tx_startup = mhuv2_data_transfer_tx_startup,
0493     .tx_shutdown = mhuv2_data_transfer_tx_shutdown,
0494     .last_tx_done = mhuv2_data_transfer_last_tx_done,
0495     .send_data = mhuv2_data_transfer_send_data,
0496 };
0497 
0498 /* Interrupt handlers */
0499 
0500 static struct mbox_chan *get_irq_chan_comb(struct mhuv2 *mhu, u32 __iomem *reg)
0501 {
0502     struct mbox_chan *chans = mhu->mbox.chans;
0503     int channel = 0, i, offset = 0, windows, protocol, ch_wn;
0504     u32 stat;
0505 
0506     for (i = 0; i < MHUV2_CMB_INT_ST_REG_CNT; i++) {
0507         stat = readl_relaxed(reg + i);
0508         if (!stat)
0509             continue;
0510 
0511         ch_wn = i * MHUV2_STAT_BITS + __builtin_ctz(stat);
0512 
0513         for (i = 0; i < mhu->length; i += 2) {
0514             protocol = mhu->protocols[i];
0515             windows = mhu->protocols[i + 1];
0516 
0517             if (ch_wn >= offset + windows) {
0518                 if (protocol == DOORBELL)
0519                     channel += MHUV2_STAT_BITS * windows;
0520                 else
0521                     channel++;
0522 
0523                 offset += windows;
0524                 continue;
0525             }
0526 
0527             /* Return first chan of the window in doorbell mode */
0528             if (protocol == DOORBELL)
0529                 channel += MHUV2_STAT_BITS * (ch_wn - offset);
0530 
0531             return &chans[channel];
0532         }
0533     }
0534 
0535     return ERR_PTR(-EIO);
0536 }
0537 
0538 static irqreturn_t mhuv2_sender_interrupt(int irq, void *data)
0539 {
0540     struct mhuv2 *mhu = data;
0541     struct device *dev = mhu->mbox.dev;
0542     struct mhuv2_mbox_chan_priv *priv;
0543     struct mbox_chan *chan;
0544     unsigned long flags;
0545     int i, found = 0;
0546     u32 stat;
0547 
0548     chan = get_irq_chan_comb(mhu, mhu->send->chcomb_int_st);
0549     if (IS_ERR(chan)) {
0550         dev_warn(dev, "Failed to find channel for the Tx interrupt\n");
0551         return IRQ_NONE;
0552     }
0553     priv = chan->con_priv;
0554 
0555     if (!IS_PROTOCOL_DOORBELL(priv)) {
0556         writel_relaxed(1, &mhu->send->ch_wn[priv->ch_wn_idx + priv->windows - 1].int_clr);
0557 
0558         if (chan->cl) {
0559             mbox_chan_txdone(chan, 0);
0560             return IRQ_HANDLED;
0561         }
0562 
0563         dev_warn(dev, "Tx interrupt Received on channel (%u) not currently attached to a mailbox client\n",
0564              priv->ch_wn_idx);
0565         return IRQ_NONE;
0566     }
0567 
0568     /* Clear the interrupt first, so we don't miss any doorbell later */
0569     writel_relaxed(1, &mhu->send->ch_wn[priv->ch_wn_idx].int_clr);
0570 
0571     /*
0572      * In Doorbell mode, make sure no new transitions happen while the
0573      * interrupt handler is trying to find the finished doorbell tx
0574      * operations, else we may think few of the transfers were complete
0575      * before they actually were.
0576      */
0577     spin_lock_irqsave(&mhu->doorbell_pending_lock, flags);
0578 
0579     /*
0580      * In case of doorbell mode, the first channel of the window is returned
0581      * by get_irq_chan_comb(). Find all the pending channels here.
0582      */
0583     stat = readl_relaxed(&mhu->send->ch_wn[priv->ch_wn_idx].stat);
0584 
0585     for (i = 0; i < MHUV2_STAT_BITS; i++) {
0586         priv = chan[i].con_priv;
0587 
0588         /* Find cases where pending was 1, but stat's bit is cleared */
0589         if (priv->pending ^ ((stat >> i) & 0x1)) {
0590             BUG_ON(!priv->pending);
0591 
0592             if (!chan->cl) {
0593                 dev_warn(dev, "Tx interrupt received on doorbell (%u : %u) channel not currently attached to a mailbox client\n",
0594                      priv->ch_wn_idx, i);
0595                 continue;
0596             }
0597 
0598             mbox_chan_txdone(&chan[i], 0);
0599             priv->pending = 0;
0600             found++;
0601         }
0602     }
0603 
0604     spin_unlock_irqrestore(&mhu->doorbell_pending_lock, flags);
0605 
0606     if (!found) {
0607         /*
0608          * We may have already processed the doorbell in the previous
0609          * iteration if the interrupt came right after we cleared it but
0610          * before we read the stat register.
0611          */
0612         dev_dbg(dev, "Couldn't find the doorbell (%u) for the Tx interrupt interrupt\n",
0613             priv->ch_wn_idx);
0614         return IRQ_NONE;
0615     }
0616 
0617     return IRQ_HANDLED;
0618 }
0619 
0620 static struct mbox_chan *get_irq_chan_comb_rx(struct mhuv2 *mhu)
0621 {
0622     struct mhuv2_mbox_chan_priv *priv;
0623     struct mbox_chan *chan;
0624     u32 stat;
0625 
0626     chan = get_irq_chan_comb(mhu, mhu->recv->chcomb_int_st);
0627     if (IS_ERR(chan))
0628         return chan;
0629 
0630     priv = chan->con_priv;
0631     if (!IS_PROTOCOL_DOORBELL(priv))
0632         return chan;
0633 
0634     /*
0635      * In case of doorbell mode, the first channel of the window is returned
0636      * by the routine. Find the exact channel here.
0637      */
0638     stat = readl_relaxed(&mhu->recv->ch_wn[priv->ch_wn_idx].stat_masked);
0639     BUG_ON(!stat);
0640 
0641     return chan + __builtin_ctz(stat);
0642 }
0643 
0644 static struct mbox_chan *get_irq_chan_stat_rx(struct mhuv2 *mhu)
0645 {
0646     struct mbox_chan *chans = mhu->mbox.chans;
0647     struct mhuv2_mbox_chan_priv *priv;
0648     u32 stat;
0649     int i = 0;
0650 
0651     while (i < mhu->mbox.num_chans) {
0652         priv = chans[i].con_priv;
0653         stat = readl_relaxed(&mhu->recv->ch_wn[priv->ch_wn_idx].stat_masked);
0654 
0655         if (stat) {
0656             if (IS_PROTOCOL_DOORBELL(priv))
0657                 i += __builtin_ctz(stat);
0658             return &chans[i];
0659         }
0660 
0661         i += IS_PROTOCOL_DOORBELL(priv) ? MHUV2_STAT_BITS : 1;
0662     }
0663 
0664     return ERR_PTR(-EIO);
0665 }
0666 
0667 static struct mbox_chan *get_irq_chan_rx(struct mhuv2 *mhu)
0668 {
0669     if (!mhu->minor)
0670         return get_irq_chan_stat_rx(mhu);
0671 
0672     return get_irq_chan_comb_rx(mhu);
0673 }
0674 
0675 static irqreturn_t mhuv2_receiver_interrupt(int irq, void *arg)
0676 {
0677     struct mhuv2 *mhu = arg;
0678     struct mbox_chan *chan = get_irq_chan_rx(mhu);
0679     struct device *dev = mhu->mbox.dev;
0680     struct mhuv2_mbox_chan_priv *priv;
0681     int ret = IRQ_NONE;
0682     void *data;
0683 
0684     if (IS_ERR(chan)) {
0685         dev_warn(dev, "Failed to find channel for the rx interrupt\n");
0686         return IRQ_NONE;
0687     }
0688     priv = chan->con_priv;
0689 
0690     /* Read and clear the data first */
0691     data = priv->ops->read_data(mhu, chan);
0692 
0693     if (!chan->cl) {
0694         dev_warn(dev, "Received data on channel (%u) not currently attached to a mailbox client\n",
0695              priv->ch_wn_idx);
0696     } else if (IS_ERR(data)) {
0697         dev_err(dev, "Failed to read data: %lu\n", PTR_ERR(data));
0698     } else {
0699         mbox_chan_received_data(chan, data);
0700         ret = IRQ_HANDLED;
0701     }
0702 
0703     if (!IS_ERR(data))
0704         kfree(data);
0705 
0706     return ret;
0707 }
0708 
0709 /* Sender and receiver ops */
0710 static bool mhuv2_sender_last_tx_done(struct mbox_chan *chan)
0711 {
0712     struct mhuv2 *mhu = mhu_from_mbox(chan->mbox);
0713     struct mhuv2_mbox_chan_priv *priv = chan->con_priv;
0714 
0715     return priv->ops->last_tx_done(mhu, chan);
0716 }
0717 
0718 static int mhuv2_sender_send_data(struct mbox_chan *chan, void *data)
0719 {
0720     struct mhuv2 *mhu = mhu_from_mbox(chan->mbox);
0721     struct mhuv2_mbox_chan_priv *priv = chan->con_priv;
0722 
0723     if (!priv->ops->last_tx_done(mhu, chan))
0724         return -EBUSY;
0725 
0726     return priv->ops->send_data(mhu, chan, data);
0727 }
0728 
0729 static int mhuv2_sender_startup(struct mbox_chan *chan)
0730 {
0731     struct mhuv2 *mhu = mhu_from_mbox(chan->mbox);
0732     struct mhuv2_mbox_chan_priv *priv = chan->con_priv;
0733 
0734     if (priv->ops->tx_startup)
0735         priv->ops->tx_startup(mhu, chan);
0736     return 0;
0737 }
0738 
0739 static void mhuv2_sender_shutdown(struct mbox_chan *chan)
0740 {
0741     struct mhuv2 *mhu = mhu_from_mbox(chan->mbox);
0742     struct mhuv2_mbox_chan_priv *priv = chan->con_priv;
0743 
0744     if (priv->ops->tx_shutdown)
0745         priv->ops->tx_shutdown(mhu, chan);
0746 }
0747 
0748 static const struct mbox_chan_ops mhuv2_sender_ops = {
0749     .send_data = mhuv2_sender_send_data,
0750     .startup = mhuv2_sender_startup,
0751     .shutdown = mhuv2_sender_shutdown,
0752     .last_tx_done = mhuv2_sender_last_tx_done,
0753 };
0754 
0755 static int mhuv2_receiver_startup(struct mbox_chan *chan)
0756 {
0757     struct mhuv2 *mhu = mhu_from_mbox(chan->mbox);
0758     struct mhuv2_mbox_chan_priv *priv = chan->con_priv;
0759 
0760     return priv->ops->rx_startup(mhu, chan);
0761 }
0762 
0763 static void mhuv2_receiver_shutdown(struct mbox_chan *chan)
0764 {
0765     struct mhuv2 *mhu = mhu_from_mbox(chan->mbox);
0766     struct mhuv2_mbox_chan_priv *priv = chan->con_priv;
0767 
0768     priv->ops->rx_shutdown(mhu, chan);
0769 }
0770 
0771 static int mhuv2_receiver_send_data(struct mbox_chan *chan, void *data)
0772 {
0773     dev_err(chan->mbox->dev,
0774         "Trying to transmit on a receiver MHU frame\n");
0775     return -EIO;
0776 }
0777 
0778 static bool mhuv2_receiver_last_tx_done(struct mbox_chan *chan)
0779 {
0780     dev_err(chan->mbox->dev, "Trying to Tx poll on a receiver MHU frame\n");
0781     return true;
0782 }
0783 
0784 static const struct mbox_chan_ops mhuv2_receiver_ops = {
0785     .send_data = mhuv2_receiver_send_data,
0786     .startup = mhuv2_receiver_startup,
0787     .shutdown = mhuv2_receiver_shutdown,
0788     .last_tx_done = mhuv2_receiver_last_tx_done,
0789 };
0790 
0791 static struct mbox_chan *mhuv2_mbox_of_xlate(struct mbox_controller *mbox,
0792                          const struct of_phandle_args *pa)
0793 {
0794     struct mhuv2 *mhu = mhu_from_mbox(mbox);
0795     struct mbox_chan *chans = mbox->chans;
0796     int channel = 0, i, offset, doorbell, protocol, windows;
0797 
0798     if (pa->args_count != 2)
0799         return ERR_PTR(-EINVAL);
0800 
0801     offset = pa->args[0];
0802     doorbell = pa->args[1];
0803     if (doorbell >= MHUV2_STAT_BITS)
0804         goto out;
0805 
0806     for (i = 0; i < mhu->length; i += 2) {
0807         protocol = mhu->protocols[i];
0808         windows = mhu->protocols[i + 1];
0809 
0810         if (protocol == DOORBELL) {
0811             if (offset < windows)
0812                 return &chans[channel + MHUV2_STAT_BITS * offset + doorbell];
0813 
0814             channel += MHUV2_STAT_BITS * windows;
0815             offset -= windows;
0816         } else {
0817             if (offset == 0) {
0818                 if (doorbell)
0819                     goto out;
0820 
0821                 return &chans[channel];
0822             }
0823 
0824             channel++;
0825             offset--;
0826         }
0827     }
0828 
0829 out:
0830     dev_err(mbox->dev, "Couldn't xlate to a valid channel (%d: %d)\n",
0831         pa->args[0], doorbell);
0832     return ERR_PTR(-ENODEV);
0833 }
0834 
0835 static int mhuv2_verify_protocol(struct mhuv2 *mhu)
0836 {
0837     struct device *dev = mhu->mbox.dev;
0838     int protocol, windows, channels = 0, total_windows = 0, i;
0839 
0840     for (i = 0; i < mhu->length; i += 2) {
0841         protocol = mhu->protocols[i];
0842         windows = mhu->protocols[i + 1];
0843 
0844         if (!windows) {
0845             dev_err(dev, "Window size can't be zero (%d)\n", i);
0846             return -EINVAL;
0847         }
0848         total_windows += windows;
0849 
0850         if (protocol == DOORBELL) {
0851             channels += MHUV2_STAT_BITS * windows;
0852         } else if (protocol == DATA_TRANSFER) {
0853             channels++;
0854         } else {
0855             dev_err(dev, "Invalid protocol (%d) present in %s property at index %d\n",
0856                 protocol, MHUV2_PROTOCOL_PROP, i);
0857             return -EINVAL;
0858         }
0859     }
0860 
0861     if (total_windows > mhu->windows) {
0862         dev_err(dev, "Channel windows can't be more than what's implemented by the hardware ( %d: %d)\n",
0863             total_windows, mhu->windows);
0864         return -EINVAL;
0865     }
0866 
0867     mhu->mbox.num_chans = channels;
0868     return 0;
0869 }
0870 
0871 static int mhuv2_allocate_channels(struct mhuv2 *mhu)
0872 {
0873     struct mbox_controller *mbox = &mhu->mbox;
0874     struct mhuv2_mbox_chan_priv *priv;
0875     struct device *dev = mbox->dev;
0876     struct mbox_chan *chans;
0877     int protocol, windows = 0, next_window = 0, i, j, k;
0878 
0879     chans = devm_kcalloc(dev, mbox->num_chans, sizeof(*chans), GFP_KERNEL);
0880     if (!chans)
0881         return -ENOMEM;
0882 
0883     mbox->chans = chans;
0884 
0885     for (i = 0; i < mhu->length; i += 2) {
0886         next_window += windows;
0887 
0888         protocol = mhu->protocols[i];
0889         windows = mhu->protocols[i + 1];
0890 
0891         if (protocol == DATA_TRANSFER) {
0892             priv = devm_kmalloc(dev, sizeof(*priv), GFP_KERNEL);
0893             if (!priv)
0894                 return -ENOMEM;
0895 
0896             priv->ch_wn_idx = next_window;
0897             priv->ops = &mhuv2_data_transfer_ops;
0898             priv->windows = windows;
0899             chans++->con_priv = priv;
0900             continue;
0901         }
0902 
0903         for (j = 0; j < windows; j++) {
0904             for (k = 0; k < MHUV2_STAT_BITS; k++) {
0905                 priv = devm_kmalloc(dev, sizeof(*priv), GFP_KERNEL);
0906                 if (!priv)
0907                     return -ENOMEM;
0908 
0909                 priv->ch_wn_idx = next_window + j;
0910                 priv->ops = &mhuv2_doorbell_ops;
0911                 priv->doorbell = k;
0912                 chans++->con_priv = priv;
0913             }
0914 
0915             /*
0916              * Permanently enable interrupt as we can't
0917              * control it per doorbell.
0918              */
0919             if (mhu->frame == SENDER_FRAME && mhu->minor)
0920                 writel_relaxed(0x1, &mhu->send->ch_wn[priv->ch_wn_idx].int_en);
0921         }
0922     }
0923 
0924     /* Make sure we have initialized all channels */
0925     BUG_ON(chans - mbox->chans != mbox->num_chans);
0926 
0927     return 0;
0928 }
0929 
0930 static int mhuv2_parse_channels(struct mhuv2 *mhu)
0931 {
0932     struct device *dev = mhu->mbox.dev;
0933     const struct device_node *np = dev->of_node;
0934     int ret, count;
0935     u32 *protocols;
0936 
0937     count = of_property_count_u32_elems(np, MHUV2_PROTOCOL_PROP);
0938     if (count <= 0 || count % 2) {
0939         dev_err(dev, "Invalid %s property (%d)\n", MHUV2_PROTOCOL_PROP,
0940             count);
0941         return -EINVAL;
0942     }
0943 
0944     protocols = devm_kmalloc_array(dev, count, sizeof(*protocols), GFP_KERNEL);
0945     if (!protocols)
0946         return -ENOMEM;
0947 
0948     ret = of_property_read_u32_array(np, MHUV2_PROTOCOL_PROP, protocols, count);
0949     if (ret) {
0950         dev_err(dev, "Failed to read %s property: %d\n",
0951             MHUV2_PROTOCOL_PROP, ret);
0952         return ret;
0953     }
0954 
0955     mhu->protocols = protocols;
0956     mhu->length = count;
0957 
0958     ret = mhuv2_verify_protocol(mhu);
0959     if (ret)
0960         return ret;
0961 
0962     return mhuv2_allocate_channels(mhu);
0963 }
0964 
0965 static int mhuv2_tx_init(struct amba_device *adev, struct mhuv2 *mhu,
0966              void __iomem *reg)
0967 {
0968     struct device *dev = mhu->mbox.dev;
0969     int ret, i;
0970 
0971     mhu->frame = SENDER_FRAME;
0972     mhu->mbox.ops = &mhuv2_sender_ops;
0973     mhu->send = reg;
0974 
0975     mhu->windows = readl_relaxed_bitfield(&mhu->send->mhu_cfg, struct mhu_cfg_t, num_ch);
0976     mhu->minor = readl_relaxed_bitfield(&mhu->send->aidr, struct aidr_t, arch_minor_rev);
0977 
0978     spin_lock_init(&mhu->doorbell_pending_lock);
0979 
0980     /*
0981      * For minor version 1 and forward, tx interrupt is provided by
0982      * the controller.
0983      */
0984     if (mhu->minor && adev->irq[0]) {
0985         ret = devm_request_threaded_irq(dev, adev->irq[0], NULL,
0986                         mhuv2_sender_interrupt,
0987                         IRQF_ONESHOT, "mhuv2-tx", mhu);
0988         if (ret) {
0989             dev_err(dev, "Failed to request tx IRQ, fallback to polling mode: %d\n",
0990                 ret);
0991         } else {
0992             mhu->mbox.txdone_irq = true;
0993             mhu->mbox.txdone_poll = false;
0994             mhu->irq = adev->irq[0];
0995 
0996             writel_relaxed_bitfield(1, &mhu->send->int_en, struct int_en_t, chcomb);
0997 
0998             /* Disable all channel interrupts */
0999             for (i = 0; i < mhu->windows; i++)
1000                 writel_relaxed(0x0, &mhu->send->ch_wn[i].int_en);
1001 
1002             goto out;
1003         }
1004     }
1005 
1006     mhu->mbox.txdone_irq = false;
1007     mhu->mbox.txdone_poll = true;
1008     mhu->mbox.txpoll_period = 1;
1009 
1010 out:
1011     /* Wait for receiver to be ready */
1012     writel_relaxed(0x1, &mhu->send->access_request);
1013     while (!readl_relaxed(&mhu->send->access_ready))
1014         continue;
1015 
1016     return 0;
1017 }
1018 
1019 static int mhuv2_rx_init(struct amba_device *adev, struct mhuv2 *mhu,
1020              void __iomem *reg)
1021 {
1022     struct device *dev = mhu->mbox.dev;
1023     int ret, i;
1024 
1025     mhu->frame = RECEIVER_FRAME;
1026     mhu->mbox.ops = &mhuv2_receiver_ops;
1027     mhu->recv = reg;
1028 
1029     mhu->windows = readl_relaxed_bitfield(&mhu->recv->mhu_cfg, struct mhu_cfg_t, num_ch);
1030     mhu->minor = readl_relaxed_bitfield(&mhu->recv->aidr, struct aidr_t, arch_minor_rev);
1031 
1032     mhu->irq = adev->irq[0];
1033     if (!mhu->irq) {
1034         dev_err(dev, "Missing receiver IRQ\n");
1035         return -EINVAL;
1036     }
1037 
1038     ret = devm_request_threaded_irq(dev, mhu->irq, NULL,
1039                     mhuv2_receiver_interrupt, IRQF_ONESHOT,
1040                     "mhuv2-rx", mhu);
1041     if (ret) {
1042         dev_err(dev, "Failed to request rx IRQ\n");
1043         return ret;
1044     }
1045 
1046     /* Mask all the channel windows */
1047     for (i = 0; i < mhu->windows; i++)
1048         writel_relaxed(0xFFFFFFFF, &mhu->recv->ch_wn[i].mask_set);
1049 
1050     if (mhu->minor)
1051         writel_relaxed_bitfield(1, &mhu->recv->int_en, struct int_en_t, chcomb);
1052 
1053     return 0;
1054 }
1055 
1056 static int mhuv2_probe(struct amba_device *adev, const struct amba_id *id)
1057 {
1058     struct device *dev = &adev->dev;
1059     const struct device_node *np = dev->of_node;
1060     struct mhuv2 *mhu;
1061     void __iomem *reg;
1062     int ret = -EINVAL;
1063 
1064     reg = devm_of_iomap(dev, dev->of_node, 0, NULL);
1065     if (!reg)
1066         return -ENOMEM;
1067 
1068     mhu = devm_kzalloc(dev, sizeof(*mhu), GFP_KERNEL);
1069     if (!mhu)
1070         return -ENOMEM;
1071 
1072     mhu->mbox.dev = dev;
1073     mhu->mbox.of_xlate = mhuv2_mbox_of_xlate;
1074 
1075     if (of_device_is_compatible(np, "arm,mhuv2-tx"))
1076         ret = mhuv2_tx_init(adev, mhu, reg);
1077     else if (of_device_is_compatible(np, "arm,mhuv2-rx"))
1078         ret = mhuv2_rx_init(adev, mhu, reg);
1079     else
1080         dev_err(dev, "Invalid compatible property\n");
1081 
1082     if (ret)
1083         return ret;
1084 
1085     /* Channel windows can't be 0 */
1086     BUG_ON(!mhu->windows);
1087 
1088     ret = mhuv2_parse_channels(mhu);
1089     if (ret)
1090         return ret;
1091 
1092     amba_set_drvdata(adev, mhu);
1093 
1094     ret = devm_mbox_controller_register(dev, &mhu->mbox);
1095     if (ret)
1096         dev_err(dev, "failed to register ARM MHUv2 driver %d\n", ret);
1097 
1098     return ret;
1099 }
1100 
1101 static void mhuv2_remove(struct amba_device *adev)
1102 {
1103     struct mhuv2 *mhu = amba_get_drvdata(adev);
1104 
1105     if (mhu->frame == SENDER_FRAME)
1106         writel_relaxed(0x0, &mhu->send->access_request);
1107 }
1108 
1109 static struct amba_id mhuv2_ids[] = {
1110     {
1111         /* 2.0 */
1112         .id = 0xbb0d1,
1113         .mask = 0xfffff,
1114     },
1115     {
1116         /* 2.1 */
1117         .id = 0xbb076,
1118         .mask = 0xfffff,
1119     },
1120     { 0, 0 },
1121 };
1122 MODULE_DEVICE_TABLE(amba, mhuv2_ids);
1123 
1124 static struct amba_driver mhuv2_driver = {
1125     .drv = {
1126         .name   = "arm-mhuv2",
1127     },
1128     .id_table   = mhuv2_ids,
1129     .probe      = mhuv2_probe,
1130     .remove     = mhuv2_remove,
1131 };
1132 module_amba_driver(mhuv2_driver);
1133 
1134 MODULE_LICENSE("GPL v2");
1135 MODULE_DESCRIPTION("ARM MHUv2 Driver");
1136 MODULE_AUTHOR("Viresh Kumar <viresh.kumar@linaro.org>");
1137 MODULE_AUTHOR("Tushar Khandelwal <tushar.khandelwal@arm.com>");
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