drivers/mailbox/arm_mhu.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2013-2015 Fujitsu Semiconductor Ltd.
0004  * Copyright (C) 2015 Linaro Ltd.
0005  * Author: Jassi Brar <jaswinder.singh@linaro.org>
0006  */
0007
0008 #include <linux/amba/bus.h>
0009 #include <linux/device.h>
0010 #include <linux/err.h>
0011 #include <linux/interrupt.h>
0012 #include <linux/io.h>
0013 #include <linux/mailbox_controller.h>
0014 #include <linux/module.h>
0015
0016 #define INTR_STAT_OFS   0x0
0017 #define INTR_SET_OFS    0x8
0018 #define INTR_CLR_OFS    0x10
0019
0020 #define MHU_LP_OFFSET   0x0
0021 #define MHU_HP_OFFSET   0x20
0022 #define MHU_SEC_OFFSET  0x200
0023 #define TX_REG_OFFSET   0x100
0024
0025 #define MHU_CHANS   3
0026
0027 struct mhu_link {
0028     unsigned irq;
0029     void __iomem *tx_reg;
0030     void __iomem *rx_reg;
0031 };
0032
0033 struct arm_mhu {
0034     void __iomem *base;
0035     struct mhu_link mlink[MHU_CHANS];
0036     struct mbox_chan chan[MHU_CHANS];
0037     struct mbox_controller mbox;
0038 };
0039
0040 static irqreturn_t mhu_rx_interrupt(int irq, void *p)
0041 {
0042     struct mbox_chan *chan = p;
0043     struct mhu_link *mlink = chan->con_priv;
0044     u32 val;
0045
0046     val = readl_relaxed(mlink->rx_reg + INTR_STAT_OFS);
0047     if (!val)
0048         return IRQ_NONE;
0049
0050     mbox_chan_received_data(chan, (void *)&val);
0051
0052     writel_relaxed(val, mlink->rx_reg + INTR_CLR_OFS);
0053
0054     return IRQ_HANDLED;
0055 }
0056
0057 static bool mhu_last_tx_done(struct mbox_chan *chan)
0058 {
0059     struct mhu_link *mlink = chan->con_priv;
0060     u32 val = readl_relaxed(mlink->tx_reg + INTR_STAT_OFS);
0061
0062     return (val == 0);
0063 }
0064
0065 static int mhu_send_data(struct mbox_chan *chan, void *data)
0066 {
0067     struct mhu_link *mlink = chan->con_priv;
0068     u32 *arg = data;
0069
0070     writel_relaxed(*arg, mlink->tx_reg + INTR_SET_OFS);
0071
0072     return 0;
0073 }
0074
0075 static int mhu_startup(struct mbox_chan *chan)
0076 {
0077     struct mhu_link *mlink = chan->con_priv;
0078     u32 val;
0079     int ret;
0080
0081     val = readl_relaxed(mlink->tx_reg + INTR_STAT_OFS);
0082     writel_relaxed(val, mlink->tx_reg + INTR_CLR_OFS);
0083
0084     ret = request_irq(mlink->irq, mhu_rx_interrupt,
0085               IRQF_SHARED, "mhu_link", chan);
0086     if (ret) {
0087         dev_err(chan->mbox->dev,
0088             "Unable to acquire IRQ %d\n", mlink->irq);
0089         return ret;
0090     }
0091
0092     return 0;
0093 }
0094
0095 static void mhu_shutdown(struct mbox_chan *chan)
0096 {
0097     struct mhu_link *mlink = chan->con_priv;
0098
0099     free_irq(mlink->irq, chan);
0100 }
0101
0102 static const struct mbox_chan_ops mhu_ops = {
0103     .send_data = mhu_send_data,
0104     .startup = mhu_startup,
0105     .shutdown = mhu_shutdown,
0106     .last_tx_done = mhu_last_tx_done,
0107 };
0108
0109 static int mhu_probe(struct amba_device *adev, const struct amba_id *id)
0110 {
0111     int i, err;
0112     struct arm_mhu *mhu;
0113     struct device *dev = &adev->dev;
0114     int mhu_reg[MHU_CHANS] = {MHU_LP_OFFSET, MHU_HP_OFFSET, MHU_SEC_OFFSET};
0115
0116     if (!of_device_is_compatible(dev->of_node, "arm,mhu"))
0117         return -ENODEV;
0118
0119     /* Allocate memory for device */
0120     mhu = devm_kzalloc(dev, sizeof(*mhu), GFP_KERNEL);
0121     if (!mhu)
0122         return -ENOMEM;
0123
0124     mhu->base = devm_ioremap_resource(dev, &adev->res);
0125     if (IS_ERR(mhu->base))
0126         return PTR_ERR(mhu->base);
0127
0128     for (i = 0; i < MHU_CHANS; i++) {
0129         mhu->chan[i].con_priv = &mhu->mlink[i];
0130         mhu->mlink[i].irq = adev->irq[i];
0131         mhu->mlink[i].rx_reg = mhu->base + mhu_reg[i];
0132         mhu->mlink[i].tx_reg = mhu->mlink[i].rx_reg + TX_REG_OFFSET;
0133     }
0134
0135     mhu->mbox.dev = dev;
0136     mhu->mbox.chans = &mhu->chan[0];
0137     mhu->mbox.num_chans = MHU_CHANS;
0138     mhu->mbox.ops = &mhu_ops;
0139     mhu->mbox.txdone_irq = false;
0140     mhu->mbox.txdone_poll = true;
0141     mhu->mbox.txpoll_period = 1;
0142
0143     amba_set_drvdata(adev, mhu);
0144
0145     err = devm_mbox_controller_register(dev, &mhu->mbox);
0146     if (err) {
0147         dev_err(dev, "Failed to register mailboxes %d\n", err);
0148         return err;
0149     }
0150
0151     dev_info(dev, "ARM MHU Mailbox registered\n");
0152     return 0;
0153 }
0154
0155 static struct amba_id mhu_ids[] = {
0156     {
0157         .id = 0x1bb098,
0158         .mask   = 0xffffff,
0159     },
0160     { 0, 0 },
0161 };
0162 MODULE_DEVICE_TABLE(amba, mhu_ids);
0163
0164 static struct amba_driver arm_mhu_driver = {
0165     .drv = {
0166         .name   = "mhu",
0167     },
0168     .id_table   = mhu_ids,
0169     .probe      = mhu_probe,
0170 };
0171 module_amba_driver(arm_mhu_driver);
0172
0173 MODULE_LICENSE("GPL v2");
0174 MODULE_DESCRIPTION("ARM MHU Driver");
0175 MODULE_AUTHOR("Jassi Brar <jassisinghbrar@gmail.com>");