0001 # SPDX-License-Identifier: GPL-2.0-only
0002 menuconfig MAILBOX
0003 bool "Mailbox Hardware Support"
0004 help
0005 Mailbox is a framework to control hardware communication between
0006 on-chip processors through queued messages and interrupt driven
0007 signals. Say Y if your platform supports hardware mailboxes.
0008
0009 if MAILBOX
0010
0011 config APPLE_MAILBOX
0012 tristate "Apple Mailbox driver"
0013 depends on ARCH_APPLE || (ARM64 && COMPILE_TEST)
0014 default ARCH_APPLE
0015 help
0016 Apple SoCs have various co-processors required for certain
0017 peripherals to work (NVMe, display controller, etc.). This
0018 driver adds support for the mailbox controller used to
0019 communicate with those.
0020
0021 Say Y here if you have a Apple SoC.
0022
0023 config ARM_MHU
0024 tristate "ARM MHU Mailbox"
0025 depends on ARM_AMBA
0026 help
0027 Say Y here if you want to build the ARM MHU controller driver.
0028 The controller has 3 mailbox channels, the last of which can be
0029 used in Secure mode only.
0030
0031 config ARM_MHU_V2
0032 tristate "ARM MHUv2 Mailbox"
0033 depends on ARM_AMBA
0034 help
0035 Say Y here if you want to build the ARM MHUv2 controller driver,
0036 which provides unidirectional mailboxes between processing elements.
0037
0038 config IMX_MBOX
0039 tristate "i.MX Mailbox"
0040 depends on ARCH_MXC || COMPILE_TEST
0041 help
0042 Mailbox implementation for i.MX Messaging Unit (MU).
0043
0044 config PLATFORM_MHU
0045 tristate "Platform MHU Mailbox"
0046 depends on OF
0047 depends on HAS_IOMEM
0048 help
0049 Say Y here if you want to build a platform specific variant MHU
0050 controller driver.
0051 The controller has a maximum of 3 mailbox channels, the last of
0052 which can be used in Secure mode only.
0053
0054 config PL320_MBOX
0055 bool "ARM PL320 Mailbox"
0056 depends on ARM_AMBA
0057 help
0058 An implementation of the ARM PL320 Interprocessor Communication
0059 Mailbox (IPCM), tailored for the Calxeda Highbank. It is used to
0060 send short messages between Highbank's A9 cores and the EnergyCore
0061 Management Engine, primarily for cpufreq. Say Y here if you want
0062 to use the PL320 IPCM support.
0063
0064 config ARMADA_37XX_RWTM_MBOX
0065 tristate "Armada 37xx rWTM BIU Mailbox"
0066 depends on ARCH_MVEBU || COMPILE_TEST
0067 depends on OF
0068 help
0069 Mailbox implementation for communication with the the firmware
0070 running on the Cortex-M3 rWTM secure processor of the Armada 37xx
0071 SOC. Say Y here if you are building for such a device (for example
0072 the Turris Mox router).
0073
0074 config OMAP2PLUS_MBOX
0075 tristate "OMAP2+ Mailbox framework support"
0076 depends on ARCH_OMAP2PLUS || ARCH_K3
0077 help
0078 Mailbox implementation for OMAP family chips with hardware for
0079 interprocessor communication involving DSP, IVA1.0 and IVA2 in
0080 OMAP2/3; or IPU, IVA HD and DSP in OMAP4/5. Say Y here if you
0081 want to use OMAP2+ Mailbox framework support.
0082
0083 config OMAP_MBOX_KFIFO_SIZE
0084 int "Mailbox kfifo default buffer size (bytes)"
0085 depends on OMAP2PLUS_MBOX
0086 default 256
0087 help
0088 Specify the default size of mailbox's kfifo buffers (bytes).
0089 This can also be changed at runtime (via the mbox_kfifo_size
0090 module parameter).
0091
0092 config ROCKCHIP_MBOX
0093 bool "Rockchip Soc Integrated Mailbox Support"
0094 depends on ARCH_ROCKCHIP || COMPILE_TEST
0095 help
0096 This driver provides support for inter-processor communication
0097 between CPU cores and MCU processor on Some Rockchip SOCs.
0098 Please check it that the Soc you use have Mailbox hardware.
0099 Say Y here if you want to use the Rockchip Mailbox support.
0100
0101 config PCC
0102 bool "Platform Communication Channel Driver"
0103 depends on ACPI
0104 default n
0105 help
0106 ACPI 5.0+ spec defines a generic mode of communication
0107 between the OS and a platform such as the BMC. This medium
0108 (PCC) is typically used by CPPC (ACPI CPU Performance management),
0109 RAS (ACPI reliability protocol) and MPST (ACPI Memory power
0110 states). Select this driver if your platform implements the
0111 PCC clients mentioned above.
0112
0113 config ALTERA_MBOX
0114 tristate "Altera Mailbox"
0115 depends on HAS_IOMEM
0116 help
0117 An implementation of the Altera Mailbox soft core. It is used
0118 to send message between processors. Say Y here if you want to use the
0119 Altera mailbox support.
0120
0121 config BCM2835_MBOX
0122 tristate "BCM2835 Mailbox"
0123 depends on ARCH_BCM2835
0124 help
0125 An implementation of the BCM2385 Mailbox. It is used to invoke
0126 the services of the Videocore. Say Y here if you want to use the
0127 BCM2835 Mailbox.
0128
0129 config STI_MBOX
0130 tristate "STI Mailbox framework support"
0131 depends on ARCH_STI && OF
0132 help
0133 Mailbox implementation for STMicroelectonics family chips with
0134 hardware for interprocessor communication.
0135
0136 config TI_MESSAGE_MANAGER
0137 tristate "Texas Instruments Message Manager Driver"
0138 depends on ARCH_KEYSTONE || ARCH_K3
0139 help
0140 An implementation of Message Manager slave driver for Keystone
0141 and K3 architecture SoCs from Texas Instruments. Message Manager
0142 is a communication entity found on few of Texas Instrument's keystone
0143 and K3 architecture SoCs. These may be used for communication between
0144 multiple processors within the SoC. Select this driver if your
0145 platform has support for the hardware block.
0146
0147 config HI3660_MBOX
0148 tristate "Hi3660 Mailbox" if EXPERT
0149 depends on (ARCH_HISI || COMPILE_TEST)
0150 depends on OF
0151 default ARCH_HISI
0152 help
0153 An implementation of the hi3660 mailbox. It is used to send message
0154 between application processors and other processors/MCU/DSP. Select
0155 Y here if you want to use Hi3660 mailbox controller.
0156
0157 config HI6220_MBOX
0158 tristate "Hi6220 Mailbox" if EXPERT
0159 depends on (ARCH_HISI || COMPILE_TEST)
0160 depends on OF
0161 default ARCH_HISI
0162 help
0163 An implementation of the hi6220 mailbox. It is used to send message
0164 between application processors and MCU. Say Y here if you want to
0165 build Hi6220 mailbox controller driver.
0166
0167 config MAILBOX_TEST
0168 tristate "Mailbox Test Client"
0169 depends on OF
0170 depends on HAS_IOMEM
0171 help
0172 Test client to help with testing new Controller driver
0173 implementations.
0174
0175 config POLARFIRE_SOC_MAILBOX
0176 tristate "PolarFire SoC (MPFS) Mailbox"
0177 depends on HAS_IOMEM
0178 depends on SOC_MICROCHIP_POLARFIRE || COMPILE_TEST
0179 help
0180 This driver adds support for the PolarFire SoC (MPFS) mailbox controller.
0181
0182 To compile this driver as a module, choose M here. the
0183 module will be called mailbox-mpfs.
0184
0185 If unsure, say N.
0186
0187 config QCOM_APCS_IPC
0188 tristate "Qualcomm APCS IPC driver"
0189 depends on ARCH_QCOM || COMPILE_TEST
0190 help
0191 Say y here to enable support for the APCS IPC mailbox driver,
0192 providing an interface for invoking the inter-process communication
0193 signals from the application processor to other masters.
0194
0195 config TEGRA_HSP_MBOX
0196 bool "Tegra HSP (Hardware Synchronization Primitives) Driver"
0197 depends on ARCH_TEGRA
0198 help
0199 The Tegra HSP driver is used for the interprocessor communication
0200 between different remote processors and host processors on Tegra186
0201 and later SoCs. Say Y here if you want to have this support.
0202 If unsure say N.
0203
0204 config XGENE_SLIMPRO_MBOX
0205 tristate "APM SoC X-Gene SLIMpro Mailbox Controller"
0206 depends on ARCH_XGENE
0207 help
0208 An implementation of the APM X-Gene Interprocessor Communication
0209 Mailbox (IPCM) between the ARM 64-bit cores and SLIMpro controller.
0210 It is used to send short messages between ARM64-bit cores and
0211 the SLIMpro Management Engine, primarily for PM. Say Y here if you
0212 want to use the APM X-Gene SLIMpro IPCM support.
0213
0214 config BCM_PDC_MBOX
0215 tristate "Broadcom FlexSparx DMA Mailbox"
0216 depends on ARCH_BCM_IPROC || COMPILE_TEST
0217 help
0218 Mailbox implementation for the Broadcom FlexSparx DMA ring manager,
0219 which provides access to various offload engines on Broadcom
0220 SoCs, including FA2/FA+ on Northstar Plus and PDC on Northstar 2.
0221
0222 config BCM_FLEXRM_MBOX
0223 tristate "Broadcom FlexRM Mailbox"
0224 depends on ARM64
0225 depends on ARCH_BCM_IPROC || COMPILE_TEST
0226 select GENERIC_MSI_IRQ_DOMAIN
0227 default m if ARCH_BCM_IPROC
0228 help
0229 Mailbox implementation of the Broadcom FlexRM ring manager,
0230 which provides access to various offload engines on Broadcom
0231 SoCs. Say Y here if you want to use the Broadcom FlexRM.
0232
0233 config STM32_IPCC
0234 tristate "STM32 IPCC Mailbox"
0235 depends on MACH_STM32MP157 || COMPILE_TEST
0236 help
0237 Mailbox implementation for STMicroelectonics STM32 family chips
0238 with hardware for Inter-Processor Communication Controller (IPCC)
0239 between processors. Say Y here if you want to have this support.
0240
0241 config MTK_ADSP_MBOX
0242 tristate "MediaTek ADSP Mailbox Controller"
0243 depends on ARCH_MEDIATEK || COMPILE_TEST
0244 help
0245 Say yes here to add support for "MediaTek ADSP Mailbox Controller.
0246 This mailbox driver is used to send notification or short message
0247 between processors with ADSP. It will place the message to share
0248 buffer and will access the ipc control.
0249
0250 config MTK_CMDQ_MBOX
0251 tristate "MediaTek CMDQ Mailbox Support"
0252 depends on ARCH_MEDIATEK || COMPILE_TEST
0253 select MTK_INFRACFG
0254 help
0255 Say yes here to add support for the MediaTek Command Queue (CMDQ)
0256 mailbox driver. The CMDQ is used to help read/write registers with
0257 critical time limitation, such as updating display configuration
0258 during the vblank.
0259
0260 config ZYNQMP_IPI_MBOX
0261 bool "Xilinx ZynqMP IPI Mailbox"
0262 depends on ARCH_ZYNQMP && OF
0263 help
0264 Say yes here to add support for Xilinx IPI mailbox driver.
0265 This mailbox driver is used to send notification or short message
0266 between processors with Xilinx ZynqMP IPI. It will place the
0267 message to the IPI buffer and will access the IPI control
0268 registers to kick the other processor or enquire status.
0269
0270 config SUN6I_MSGBOX
0271 tristate "Allwinner sun6i/sun8i/sun9i/sun50i Message Box"
0272 depends on ARCH_SUNXI || COMPILE_TEST
0273 default ARCH_SUNXI
0274 help
0275 Mailbox implementation for the hardware message box present in
0276 various Allwinner SoCs. This mailbox is used for communication
0277 between the application CPUs and the power management coprocessor.
0278
0279 config SPRD_MBOX
0280 tristate "Spreadtrum Mailbox"
0281 depends on ARCH_SPRD || COMPILE_TEST
0282 help
0283 Mailbox driver implementation for the Spreadtrum platform. It is used
0284 to send message between application processors and MCU. Say Y here if
0285 you want to build the Spreatrum mailbox controller driver.
0286
0287 config QCOM_IPCC
0288 tristate "Qualcomm Technologies, Inc. IPCC driver"
0289 depends on ARCH_QCOM || COMPILE_TEST
0290 help
0291 Qualcomm Technologies, Inc. Inter-Processor Communication Controller
0292 (IPCC) driver for MSM devices. The driver provides mailbox support for
0293 sending interrupts to the clients. On the other hand, the driver also
0294 acts as an interrupt controller for receiving interrupts from clients.
0295 Say Y here if you want to build this driver.
0296
0297 endif
