drivers/irqchip/qcom-pdc.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
0004  */
0005
0006 #include <linux/err.h>
0007 #include <linux/init.h>
0008 #include <linux/interrupt.h>
0009 #include <linux/irq.h>
0010 #include <linux/irqchip.h>
0011 #include <linux/irqdomain.h>
0012 #include <linux/io.h>
0013 #include <linux/kernel.h>
0014 #include <linux/module.h>
0015 #include <linux/of.h>
0016 #include <linux/of_address.h>
0017 #include <linux/of_device.h>
0018 #include <linux/of_irq.h>
0019 #include <linux/soc/qcom/irq.h>
0020 #include <linux/spinlock.h>
0021 #include <linux/slab.h>
0022 #include <linux/types.h>
0023
0024 #define PDC_MAX_GPIO_IRQS   256
0025
0026 #define IRQ_ENABLE_BANK     0x10
0027 #define IRQ_i_CFG       0x110
0028
0029 struct pdc_pin_region {
0030     u32 pin_base;
0031     u32 parent_base;
0032     u32 cnt;
0033 };
0034
0035 #define pin_to_hwirq(r, p)  ((r)->parent_base + (p) - (r)->pin_base)
0036
0037 static DEFINE_RAW_SPINLOCK(pdc_lock);
0038 static void __iomem *pdc_base;
0039 static struct pdc_pin_region *pdc_region;
0040 static int pdc_region_cnt;
0041
0042 static void pdc_reg_write(int reg, u32 i, u32 val)
0043 {
0044     writel_relaxed(val, pdc_base + reg + i * sizeof(u32));
0045 }
0046
0047 static u32 pdc_reg_read(int reg, u32 i)
0048 {
0049     return readl_relaxed(pdc_base + reg + i * sizeof(u32));
0050 }
0051
0052 static void pdc_enable_intr(struct irq_data *d, bool on)
0053 {
0054     int pin_out = d->hwirq;
0055     unsigned long enable;
0056     unsigned long flags;
0057     u32 index, mask;
0058
0059     index = pin_out / 32;
0060     mask = pin_out % 32;
0061
0062     raw_spin_lock_irqsave(&pdc_lock, flags);
0063     enable = pdc_reg_read(IRQ_ENABLE_BANK, index);
0064     __assign_bit(mask, &enable, on);
0065     pdc_reg_write(IRQ_ENABLE_BANK, index, enable);
0066     raw_spin_unlock_irqrestore(&pdc_lock, flags);
0067 }
0068
0069 static void qcom_pdc_gic_disable(struct irq_data *d)
0070 {
0071     pdc_enable_intr(d, false);
0072     irq_chip_disable_parent(d);
0073 }
0074
0075 static void qcom_pdc_gic_enable(struct irq_data *d)
0076 {
0077     pdc_enable_intr(d, true);
0078     irq_chip_enable_parent(d);
0079 }
0080
0081 /*
0082  * GIC does not handle falling edge or active low. To allow falling edge and
0083  * active low interrupts to be handled at GIC, PDC has an inverter that inverts
0084  * falling edge into a rising edge and active low into an active high.
0085  * For the inverter to work, the polarity bit in the IRQ_CONFIG register has to
0086  * set as per the table below.
0087  * Level sensitive active low    LOW
0088  * Rising edge sensitive         NOT USED
0089  * Falling edge sensitive        LOW
0090  * Dual Edge sensitive           NOT USED
0091  * Level sensitive active High   HIGH
0092  * Falling Edge sensitive        NOT USED
0093  * Rising edge sensitive         HIGH
0094  * Dual Edge sensitive           HIGH
0095  */
0096 enum pdc_irq_config_bits {
0097     PDC_LEVEL_LOW       = 0b000,
0098     PDC_EDGE_FALLING    = 0b010,
0099     PDC_LEVEL_HIGH      = 0b100,
0100     PDC_EDGE_RISING     = 0b110,
0101     PDC_EDGE_DUAL       = 0b111,
0102 };
0103
0104 /**
0105  * qcom_pdc_gic_set_type: Configure PDC for the interrupt
0106  *
0107  * @d: the interrupt data
0108  * @type: the interrupt type
0109  *
0110  * If @type is edge triggered, forward that as Rising edge as PDC
0111  * takes care of converting falling edge to rising edge signal
0112  * If @type is level, then forward that as level high as PDC
0113  * takes care of converting falling edge to rising edge signal
0114  */
0115 static int qcom_pdc_gic_set_type(struct irq_data *d, unsigned int type)
0116 {
0117     enum pdc_irq_config_bits pdc_type;
0118     enum pdc_irq_config_bits old_pdc_type;
0119     int ret;
0120
0121     switch (type) {
0122     case IRQ_TYPE_EDGE_RISING:
0123         pdc_type = PDC_EDGE_RISING;
0124         break;
0125     case IRQ_TYPE_EDGE_FALLING:
0126         pdc_type = PDC_EDGE_FALLING;
0127         type = IRQ_TYPE_EDGE_RISING;
0128         break;
0129     case IRQ_TYPE_EDGE_BOTH:
0130         pdc_type = PDC_EDGE_DUAL;
0131         type = IRQ_TYPE_EDGE_RISING;
0132         break;
0133     case IRQ_TYPE_LEVEL_HIGH:
0134         pdc_type = PDC_LEVEL_HIGH;
0135         break;
0136     case IRQ_TYPE_LEVEL_LOW:
0137         pdc_type = PDC_LEVEL_LOW;
0138         type = IRQ_TYPE_LEVEL_HIGH;
0139         break;
0140     default:
0141         WARN_ON(1);
0142         return -EINVAL;
0143     }
0144
0145     old_pdc_type = pdc_reg_read(IRQ_i_CFG, d->hwirq);
0146     pdc_reg_write(IRQ_i_CFG, d->hwirq, pdc_type);
0147
0148     ret = irq_chip_set_type_parent(d, type);
0149     if (ret)
0150         return ret;
0151
0152     /*
0153      * When we change types the PDC can give a phantom interrupt.
0154      * Clear it.  Specifically the phantom shows up when reconfiguring
0155      * polarity of interrupt without changing the state of the signal
0156      * but let's be consistent and clear it always.
0157      *
0158      * Doing this works because we have IRQCHIP_SET_TYPE_MASKED so the
0159      * interrupt will be cleared before the rest of the system sees it.
0160      */
0161     if (old_pdc_type != pdc_type)
0162         irq_chip_set_parent_state(d, IRQCHIP_STATE_PENDING, false);
0163
0164     return 0;
0165 }
0166
0167 static struct irq_chip qcom_pdc_gic_chip = {
0168     .name           = "PDC",
0169     .irq_eoi        = irq_chip_eoi_parent,
0170     .irq_mask       = irq_chip_mask_parent,
0171     .irq_unmask     = irq_chip_unmask_parent,
0172     .irq_disable        = qcom_pdc_gic_disable,
0173     .irq_enable     = qcom_pdc_gic_enable,
0174     .irq_get_irqchip_state  = irq_chip_get_parent_state,
0175     .irq_set_irqchip_state  = irq_chip_set_parent_state,
0176     .irq_retrigger      = irq_chip_retrigger_hierarchy,
0177     .irq_set_type       = qcom_pdc_gic_set_type,
0178     .flags          = IRQCHIP_MASK_ON_SUSPEND |
0179                   IRQCHIP_SET_TYPE_MASKED |
0180                   IRQCHIP_SKIP_SET_WAKE |
0181                   IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND,
0182     .irq_set_vcpu_affinity  = irq_chip_set_vcpu_affinity_parent,
0183     .irq_set_affinity   = irq_chip_set_affinity_parent,
0184 };
0185
0186 static struct pdc_pin_region *get_pin_region(int pin)
0187 {
0188     int i;
0189
0190     for (i = 0; i < pdc_region_cnt; i++) {
0191         if (pin >= pdc_region[i].pin_base &&
0192             pin < pdc_region[i].pin_base + pdc_region[i].cnt)
0193             return &pdc_region[i];
0194     }
0195
0196     return NULL;
0197 }
0198
0199 static int qcom_pdc_alloc(struct irq_domain *domain, unsigned int virq,
0200               unsigned int nr_irqs, void *data)
0201 {
0202     struct irq_fwspec *fwspec = data;
0203     struct irq_fwspec parent_fwspec;
0204     struct pdc_pin_region *region;
0205     irq_hw_number_t hwirq;
0206     unsigned int type;
0207     int ret;
0208
0209     ret = irq_domain_translate_twocell(domain, fwspec, &hwirq, &type);
0210     if (ret)
0211         return ret;
0212
0213     if (hwirq == GPIO_NO_WAKE_IRQ)
0214         return irq_domain_disconnect_hierarchy(domain, virq);
0215
0216     ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
0217                         &qcom_pdc_gic_chip, NULL);
0218     if (ret)
0219         return ret;
0220
0221     region = get_pin_region(hwirq);
0222     if (!region)
0223         return irq_domain_disconnect_hierarchy(domain->parent, virq);
0224
0225     if (type & IRQ_TYPE_EDGE_BOTH)
0226         type = IRQ_TYPE_EDGE_RISING;
0227
0228     if (type & IRQ_TYPE_LEVEL_MASK)
0229         type = IRQ_TYPE_LEVEL_HIGH;
0230
0231     parent_fwspec.fwnode      = domain->parent->fwnode;
0232     parent_fwspec.param_count = 3;
0233     parent_fwspec.param[0]    = 0;
0234     parent_fwspec.param[1]    = pin_to_hwirq(region, hwirq);
0235     parent_fwspec.param[2]    = type;
0236
0237     return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
0238                         &parent_fwspec);
0239 }
0240
0241 static const struct irq_domain_ops qcom_pdc_ops = {
0242     .translate  = irq_domain_translate_twocell,
0243     .alloc      = qcom_pdc_alloc,
0244     .free       = irq_domain_free_irqs_common,
0245 };
0246
0247 static int pdc_setup_pin_mapping(struct device_node *np)
0248 {
0249     int ret, n, i;
0250     u32 irq_index, reg_index, val;
0251
0252     n = of_property_count_elems_of_size(np, "qcom,pdc-ranges", sizeof(u32));
0253     if (n <= 0 || n % 3)
0254         return -EINVAL;
0255
0256     pdc_region_cnt = n / 3;
0257     pdc_region = kcalloc(pdc_region_cnt, sizeof(*pdc_region), GFP_KERNEL);
0258     if (!pdc_region) {
0259         pdc_region_cnt = 0;
0260         return -ENOMEM;
0261     }
0262
0263     for (n = 0; n < pdc_region_cnt; n++) {
0264         ret = of_property_read_u32_index(np, "qcom,pdc-ranges",
0265                          n * 3 + 0,
0266                          &pdc_region[n].pin_base);
0267         if (ret)
0268             return ret;
0269         ret = of_property_read_u32_index(np, "qcom,pdc-ranges",
0270                          n * 3 + 1,
0271                          &pdc_region[n].parent_base);
0272         if (ret)
0273             return ret;
0274         ret = of_property_read_u32_index(np, "qcom,pdc-ranges",
0275                          n * 3 + 2,
0276                          &pdc_region[n].cnt);
0277         if (ret)
0278             return ret;
0279
0280         for (i = 0; i < pdc_region[n].cnt; i++) {
0281             reg_index = (i + pdc_region[n].pin_base) >> 5;
0282             irq_index = (i + pdc_region[n].pin_base) & 0x1f;
0283             val = pdc_reg_read(IRQ_ENABLE_BANK, reg_index);
0284             val &= ~BIT(irq_index);
0285             pdc_reg_write(IRQ_ENABLE_BANK, reg_index, val);
0286         }
0287     }
0288
0289     return 0;
0290 }
0291
0292 static int qcom_pdc_init(struct device_node *node, struct device_node *parent)
0293 {
0294     struct irq_domain *parent_domain, *pdc_domain;
0295     int ret;
0296
0297     pdc_base = of_iomap(node, 0);
0298     if (!pdc_base) {
0299         pr_err("%pOF: unable to map PDC registers\n", node);
0300         return -ENXIO;
0301     }
0302
0303     parent_domain = irq_find_host(parent);
0304     if (!parent_domain) {
0305         pr_err("%pOF: unable to find PDC's parent domain\n", node);
0306         ret = -ENXIO;
0307         goto fail;
0308     }
0309
0310     ret = pdc_setup_pin_mapping(node);
0311     if (ret) {
0312         pr_err("%pOF: failed to init PDC pin-hwirq mapping\n", node);
0313         goto fail;
0314     }
0315
0316     pdc_domain = irq_domain_create_hierarchy(parent_domain,
0317                     IRQ_DOMAIN_FLAG_QCOM_PDC_WAKEUP,
0318                     PDC_MAX_GPIO_IRQS,
0319                     of_fwnode_handle(node),
0320                     &qcom_pdc_ops, NULL);
0321     if (!pdc_domain) {
0322         pr_err("%pOF: PDC domain add failed\n", node);
0323         ret = -ENOMEM;
0324         goto fail;
0325     }
0326
0327     irq_domain_update_bus_token(pdc_domain, DOMAIN_BUS_WAKEUP);
0328
0329     return 0;
0330
0331 fail:
0332     kfree(pdc_region);
0333     iounmap(pdc_base);
0334     return ret;
0335 }
0336
0337 IRQCHIP_PLATFORM_DRIVER_BEGIN(qcom_pdc)
0338 IRQCHIP_MATCH("qcom,pdc", qcom_pdc_init)
0339 IRQCHIP_PLATFORM_DRIVER_END(qcom_pdc)
0340 MODULE_DESCRIPTION("Qualcomm Technologies, Inc. Power Domain Controller");
0341 MODULE_LICENSE("GPL v2");