drivers/irqchip/irq-xtensa-mx.c

0001 /*
0002  * Xtensa MX interrupt distributor
0003  *
0004  * Copyright (C) 2002 - 2013 Tensilica, Inc.
0005  *
0006  * This file is subject to the terms and conditions of the GNU General Public
0007  * License.  See the file "COPYING" in the main directory of this archive
0008  * for more details.
0009  */
0010
0011 #include <linux/interrupt.h>
0012 #include <linux/irqdomain.h>
0013 #include <linux/irq.h>
0014 #include <linux/irqchip.h>
0015 #include <linux/of.h>
0016
0017 #include <asm/mxregs.h>
0018
0019 #define HW_IRQ_IPI_COUNT 2
0020 #define HW_IRQ_MX_BASE 2
0021 #define HW_IRQ_EXTERN_BASE 3
0022
0023 static DEFINE_PER_CPU(unsigned int, cached_irq_mask);
0024
0025 static int xtensa_mx_irq_map(struct irq_domain *d, unsigned int irq,
0026         irq_hw_number_t hw)
0027 {
0028     if (hw < HW_IRQ_IPI_COUNT) {
0029         struct irq_chip *irq_chip = d->host_data;
0030         irq_set_chip_and_handler_name(irq, irq_chip,
0031                 handle_percpu_irq, "ipi");
0032         irq_set_status_flags(irq, IRQ_LEVEL);
0033         return 0;
0034     }
0035     irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(irq)));
0036     return xtensa_irq_map(d, irq, hw);
0037 }
0038
0039 /*
0040  * Device Tree IRQ specifier translation function which works with one or
0041  * two cell bindings. First cell value maps directly to the hwirq number.
0042  * Second cell if present specifies whether hwirq number is external (1) or
0043  * internal (0).
0044  */
0045 static int xtensa_mx_irq_domain_xlate(struct irq_domain *d,
0046         struct device_node *ctrlr,
0047         const u32 *intspec, unsigned int intsize,
0048         unsigned long *out_hwirq, unsigned int *out_type)
0049 {
0050     return xtensa_irq_domain_xlate(intspec, intsize,
0051             intspec[0], intspec[0] + HW_IRQ_EXTERN_BASE,
0052             out_hwirq, out_type);
0053 }
0054
0055 static const struct irq_domain_ops xtensa_mx_irq_domain_ops = {
0056     .xlate = xtensa_mx_irq_domain_xlate,
0057     .map = xtensa_mx_irq_map,
0058 };
0059
0060 void secondary_init_irq(void)
0061 {
0062     __this_cpu_write(cached_irq_mask,
0063             XCHAL_INTTYPE_MASK_EXTERN_EDGE |
0064             XCHAL_INTTYPE_MASK_EXTERN_LEVEL);
0065     xtensa_set_sr(XCHAL_INTTYPE_MASK_EXTERN_EDGE |
0066             XCHAL_INTTYPE_MASK_EXTERN_LEVEL, intenable);
0067 }
0068
0069 static void xtensa_mx_irq_mask(struct irq_data *d)
0070 {
0071     unsigned int mask = 1u << d->hwirq;
0072
0073     if (mask & (XCHAL_INTTYPE_MASK_EXTERN_EDGE |
0074             XCHAL_INTTYPE_MASK_EXTERN_LEVEL)) {
0075         unsigned int ext_irq = xtensa_get_ext_irq_no(d->hwirq);
0076
0077         if (ext_irq >= HW_IRQ_MX_BASE) {
0078             set_er(1u << (ext_irq - HW_IRQ_MX_BASE), MIENG);
0079             return;
0080         }
0081     }
0082     mask = __this_cpu_read(cached_irq_mask) & ~mask;
0083     __this_cpu_write(cached_irq_mask, mask);
0084     xtensa_set_sr(mask, intenable);
0085 }
0086
0087 static void xtensa_mx_irq_unmask(struct irq_data *d)
0088 {
0089     unsigned int mask = 1u << d->hwirq;
0090
0091     if (mask & (XCHAL_INTTYPE_MASK_EXTERN_EDGE |
0092             XCHAL_INTTYPE_MASK_EXTERN_LEVEL)) {
0093         unsigned int ext_irq = xtensa_get_ext_irq_no(d->hwirq);
0094
0095         if (ext_irq >= HW_IRQ_MX_BASE) {
0096             set_er(1u << (ext_irq - HW_IRQ_MX_BASE), MIENGSET);
0097             return;
0098         }
0099     }
0100     mask |= __this_cpu_read(cached_irq_mask);
0101     __this_cpu_write(cached_irq_mask, mask);
0102     xtensa_set_sr(mask, intenable);
0103 }
0104
0105 static void xtensa_mx_irq_enable(struct irq_data *d)
0106 {
0107     xtensa_mx_irq_unmask(d);
0108 }
0109
0110 static void xtensa_mx_irq_disable(struct irq_data *d)
0111 {
0112     xtensa_mx_irq_mask(d);
0113 }
0114
0115 static void xtensa_mx_irq_ack(struct irq_data *d)
0116 {
0117     xtensa_set_sr(1 << d->hwirq, intclear);
0118 }
0119
0120 static int xtensa_mx_irq_retrigger(struct irq_data *d)
0121 {
0122     unsigned int mask = 1u << d->hwirq;
0123
0124     if (WARN_ON(mask & ~XCHAL_INTTYPE_MASK_SOFTWARE))
0125         return 0;
0126     xtensa_set_sr(mask, intset);
0127     return 1;
0128 }
0129
0130 static int xtensa_mx_irq_set_affinity(struct irq_data *d,
0131         const struct cpumask *dest, bool force)
0132 {
0133     int cpu = cpumask_any_and(dest, cpu_online_mask);
0134     unsigned mask = 1u << cpu;
0135
0136     set_er(mask, MIROUT(d->hwirq - HW_IRQ_MX_BASE));
0137     irq_data_update_effective_affinity(d, cpumask_of(cpu));
0138
0139     return 0;
0140
0141 }
0142
0143 static struct irq_chip xtensa_mx_irq_chip = {
0144     .name       = "xtensa-mx",
0145     .irq_enable = xtensa_mx_irq_enable,
0146     .irq_disable    = xtensa_mx_irq_disable,
0147     .irq_mask   = xtensa_mx_irq_mask,
0148     .irq_unmask = xtensa_mx_irq_unmask,
0149     .irq_ack    = xtensa_mx_irq_ack,
0150     .irq_retrigger  = xtensa_mx_irq_retrigger,
0151     .irq_set_affinity = xtensa_mx_irq_set_affinity,
0152 };
0153
0154 static void __init xtensa_mx_init_common(struct irq_domain *root_domain)
0155 {
0156     unsigned int i;
0157
0158     irq_set_default_host(root_domain);
0159     secondary_init_irq();
0160
0161     /* Initialize default IRQ routing to CPU 0 */
0162     for (i = 0; i < XCHAL_NUM_EXTINTERRUPTS; ++i)
0163         set_er(1, MIROUT(i));
0164 }
0165
0166 int __init xtensa_mx_init_legacy(struct device_node *interrupt_parent)
0167 {
0168     struct irq_domain *root_domain =
0169         irq_domain_add_legacy(NULL, NR_IRQS - 1, 1, 0,
0170                 &xtensa_mx_irq_domain_ops,
0171                 &xtensa_mx_irq_chip);
0172     xtensa_mx_init_common(root_domain);
0173     return 0;
0174 }
0175
0176 static int __init xtensa_mx_init(struct device_node *np,
0177         struct device_node *interrupt_parent)
0178 {
0179     struct irq_domain *root_domain =
0180         irq_domain_add_linear(np, NR_IRQS, &xtensa_mx_irq_domain_ops,
0181                 &xtensa_mx_irq_chip);
0182     xtensa_mx_init_common(root_domain);
0183     return 0;
0184 }
0185 IRQCHIP_DECLARE(xtensa_mx_irq_chip, "cdns,xtensa-mx", xtensa_mx_init);