drivers/irqchip/irq-xilinx-intc.c

0001 /*
0002  * Copyright (C) 2007-2013 Michal Simek <monstr@monstr.eu>
0003  * Copyright (C) 2012-2013 Xilinx, Inc.
0004  * Copyright (C) 2007-2009 PetaLogix
0005  * Copyright (C) 2006 Atmark Techno, Inc.
0006  *
0007  * This file is subject to the terms and conditions of the GNU General Public
0008  * License. See the file "COPYING" in the main directory of this archive
0009  * for more details.
0010  */
0011
0012 #include <linux/irqdomain.h>
0013 #include <linux/irq.h>
0014 #include <linux/irqchip.h>
0015 #include <linux/irqchip/chained_irq.h>
0016 #include <linux/of_address.h>
0017 #include <linux/io.h>
0018 #include <linux/jump_label.h>
0019 #include <linux/bug.h>
0020 #include <linux/of_irq.h>
0021
0022 /* No one else should require these constants, so define them locally here. */
0023 #define ISR 0x00            /* Interrupt Status Register */
0024 #define IPR 0x04            /* Interrupt Pending Register */
0025 #define IER 0x08            /* Interrupt Enable Register */
0026 #define IAR 0x0c            /* Interrupt Acknowledge Register */
0027 #define SIE 0x10            /* Set Interrupt Enable bits */
0028 #define CIE 0x14            /* Clear Interrupt Enable bits */
0029 #define IVR 0x18            /* Interrupt Vector Register */
0030 #define MER 0x1c            /* Master Enable Register */
0031
0032 #define MER_ME (1<<0)
0033 #define MER_HIE (1<<1)
0034
0035 #define SPURIOUS_IRQ    (-1U)
0036
0037 static DEFINE_STATIC_KEY_FALSE(xintc_is_be);
0038
0039 struct xintc_irq_chip {
0040     void        __iomem *base;
0041     struct      irq_domain *root_domain;
0042     u32     intr_mask;
0043     u32     nr_irq;
0044 };
0045
0046 static struct xintc_irq_chip *primary_intc;
0047
0048 static void xintc_write(struct xintc_irq_chip *irqc, int reg, u32 data)
0049 {
0050     if (static_branch_unlikely(&xintc_is_be))
0051         iowrite32be(data, irqc->base + reg);
0052     else
0053         iowrite32(data, irqc->base + reg);
0054 }
0055
0056 static u32 xintc_read(struct xintc_irq_chip *irqc, int reg)
0057 {
0058     if (static_branch_unlikely(&xintc_is_be))
0059         return ioread32be(irqc->base + reg);
0060     else
0061         return ioread32(irqc->base + reg);
0062 }
0063
0064 static void intc_enable_or_unmask(struct irq_data *d)
0065 {
0066     struct xintc_irq_chip *irqc = irq_data_get_irq_chip_data(d);
0067     unsigned long mask = BIT(d->hwirq);
0068
0069     pr_debug("irq-xilinx: enable_or_unmask: %ld\n", d->hwirq);
0070
0071     /* ack level irqs because they can't be acked during
0072      * ack function since the handle_level_irq function
0073      * acks the irq before calling the interrupt handler
0074      */
0075     if (irqd_is_level_type(d))
0076         xintc_write(irqc, IAR, mask);
0077
0078     xintc_write(irqc, SIE, mask);
0079 }
0080
0081 static void intc_disable_or_mask(struct irq_data *d)
0082 {
0083     struct xintc_irq_chip *irqc = irq_data_get_irq_chip_data(d);
0084
0085     pr_debug("irq-xilinx: disable: %ld\n", d->hwirq);
0086     xintc_write(irqc, CIE, BIT(d->hwirq));
0087 }
0088
0089 static void intc_ack(struct irq_data *d)
0090 {
0091     struct xintc_irq_chip *irqc = irq_data_get_irq_chip_data(d);
0092
0093     pr_debug("irq-xilinx: ack: %ld\n", d->hwirq);
0094     xintc_write(irqc, IAR, BIT(d->hwirq));
0095 }
0096
0097 static void intc_mask_ack(struct irq_data *d)
0098 {
0099     struct xintc_irq_chip *irqc = irq_data_get_irq_chip_data(d);
0100     unsigned long mask = BIT(d->hwirq);
0101
0102     pr_debug("irq-xilinx: disable_and_ack: %ld\n", d->hwirq);
0103     xintc_write(irqc, CIE, mask);
0104     xintc_write(irqc, IAR, mask);
0105 }
0106
0107 static struct irq_chip intc_dev = {
0108     .name = "Xilinx INTC",
0109     .irq_unmask = intc_enable_or_unmask,
0110     .irq_mask = intc_disable_or_mask,
0111     .irq_ack = intc_ack,
0112     .irq_mask_ack = intc_mask_ack,
0113 };
0114
0115 static int xintc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
0116 {
0117     struct xintc_irq_chip *irqc = d->host_data;
0118
0119     if (irqc->intr_mask & BIT(hw)) {
0120         irq_set_chip_and_handler_name(irq, &intc_dev,
0121                           handle_edge_irq, "edge");
0122         irq_clear_status_flags(irq, IRQ_LEVEL);
0123     } else {
0124         irq_set_chip_and_handler_name(irq, &intc_dev,
0125                           handle_level_irq, "level");
0126         irq_set_status_flags(irq, IRQ_LEVEL);
0127     }
0128     irq_set_chip_data(irq, irqc);
0129     return 0;
0130 }
0131
0132 static const struct irq_domain_ops xintc_irq_domain_ops = {
0133     .xlate = irq_domain_xlate_onetwocell,
0134     .map = xintc_map,
0135 };
0136
0137 static void xil_intc_irq_handler(struct irq_desc *desc)
0138 {
0139     struct irq_chip *chip = irq_desc_get_chip(desc);
0140     struct xintc_irq_chip *irqc;
0141
0142     irqc = irq_data_get_irq_handler_data(&desc->irq_data);
0143     chained_irq_enter(chip, desc);
0144     do {
0145         u32 hwirq = xintc_read(irqc, IVR);
0146
0147         if (hwirq == -1U)
0148             break;
0149
0150         generic_handle_domain_irq(irqc->root_domain, hwirq);
0151     } while (true);
0152     chained_irq_exit(chip, desc);
0153 }
0154
0155 static void xil_intc_handle_irq(struct pt_regs *regs)
0156 {
0157     u32 hwirq;
0158
0159     do {
0160         hwirq = xintc_read(primary_intc, IVR);
0161         if (unlikely(hwirq == SPURIOUS_IRQ))
0162             break;
0163
0164         generic_handle_domain_irq(primary_intc->root_domain, hwirq);
0165     } while (true);
0166 }
0167
0168 static int __init xilinx_intc_of_init(struct device_node *intc,
0169                          struct device_node *parent)
0170 {
0171     struct xintc_irq_chip *irqc;
0172     int ret, irq;
0173
0174     irqc = kzalloc(sizeof(*irqc), GFP_KERNEL);
0175     if (!irqc)
0176         return -ENOMEM;
0177     irqc->base = of_iomap(intc, 0);
0178     BUG_ON(!irqc->base);
0179
0180     ret = of_property_read_u32(intc, "xlnx,num-intr-inputs", &irqc->nr_irq);
0181     if (ret < 0) {
0182         pr_err("irq-xilinx: unable to read xlnx,num-intr-inputs\n");
0183         goto error;
0184     }
0185
0186     ret = of_property_read_u32(intc, "xlnx,kind-of-intr", &irqc->intr_mask);
0187     if (ret < 0) {
0188         pr_warn("irq-xilinx: unable to read xlnx,kind-of-intr\n");
0189         irqc->intr_mask = 0;
0190     }
0191
0192     if (irqc->intr_mask >> irqc->nr_irq)
0193         pr_warn("irq-xilinx: mismatch in kind-of-intr param\n");
0194
0195     pr_info("irq-xilinx: %pOF: num_irq=%d, edge=0x%x\n",
0196         intc, irqc->nr_irq, irqc->intr_mask);
0197
0198
0199     /*
0200      * Disable all external interrupts until they are
0201      * explicitly requested.
0202      */
0203     xintc_write(irqc, IER, 0);
0204
0205     /* Acknowledge any pending interrupts just in case. */
0206     xintc_write(irqc, IAR, 0xffffffff);
0207
0208     /* Turn on the Master Enable. */
0209     xintc_write(irqc, MER, MER_HIE | MER_ME);
0210     if (xintc_read(irqc, MER) != (MER_HIE | MER_ME)) {
0211         static_branch_enable(&xintc_is_be);
0212         xintc_write(irqc, MER, MER_HIE | MER_ME);
0213     }
0214
0215     irqc->root_domain = irq_domain_add_linear(intc, irqc->nr_irq,
0216                           &xintc_irq_domain_ops, irqc);
0217     if (!irqc->root_domain) {
0218         pr_err("irq-xilinx: Unable to create IRQ domain\n");
0219         ret = -EINVAL;
0220         goto error;
0221     }
0222
0223     if (parent) {
0224         irq = irq_of_parse_and_map(intc, 0);
0225         if (irq) {
0226             irq_set_chained_handler_and_data(irq,
0227                              xil_intc_irq_handler,
0228                              irqc);
0229         } else {
0230             pr_err("irq-xilinx: interrupts property not in DT\n");
0231             ret = -EINVAL;
0232             goto error;
0233         }
0234     } else {
0235         primary_intc = irqc;
0236         irq_set_default_host(primary_intc->root_domain);
0237         set_handle_irq(xil_intc_handle_irq);
0238     }
0239
0240     return 0;
0241
0242 error:
0243     iounmap(irqc->base);
0244     kfree(irqc);
0245     return ret;
0246
0247 }
0248
0249 IRQCHIP_DECLARE(xilinx_intc_xps, "xlnx,xps-intc-1.00.a", xilinx_intc_of_init);
0250 IRQCHIP_DECLARE(xilinx_intc_opb, "xlnx,opb-intc-1.00.c", xilinx_intc_of_init);