drivers/irqchip/irq-wpcm450-aic.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 // Copyright 2021 Jonathan Neuschäfer
0003
0004 #include <linux/irqchip.h>
0005 #include <linux/of_address.h>
0006 #include <linux/of_irq.h>
0007 #include <linux/printk.h>
0008
0009 #include <asm/exception.h>
0010
0011 #define AIC_SCR(x)  ((x)*4) /* Source control registers */
0012 #define AIC_GEN     0x84    /* Interrupt group enable control register */
0013 #define AIC_GRSR    0x88    /* Interrupt group raw status register */
0014 #define AIC_IRSR    0x100   /* Interrupt raw status register */
0015 #define AIC_IASR    0x104   /* Interrupt active status register */
0016 #define AIC_ISR     0x108   /* Interrupt status register */
0017 #define AIC_IPER    0x10c   /* Interrupt priority encoding register */
0018 #define AIC_ISNR    0x110   /* Interrupt source number register */
0019 #define AIC_IMR     0x114   /* Interrupt mask register */
0020 #define AIC_OISR    0x118   /* Output interrupt status register */
0021 #define AIC_MECR    0x120   /* Mask enable command register */
0022 #define AIC_MDCR    0x124   /* Mask disable command register */
0023 #define AIC_SSCR    0x128   /* Source set command register */
0024 #define AIC_SCCR    0x12c   /* Source clear command register */
0025 #define AIC_EOSCR   0x130   /* End of service command register */
0026
0027 #define AIC_SCR_SRCTYPE_LOW_LEVEL   (0 << 6)
0028 #define AIC_SCR_SRCTYPE_HIGH_LEVEL  (1 << 6)
0029 #define AIC_SCR_SRCTYPE_NEG_EDGE    (2 << 6)
0030 #define AIC_SCR_SRCTYPE_POS_EDGE    (3 << 6)
0031 #define AIC_SCR_PRIORITY(x)     (x)
0032 #define AIC_SCR_PRIORITY_MASK       0x7
0033
0034 #define AIC_NUM_IRQS        32
0035
0036 struct wpcm450_aic {
0037     void __iomem *regs;
0038     struct irq_domain *domain;
0039 };
0040
0041 static struct wpcm450_aic *aic;
0042
0043 static void wpcm450_aic_init_hw(void)
0044 {
0045     int i;
0046
0047     /* Disable (mask) all interrupts */
0048     writel(0xffffffff, aic->regs + AIC_MDCR);
0049
0050     /*
0051      * Make sure the interrupt controller is ready to serve new interrupts.
0052      * Reading from IPER indicates that the nIRQ signal may be deasserted,
0053      * and writing to EOSCR indicates that interrupt handling has finished.
0054      */
0055     readl(aic->regs + AIC_IPER);
0056     writel(0, aic->regs + AIC_EOSCR);
0057
0058     /* Initialize trigger mode and priority of each interrupt source */
0059     for (i = 0; i < AIC_NUM_IRQS; i++)
0060         writel(AIC_SCR_SRCTYPE_HIGH_LEVEL | AIC_SCR_PRIORITY(7),
0061                aic->regs + AIC_SCR(i));
0062 }
0063
0064 static void __exception_irq_entry wpcm450_aic_handle_irq(struct pt_regs *regs)
0065 {
0066     int hwirq;
0067
0068     /* Determine the interrupt source */
0069     /* Read IPER to signal that nIRQ can be de-asserted */
0070     hwirq = readl(aic->regs + AIC_IPER) / 4;
0071
0072     generic_handle_domain_irq(aic->domain, hwirq);
0073 }
0074
0075 static void wpcm450_aic_eoi(struct irq_data *d)
0076 {
0077     /* Signal end-of-service */
0078     writel(0, aic->regs + AIC_EOSCR);
0079 }
0080
0081 static void wpcm450_aic_mask(struct irq_data *d)
0082 {
0083     unsigned int mask = BIT(d->hwirq);
0084
0085     /* Disable (mask) the interrupt */
0086     writel(mask, aic->regs + AIC_MDCR);
0087 }
0088
0089 static void wpcm450_aic_unmask(struct irq_data *d)
0090 {
0091     unsigned int mask = BIT(d->hwirq);
0092
0093     /* Enable (unmask) the interrupt */
0094     writel(mask, aic->regs + AIC_MECR);
0095 }
0096
0097 static int wpcm450_aic_set_type(struct irq_data *d, unsigned int flow_type)
0098 {
0099     /*
0100      * The hardware supports high/low level, as well as rising/falling edge
0101      * modes, and the DT binding accommodates for that, but as long as
0102      * other modes than high level mode are not used and can't be tested,
0103      * they are rejected in this driver.
0104      */
0105     if ((flow_type & IRQ_TYPE_SENSE_MASK) != IRQ_TYPE_LEVEL_HIGH)
0106         return -EINVAL;
0107
0108     return 0;
0109 }
0110
0111 static struct irq_chip wpcm450_aic_chip = {
0112     .name = "wpcm450-aic",
0113     .irq_eoi = wpcm450_aic_eoi,
0114     .irq_mask = wpcm450_aic_mask,
0115     .irq_unmask = wpcm450_aic_unmask,
0116     .irq_set_type = wpcm450_aic_set_type,
0117 };
0118
0119 static int wpcm450_aic_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hwirq)
0120 {
0121     if (hwirq >= AIC_NUM_IRQS)
0122         return -EPERM;
0123
0124     irq_set_chip_and_handler(irq, &wpcm450_aic_chip, handle_fasteoi_irq);
0125     irq_set_chip_data(irq, aic);
0126     irq_set_probe(irq);
0127
0128     return 0;
0129 }
0130
0131 static const struct irq_domain_ops wpcm450_aic_ops = {
0132     .map = wpcm450_aic_map,
0133     .xlate = irq_domain_xlate_twocell,
0134 };
0135
0136 static int __init wpcm450_aic_of_init(struct device_node *node,
0137                       struct device_node *parent)
0138 {
0139     if (parent)
0140         return -EINVAL;
0141
0142     aic = kzalloc(sizeof(*aic), GFP_KERNEL);
0143     if (!aic)
0144         return -ENOMEM;
0145
0146     aic->regs = of_iomap(node, 0);
0147     if (!aic->regs) {
0148         pr_err("Failed to map WPCM450 AIC registers\n");
0149         return -ENOMEM;
0150     }
0151
0152     wpcm450_aic_init_hw();
0153
0154     set_handle_irq(wpcm450_aic_handle_irq);
0155
0156     aic->domain = irq_domain_add_linear(node, AIC_NUM_IRQS, &wpcm450_aic_ops, aic);
0157
0158     return 0;
0159 }
0160
0161 IRQCHIP_DECLARE(wpcm450_aic, "nuvoton,wpcm450-aic", wpcm450_aic_of_init);