drivers/irqchip/irq-vf610-mscm-ir.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2014-2015 Toradex AG
0004  * Author: Stefan Agner <stefan@agner.ch>
0005  *
0006  * IRQ chip driver for MSCM interrupt router available on Vybrid SoC's.
0007  * The interrupt router is between the CPU's interrupt controller and the
0008  * peripheral. The router allows to route the peripheral interrupts to
0009  * one of the two available CPU's on Vybrid VF6xx SoC's (Cortex-A5 or
0010  * Cortex-M4). The router will be configured transparently on a IRQ
0011  * request.
0012  *
0013  * o All peripheral interrupts of the Vybrid SoC can be routed to
0014  *   CPU 0, CPU 1 or both. The routing is useful for dual-core
0015  *   variants of Vybrid SoC such as VF6xx. This driver routes the
0016  *   requested interrupt to the CPU currently running on.
0017  *
0018  * o It is required to setup the interrupt router even on single-core
0019  *   variants of Vybrid.
0020  */
0021
0022 #include <linux/cpu_pm.h>
0023 #include <linux/io.h>
0024 #include <linux/irq.h>
0025 #include <linux/irqchip.h>
0026 #include <linux/irqdomain.h>
0027 #include <linux/mfd/syscon.h>
0028 #include <dt-bindings/interrupt-controller/arm-gic.h>
0029 #include <linux/of.h>
0030 #include <linux/of_address.h>
0031 #include <linux/slab.h>
0032 #include <linux/regmap.h>
0033
0034 #define MSCM_CPxNUM     0x4
0035
0036 #define MSCM_IRSPRC(n)      (0x80 + 2 * (n))
0037 #define MSCM_IRSPRC_CPEN_MASK   0x3
0038
0039 #define MSCM_IRSPRC_NUM     112
0040
0041 struct vf610_mscm_ir_chip_data {
0042     void __iomem *mscm_ir_base;
0043     u16 cpu_mask;
0044     u16 saved_irsprc[MSCM_IRSPRC_NUM];
0045     bool is_nvic;
0046 };
0047
0048 static struct vf610_mscm_ir_chip_data *mscm_ir_data;
0049
0050 static inline void vf610_mscm_ir_save(struct vf610_mscm_ir_chip_data *data)
0051 {
0052     int i;
0053
0054     for (i = 0; i < MSCM_IRSPRC_NUM; i++)
0055         data->saved_irsprc[i] = readw_relaxed(data->mscm_ir_base + MSCM_IRSPRC(i));
0056 }
0057
0058 static inline void vf610_mscm_ir_restore(struct vf610_mscm_ir_chip_data *data)
0059 {
0060     int i;
0061
0062     for (i = 0; i < MSCM_IRSPRC_NUM; i++)
0063         writew_relaxed(data->saved_irsprc[i], data->mscm_ir_base + MSCM_IRSPRC(i));
0064 }
0065
0066 static int vf610_mscm_ir_notifier(struct notifier_block *self,
0067                   unsigned long cmd, void *v)
0068 {
0069     switch (cmd) {
0070     case CPU_CLUSTER_PM_ENTER:
0071         vf610_mscm_ir_save(mscm_ir_data);
0072         break;
0073     case CPU_CLUSTER_PM_ENTER_FAILED:
0074     case CPU_CLUSTER_PM_EXIT:
0075         vf610_mscm_ir_restore(mscm_ir_data);
0076         break;
0077     }
0078
0079     return NOTIFY_OK;
0080 }
0081
0082 static struct notifier_block mscm_ir_notifier_block = {
0083     .notifier_call = vf610_mscm_ir_notifier,
0084 };
0085
0086 static void vf610_mscm_ir_enable(struct irq_data *data)
0087 {
0088     irq_hw_number_t hwirq = data->hwirq;
0089     struct vf610_mscm_ir_chip_data *chip_data = data->chip_data;
0090     u16 irsprc;
0091
0092     irsprc = readw_relaxed(chip_data->mscm_ir_base + MSCM_IRSPRC(hwirq));
0093     irsprc &= MSCM_IRSPRC_CPEN_MASK;
0094
0095     WARN_ON(irsprc & ~chip_data->cpu_mask);
0096
0097     writew_relaxed(chip_data->cpu_mask,
0098                chip_data->mscm_ir_base + MSCM_IRSPRC(hwirq));
0099
0100     irq_chip_enable_parent(data);
0101 }
0102
0103 static void vf610_mscm_ir_disable(struct irq_data *data)
0104 {
0105     irq_hw_number_t hwirq = data->hwirq;
0106     struct vf610_mscm_ir_chip_data *chip_data = data->chip_data;
0107
0108     writew_relaxed(0x0, chip_data->mscm_ir_base + MSCM_IRSPRC(hwirq));
0109
0110     irq_chip_disable_parent(data);
0111 }
0112
0113 static struct irq_chip vf610_mscm_ir_irq_chip = {
0114     .name           = "mscm-ir",
0115     .irq_mask       = irq_chip_mask_parent,
0116     .irq_unmask     = irq_chip_unmask_parent,
0117     .irq_eoi        = irq_chip_eoi_parent,
0118     .irq_enable     = vf610_mscm_ir_enable,
0119     .irq_disable        = vf610_mscm_ir_disable,
0120     .irq_retrigger      = irq_chip_retrigger_hierarchy,
0121     .irq_set_affinity   = irq_chip_set_affinity_parent,
0122 };
0123
0124 static int vf610_mscm_ir_domain_alloc(struct irq_domain *domain, unsigned int virq,
0125                       unsigned int nr_irqs, void *arg)
0126 {
0127     int i;
0128     irq_hw_number_t hwirq;
0129     struct irq_fwspec *fwspec = arg;
0130     struct irq_fwspec parent_fwspec;
0131
0132     if (!irq_domain_get_of_node(domain->parent))
0133         return -EINVAL;
0134
0135     if (fwspec->param_count != 2)
0136         return -EINVAL;
0137
0138     hwirq = fwspec->param[0];
0139     for (i = 0; i < nr_irqs; i++)
0140         irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
0141                           &vf610_mscm_ir_irq_chip,
0142                           domain->host_data);
0143
0144     parent_fwspec.fwnode = domain->parent->fwnode;
0145
0146     if (mscm_ir_data->is_nvic) {
0147         parent_fwspec.param_count = 1;
0148         parent_fwspec.param[0] = fwspec->param[0];
0149     } else {
0150         parent_fwspec.param_count = 3;
0151         parent_fwspec.param[0] = GIC_SPI;
0152         parent_fwspec.param[1] = fwspec->param[0];
0153         parent_fwspec.param[2] = fwspec->param[1];
0154     }
0155
0156     return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
0157                         &parent_fwspec);
0158 }
0159
0160 static int vf610_mscm_ir_domain_translate(struct irq_domain *d,
0161                       struct irq_fwspec *fwspec,
0162                       unsigned long *hwirq,
0163                       unsigned int *type)
0164 {
0165     if (WARN_ON(fwspec->param_count < 2))
0166         return -EINVAL;
0167     *hwirq = fwspec->param[0];
0168     *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
0169     return 0;
0170 }
0171
0172 static const struct irq_domain_ops mscm_irq_domain_ops = {
0173     .translate = vf610_mscm_ir_domain_translate,
0174     .alloc = vf610_mscm_ir_domain_alloc,
0175     .free = irq_domain_free_irqs_common,
0176 };
0177
0178 static int __init vf610_mscm_ir_of_init(struct device_node *node,
0179                    struct device_node *parent)
0180 {
0181     struct irq_domain *domain, *domain_parent;
0182     struct regmap *mscm_cp_regmap;
0183     int ret, cpuid;
0184
0185     domain_parent = irq_find_host(parent);
0186     if (!domain_parent) {
0187         pr_err("vf610_mscm_ir: interrupt-parent not found\n");
0188         return -EINVAL;
0189     }
0190
0191     mscm_ir_data = kzalloc(sizeof(*mscm_ir_data), GFP_KERNEL);
0192     if (!mscm_ir_data)
0193         return -ENOMEM;
0194
0195     mscm_ir_data->mscm_ir_base = of_io_request_and_map(node, 0, "mscm-ir");
0196     if (IS_ERR(mscm_ir_data->mscm_ir_base)) {
0197         pr_err("vf610_mscm_ir: unable to map mscm register\n");
0198         ret = PTR_ERR(mscm_ir_data->mscm_ir_base);
0199         goto out_free;
0200     }
0201
0202     mscm_cp_regmap = syscon_regmap_lookup_by_phandle(node, "fsl,cpucfg");
0203     if (IS_ERR(mscm_cp_regmap)) {
0204         ret = PTR_ERR(mscm_cp_regmap);
0205         pr_err("vf610_mscm_ir: regmap lookup for cpucfg failed\n");
0206         goto out_unmap;
0207     }
0208
0209     regmap_read(mscm_cp_regmap, MSCM_CPxNUM, &cpuid);
0210     mscm_ir_data->cpu_mask = 0x1 << cpuid;
0211
0212     domain = irq_domain_add_hierarchy(domain_parent, 0,
0213                       MSCM_IRSPRC_NUM, node,
0214                       &mscm_irq_domain_ops, mscm_ir_data);
0215     if (!domain) {
0216         ret = -ENOMEM;
0217         goto out_unmap;
0218     }
0219
0220     if (of_device_is_compatible(irq_domain_get_of_node(domain->parent),
0221                     "arm,armv7m-nvic"))
0222         mscm_ir_data->is_nvic = true;
0223
0224     cpu_pm_register_notifier(&mscm_ir_notifier_block);
0225
0226     return 0;
0227
0228 out_unmap:
0229     iounmap(mscm_ir_data->mscm_ir_base);
0230 out_free:
0231     kfree(mscm_ir_data);
0232     return ret;
0233 }
0234 IRQCHIP_DECLARE(vf610_mscm_ir, "fsl,vf610-mscm-ir", vf610_mscm_ir_of_init);