drivers/irqchip/irq-versatile-fpga.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  *  Support for Versatile FPGA-based IRQ controllers
0004  */
0005 #include <linux/bitops.h>
0006 #include <linux/irq.h>
0007 #include <linux/io.h>
0008 #include <linux/irqchip.h>
0009 #include <linux/irqchip/chained_irq.h>
0010 #include <linux/irqdomain.h>
0011 #include <linux/module.h>
0012 #include <linux/of.h>
0013 #include <linux/of_address.h>
0014 #include <linux/of_irq.h>
0015 #include <linux/seq_file.h>
0016
0017 #include <asm/exception.h>
0018 #include <asm/mach/irq.h>
0019
0020 #define IRQ_STATUS      0x00
0021 #define IRQ_RAW_STATUS      0x04
0022 #define IRQ_ENABLE_SET      0x08
0023 #define IRQ_ENABLE_CLEAR    0x0c
0024 #define INT_SOFT_SET        0x10
0025 #define INT_SOFT_CLEAR      0x14
0026 #define FIQ_STATUS      0x20
0027 #define FIQ_RAW_STATUS      0x24
0028 #define FIQ_ENABLE      0x28
0029 #define FIQ_ENABLE_SET      0x28
0030 #define FIQ_ENABLE_CLEAR    0x2C
0031
0032 #define PIC_ENABLES             0x20    /* set interrupt pass through bits */
0033
0034 /**
0035  * struct fpga_irq_data - irq data container for the FPGA IRQ controller
0036  * @base: memory offset in virtual memory
0037  * @domain: IRQ domain for this instance
0038  * @valid: mask for valid IRQs on this controller
0039  * @used_irqs: number of active IRQs on this controller
0040  */
0041 struct fpga_irq_data {
0042     void __iomem *base;
0043     u32 valid;
0044     struct irq_domain *domain;
0045     u8 used_irqs;
0046 };
0047
0048 /* we cannot allocate memory when the controllers are initially registered */
0049 static struct fpga_irq_data fpga_irq_devices[CONFIG_VERSATILE_FPGA_IRQ_NR];
0050 static int fpga_irq_id;
0051
0052 static void fpga_irq_mask(struct irq_data *d)
0053 {
0054     struct fpga_irq_data *f = irq_data_get_irq_chip_data(d);
0055     u32 mask = 1 << d->hwirq;
0056
0057     writel(mask, f->base + IRQ_ENABLE_CLEAR);
0058 }
0059
0060 static void fpga_irq_unmask(struct irq_data *d)
0061 {
0062     struct fpga_irq_data *f = irq_data_get_irq_chip_data(d);
0063     u32 mask = 1 << d->hwirq;
0064
0065     writel(mask, f->base + IRQ_ENABLE_SET);
0066 }
0067
0068 static void fpga_irq_print_chip(struct irq_data *d, struct seq_file *p)
0069 {
0070     struct fpga_irq_data *f = irq_data_get_irq_chip_data(d);
0071
0072     seq_printf(p, irq_domain_get_of_node(f->domain)->name);
0073 }
0074
0075 static const struct irq_chip fpga_chip = {
0076     .irq_ack    = fpga_irq_mask,
0077     .irq_mask   = fpga_irq_mask,
0078     .irq_unmask = fpga_irq_unmask,
0079     .irq_print_chip = fpga_irq_print_chip,
0080 };
0081
0082 static void fpga_irq_handle(struct irq_desc *desc)
0083 {
0084     struct irq_chip *chip = irq_desc_get_chip(desc);
0085     struct fpga_irq_data *f = irq_desc_get_handler_data(desc);
0086     u32 status;
0087
0088     chained_irq_enter(chip, desc);
0089
0090     status = readl(f->base + IRQ_STATUS);
0091     if (status == 0) {
0092         do_bad_IRQ(desc);
0093         goto out;
0094     }
0095
0096     do {
0097         unsigned int irq = ffs(status) - 1;
0098
0099         status &= ~(1 << irq);
0100         generic_handle_domain_irq(f->domain, irq);
0101     } while (status);
0102
0103 out:
0104     chained_irq_exit(chip, desc);
0105 }
0106
0107 /*
0108  * Handle each interrupt in a single FPGA IRQ controller.  Returns non-zero
0109  * if we've handled at least one interrupt.  This does a single read of the
0110  * status register and handles all interrupts in order from LSB first.
0111  */
0112 static int handle_one_fpga(struct fpga_irq_data *f, struct pt_regs *regs)
0113 {
0114     int handled = 0;
0115     int irq;
0116     u32 status;
0117
0118     while ((status  = readl(f->base + IRQ_STATUS))) {
0119         irq = ffs(status) - 1;
0120         generic_handle_domain_irq(f->domain, irq);
0121         handled = 1;
0122     }
0123
0124     return handled;
0125 }
0126
0127 /*
0128  * Keep iterating over all registered FPGA IRQ controllers until there are
0129  * no pending interrupts.
0130  */
0131 static asmlinkage void __exception_irq_entry fpga_handle_irq(struct pt_regs *regs)
0132 {
0133     int i, handled;
0134
0135     do {
0136         for (i = 0, handled = 0; i < fpga_irq_id; ++i)
0137             handled |= handle_one_fpga(&fpga_irq_devices[i], regs);
0138     } while (handled);
0139 }
0140
0141 static int fpga_irqdomain_map(struct irq_domain *d, unsigned int irq,
0142         irq_hw_number_t hwirq)
0143 {
0144     struct fpga_irq_data *f = d->host_data;
0145
0146     /* Skip invalid IRQs, only register handlers for the real ones */
0147     if (!(f->valid & BIT(hwirq)))
0148         return -EPERM;
0149     irq_set_chip_data(irq, f);
0150     irq_set_chip_and_handler(irq, &fpga_chip, handle_level_irq);
0151     irq_set_probe(irq);
0152     return 0;
0153 }
0154
0155 static const struct irq_domain_ops fpga_irqdomain_ops = {
0156     .map = fpga_irqdomain_map,
0157     .xlate = irq_domain_xlate_onetwocell,
0158 };
0159
0160 static void __init fpga_irq_init(void __iomem *base, int parent_irq,
0161                  u32 valid, struct device_node *node)
0162 {
0163     struct fpga_irq_data *f;
0164     int i;
0165
0166     if (fpga_irq_id >= ARRAY_SIZE(fpga_irq_devices)) {
0167         pr_err("%s: too few FPGA IRQ controllers, increase CONFIG_VERSATILE_FPGA_IRQ_NR\n", __func__);
0168         return;
0169     }
0170     f = &fpga_irq_devices[fpga_irq_id];
0171     f->base = base;
0172     f->valid = valid;
0173
0174     if (parent_irq != -1) {
0175         irq_set_chained_handler_and_data(parent_irq, fpga_irq_handle,
0176                          f);
0177     }
0178
0179     f->domain = irq_domain_add_linear(node, fls(valid),
0180                       &fpga_irqdomain_ops, f);
0181
0182     /* This will allocate all valid descriptors in the linear case */
0183     for (i = 0; i < fls(valid); i++)
0184         if (valid & BIT(i)) {
0185             /* Is this still required? */
0186             irq_create_mapping(f->domain, i);
0187             f->used_irqs++;
0188         }
0189
0190     pr_info("FPGA IRQ chip %d \"%s\" @ %p, %u irqs",
0191         fpga_irq_id, node->name, base, f->used_irqs);
0192     if (parent_irq != -1)
0193         pr_cont(", parent IRQ: %d\n", parent_irq);
0194     else
0195         pr_cont("\n");
0196
0197     fpga_irq_id++;
0198 }
0199
0200 #ifdef CONFIG_OF
0201 static int __init fpga_irq_of_init(struct device_node *node,
0202                    struct device_node *parent)
0203 {
0204     void __iomem *base;
0205     u32 clear_mask;
0206     u32 valid_mask;
0207     int parent_irq;
0208
0209     if (WARN_ON(!node))
0210         return -ENODEV;
0211
0212     base = of_iomap(node, 0);
0213     WARN(!base, "unable to map fpga irq registers\n");
0214
0215     if (of_property_read_u32(node, "clear-mask", &clear_mask))
0216         clear_mask = 0;
0217
0218     if (of_property_read_u32(node, "valid-mask", &valid_mask))
0219         valid_mask = 0;
0220
0221     writel(clear_mask, base + IRQ_ENABLE_CLEAR);
0222     writel(clear_mask, base + FIQ_ENABLE_CLEAR);
0223
0224     /* Some chips are cascaded from a parent IRQ */
0225     parent_irq = irq_of_parse_and_map(node, 0);
0226     if (!parent_irq) {
0227         set_handle_irq(fpga_handle_irq);
0228         parent_irq = -1;
0229     }
0230
0231     fpga_irq_init(base, parent_irq, valid_mask, node);
0232
0233     /*
0234      * On Versatile AB/PB, some secondary interrupts have a direct
0235      * pass-thru to the primary controller for IRQs 20 and 22-31 which need
0236      * to be enabled. See section 3.10 of the Versatile AB user guide.
0237      */
0238     if (of_device_is_compatible(node, "arm,versatile-sic"))
0239         writel(0xffd00000, base + PIC_ENABLES);
0240
0241     return 0;
0242 }
0243 IRQCHIP_DECLARE(arm_fpga, "arm,versatile-fpga-irq", fpga_irq_of_init);
0244 IRQCHIP_DECLARE(arm_fpga_sic, "arm,versatile-sic", fpga_irq_of_init);
0245 IRQCHIP_DECLARE(ox810se_rps, "oxsemi,ox810se-rps-irq", fpga_irq_of_init);
0246 #endif