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0010 #include <linux/interrupt.h>
0011 #include <linux/irqdomain.h>
0012 #include <linux/irq.h>
0013 #include <linux/irqchip.h>
0014 #include <linux/of_irq.h>
0015 #include <linux/of_address.h>
0016 #include <linux/of_platform.h>
0017 #include <linux/io.h>
0018 #include <linux/slab.h>
0019 #include <linux/bitops.h>
0020
0021 #define AB_IRQCTL_INT_ENABLE 0x00
0022 #define AB_IRQCTL_INT_STATUS 0x04
0023 #define AB_IRQCTL_SRC_MODE 0x08
0024 #define AB_IRQCTL_SRC_POLARITY 0x0C
0025 #define AB_IRQCTL_INT_MODE 0x10
0026 #define AB_IRQCTL_INT_POLARITY 0x14
0027 #define AB_IRQCTL_INT_FORCE 0x18
0028
0029 #define AB_IRQCTL_MAXIRQ 32
0030
0031 static inline void ab_irqctl_writereg(struct irq_chip_generic *gc, u32 reg,
0032 u32 val)
0033 {
0034 irq_reg_writel(gc, val, reg);
0035 }
0036
0037 static inline u32 ab_irqctl_readreg(struct irq_chip_generic *gc, u32 reg)
0038 {
0039 return irq_reg_readl(gc, reg);
0040 }
0041
0042 static int tb10x_irq_set_type(struct irq_data *data, unsigned int flow_type)
0043 {
0044 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
0045 uint32_t im, mod, pol;
0046
0047 im = data->mask;
0048
0049 irq_gc_lock(gc);
0050
0051 mod = ab_irqctl_readreg(gc, AB_IRQCTL_SRC_MODE) | im;
0052 pol = ab_irqctl_readreg(gc, AB_IRQCTL_SRC_POLARITY) | im;
0053
0054 switch (flow_type & IRQF_TRIGGER_MASK) {
0055 case IRQ_TYPE_EDGE_FALLING:
0056 pol ^= im;
0057 break;
0058 case IRQ_TYPE_LEVEL_HIGH:
0059 mod ^= im;
0060 break;
0061 case IRQ_TYPE_NONE:
0062 flow_type = IRQ_TYPE_LEVEL_LOW;
0063 fallthrough;
0064 case IRQ_TYPE_LEVEL_LOW:
0065 mod ^= im;
0066 pol ^= im;
0067 break;
0068 case IRQ_TYPE_EDGE_RISING:
0069 break;
0070 default:
0071 irq_gc_unlock(gc);
0072 pr_err("%s: Cannot assign multiple trigger modes to IRQ %d.\n",
0073 __func__, data->irq);
0074 return -EBADR;
0075 }
0076
0077 irqd_set_trigger_type(data, flow_type);
0078 irq_setup_alt_chip(data, flow_type);
0079
0080 ab_irqctl_writereg(gc, AB_IRQCTL_SRC_MODE, mod);
0081 ab_irqctl_writereg(gc, AB_IRQCTL_SRC_POLARITY, pol);
0082 ab_irqctl_writereg(gc, AB_IRQCTL_INT_STATUS, im);
0083
0084 irq_gc_unlock(gc);
0085
0086 return IRQ_SET_MASK_OK;
0087 }
0088
0089 static void tb10x_irq_cascade(struct irq_desc *desc)
0090 {
0091 struct irq_domain *domain = irq_desc_get_handler_data(desc);
0092 unsigned int irq = irq_desc_get_irq(desc);
0093
0094 generic_handle_domain_irq(domain, irq);
0095 }
0096
0097 static int __init of_tb10x_init_irq(struct device_node *ictl,
0098 struct device_node *parent)
0099 {
0100 int i, ret, nrirqs = of_irq_count(ictl);
0101 struct resource mem;
0102 struct irq_chip_generic *gc;
0103 struct irq_domain *domain;
0104 void __iomem *reg_base;
0105
0106 if (of_address_to_resource(ictl, 0, &mem)) {
0107 pr_err("%pOFn: No registers declared in DeviceTree.\n",
0108 ictl);
0109 return -EINVAL;
0110 }
0111
0112 if (!request_mem_region(mem.start, resource_size(&mem),
0113 ictl->full_name)) {
0114 pr_err("%pOFn: Request mem region failed.\n", ictl);
0115 return -EBUSY;
0116 }
0117
0118 reg_base = ioremap(mem.start, resource_size(&mem));
0119 if (!reg_base) {
0120 ret = -EBUSY;
0121 pr_err("%pOFn: ioremap failed.\n", ictl);
0122 goto ioremap_fail;
0123 }
0124
0125 domain = irq_domain_add_linear(ictl, AB_IRQCTL_MAXIRQ,
0126 &irq_generic_chip_ops, NULL);
0127 if (!domain) {
0128 ret = -ENOMEM;
0129 pr_err("%pOFn: Could not register interrupt domain.\n",
0130 ictl);
0131 goto irq_domain_add_fail;
0132 }
0133
0134 ret = irq_alloc_domain_generic_chips(domain, AB_IRQCTL_MAXIRQ,
0135 2, ictl->name, handle_level_irq,
0136 IRQ_NOREQUEST, IRQ_NOPROBE,
0137 IRQ_GC_INIT_MASK_CACHE);
0138 if (ret) {
0139 pr_err("%pOFn: Could not allocate generic interrupt chip.\n",
0140 ictl);
0141 goto gc_alloc_fail;
0142 }
0143
0144 gc = domain->gc->gc[0];
0145 gc->reg_base = reg_base;
0146
0147 gc->chip_types[0].type = IRQ_TYPE_LEVEL_MASK;
0148 gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
0149 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
0150 gc->chip_types[0].chip.irq_set_type = tb10x_irq_set_type;
0151 gc->chip_types[0].regs.mask = AB_IRQCTL_INT_ENABLE;
0152
0153 gc->chip_types[1].type = IRQ_TYPE_EDGE_BOTH;
0154 gc->chip_types[1].chip.name = gc->chip_types[0].chip.name;
0155 gc->chip_types[1].chip.irq_ack = irq_gc_ack_set_bit;
0156 gc->chip_types[1].chip.irq_mask = irq_gc_mask_clr_bit;
0157 gc->chip_types[1].chip.irq_unmask = irq_gc_mask_set_bit;
0158 gc->chip_types[1].chip.irq_set_type = tb10x_irq_set_type;
0159 gc->chip_types[1].regs.ack = AB_IRQCTL_INT_STATUS;
0160 gc->chip_types[1].regs.mask = AB_IRQCTL_INT_ENABLE;
0161 gc->chip_types[1].handler = handle_edge_irq;
0162
0163 for (i = 0; i < nrirqs; i++) {
0164 unsigned int irq = irq_of_parse_and_map(ictl, i);
0165
0166 irq_set_chained_handler_and_data(irq, tb10x_irq_cascade,
0167 domain);
0168 }
0169
0170 ab_irqctl_writereg(gc, AB_IRQCTL_INT_ENABLE, 0);
0171 ab_irqctl_writereg(gc, AB_IRQCTL_INT_MODE, 0);
0172 ab_irqctl_writereg(gc, AB_IRQCTL_INT_POLARITY, 0);
0173 ab_irqctl_writereg(gc, AB_IRQCTL_INT_STATUS, ~0UL);
0174
0175 return 0;
0176
0177 gc_alloc_fail:
0178 irq_domain_remove(domain);
0179 irq_domain_add_fail:
0180 iounmap(reg_base);
0181 ioremap_fail:
0182 release_mem_region(mem.start, resource_size(&mem));
0183 return ret;
0184 }
0185 IRQCHIP_DECLARE(tb10x_intc, "abilis,tb10x-ictl", of_tb10x_init_irq);
