drivers/irqchip/irq-sunxi-nmi.c

0001 /*
0002  * Allwinner A20/A31 SoCs NMI IRQ chip driver.
0003  *
0004  * Carlo Caione <carlo.caione@gmail.com>
0005  *
0006  * This file is licensed under the terms of the GNU General Public
0007  * License version 2.  This program is licensed "as is" without any
0008  * warranty of any kind, whether express or implied.
0009  */
0010
0011 #define DRV_NAME    "sunxi-nmi"
0012 #define pr_fmt(fmt) DRV_NAME ": " fmt
0013
0014 #include <linux/bitops.h>
0015 #include <linux/device.h>
0016 #include <linux/io.h>
0017 #include <linux/irq.h>
0018 #include <linux/interrupt.h>
0019 #include <linux/irqdomain.h>
0020 #include <linux/of_irq.h>
0021 #include <linux/of_address.h>
0022 #include <linux/of_platform.h>
0023 #include <linux/irqchip.h>
0024 #include <linux/irqchip/chained_irq.h>
0025
0026 #define SUNXI_NMI_SRC_TYPE_MASK 0x00000003
0027
0028 #define SUNXI_NMI_IRQ_BIT   BIT(0)
0029
0030 /*
0031  * For deprecated sun6i-a31-sc-nmi compatible.
0032  */
0033 #define SUN6I_NMI_CTRL      0x00
0034 #define SUN6I_NMI_PENDING   0x04
0035 #define SUN6I_NMI_ENABLE    0x34
0036
0037 #define SUN7I_NMI_CTRL      0x00
0038 #define SUN7I_NMI_PENDING   0x04
0039 #define SUN7I_NMI_ENABLE    0x08
0040
0041 #define SUN9I_NMI_CTRL      0x00
0042 #define SUN9I_NMI_ENABLE    0x04
0043 #define SUN9I_NMI_PENDING   0x08
0044
0045 enum {
0046     SUNXI_SRC_TYPE_LEVEL_LOW = 0,
0047     SUNXI_SRC_TYPE_EDGE_FALLING,
0048     SUNXI_SRC_TYPE_LEVEL_HIGH,
0049     SUNXI_SRC_TYPE_EDGE_RISING,
0050 };
0051
0052 struct sunxi_sc_nmi_reg_offs {
0053     u32 ctrl;
0054     u32 pend;
0055     u32 enable;
0056 };
0057
0058 static const struct sunxi_sc_nmi_reg_offs sun6i_reg_offs __initconst = {
0059     .ctrl   = SUN6I_NMI_CTRL,
0060     .pend   = SUN6I_NMI_PENDING,
0061     .enable = SUN6I_NMI_ENABLE,
0062 };
0063
0064 static const struct sunxi_sc_nmi_reg_offs sun7i_reg_offs __initconst = {
0065     .ctrl   = SUN7I_NMI_CTRL,
0066     .pend   = SUN7I_NMI_PENDING,
0067     .enable = SUN7I_NMI_ENABLE,
0068 };
0069
0070 static const struct sunxi_sc_nmi_reg_offs sun9i_reg_offs __initconst = {
0071     .ctrl   = SUN9I_NMI_CTRL,
0072     .pend   = SUN9I_NMI_PENDING,
0073     .enable = SUN9I_NMI_ENABLE,
0074 };
0075
0076 static inline void sunxi_sc_nmi_write(struct irq_chip_generic *gc, u32 off,
0077                       u32 val)
0078 {
0079     irq_reg_writel(gc, val, off);
0080 }
0081
0082 static inline u32 sunxi_sc_nmi_read(struct irq_chip_generic *gc, u32 off)
0083 {
0084     return irq_reg_readl(gc, off);
0085 }
0086
0087 static void sunxi_sc_nmi_handle_irq(struct irq_desc *desc)
0088 {
0089     struct irq_domain *domain = irq_desc_get_handler_data(desc);
0090     struct irq_chip *chip = irq_desc_get_chip(desc);
0091
0092     chained_irq_enter(chip, desc);
0093     generic_handle_domain_irq(domain, 0);
0094     chained_irq_exit(chip, desc);
0095 }
0096
0097 static int sunxi_sc_nmi_set_type(struct irq_data *data, unsigned int flow_type)
0098 {
0099     struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
0100     struct irq_chip_type *ct = gc->chip_types;
0101     u32 src_type_reg;
0102     u32 ctrl_off = ct->regs.type;
0103     unsigned int src_type;
0104     unsigned int i;
0105
0106     irq_gc_lock(gc);
0107
0108     switch (flow_type & IRQF_TRIGGER_MASK) {
0109     case IRQ_TYPE_EDGE_FALLING:
0110         src_type = SUNXI_SRC_TYPE_EDGE_FALLING;
0111         break;
0112     case IRQ_TYPE_EDGE_RISING:
0113         src_type = SUNXI_SRC_TYPE_EDGE_RISING;
0114         break;
0115     case IRQ_TYPE_LEVEL_HIGH:
0116         src_type = SUNXI_SRC_TYPE_LEVEL_HIGH;
0117         break;
0118     case IRQ_TYPE_NONE:
0119     case IRQ_TYPE_LEVEL_LOW:
0120         src_type = SUNXI_SRC_TYPE_LEVEL_LOW;
0121         break;
0122     default:
0123         irq_gc_unlock(gc);
0124         pr_err("Cannot assign multiple trigger modes to IRQ %d.\n",
0125             data->irq);
0126         return -EBADR;
0127     }
0128
0129     irqd_set_trigger_type(data, flow_type);
0130     irq_setup_alt_chip(data, flow_type);
0131
0132     for (i = 0; i < gc->num_ct; i++, ct++)
0133         if (ct->type & flow_type)
0134             ctrl_off = ct->regs.type;
0135
0136     src_type_reg = sunxi_sc_nmi_read(gc, ctrl_off);
0137     src_type_reg &= ~SUNXI_NMI_SRC_TYPE_MASK;
0138     src_type_reg |= src_type;
0139     sunxi_sc_nmi_write(gc, ctrl_off, src_type_reg);
0140
0141     irq_gc_unlock(gc);
0142
0143     return IRQ_SET_MASK_OK;
0144 }
0145
0146 static int __init sunxi_sc_nmi_irq_init(struct device_node *node,
0147                     const struct sunxi_sc_nmi_reg_offs *reg_offs)
0148 {
0149     struct irq_domain *domain;
0150     struct irq_chip_generic *gc;
0151     unsigned int irq;
0152     unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
0153     int ret;
0154
0155
0156     domain = irq_domain_add_linear(node, 1, &irq_generic_chip_ops, NULL);
0157     if (!domain) {
0158         pr_err("Could not register interrupt domain.\n");
0159         return -ENOMEM;
0160     }
0161
0162     ret = irq_alloc_domain_generic_chips(domain, 1, 2, DRV_NAME,
0163                          handle_fasteoi_irq, clr, 0,
0164                          IRQ_GC_INIT_MASK_CACHE);
0165     if (ret) {
0166         pr_err("Could not allocate generic interrupt chip.\n");
0167         goto fail_irqd_remove;
0168     }
0169
0170     irq = irq_of_parse_and_map(node, 0);
0171     if (irq <= 0) {
0172         pr_err("unable to parse irq\n");
0173         ret = -EINVAL;
0174         goto fail_irqd_remove;
0175     }
0176
0177     gc = irq_get_domain_generic_chip(domain, 0);
0178     gc->reg_base = of_io_request_and_map(node, 0, of_node_full_name(node));
0179     if (IS_ERR(gc->reg_base)) {
0180         pr_err("unable to map resource\n");
0181         ret = PTR_ERR(gc->reg_base);
0182         goto fail_irqd_remove;
0183     }
0184
0185     gc->chip_types[0].type          = IRQ_TYPE_LEVEL_MASK;
0186     gc->chip_types[0].chip.irq_mask     = irq_gc_mask_clr_bit;
0187     gc->chip_types[0].chip.irq_unmask   = irq_gc_mask_set_bit;
0188     gc->chip_types[0].chip.irq_eoi      = irq_gc_ack_set_bit;
0189     gc->chip_types[0].chip.irq_set_type = sunxi_sc_nmi_set_type;
0190     gc->chip_types[0].chip.flags        = IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED;
0191     gc->chip_types[0].regs.ack      = reg_offs->pend;
0192     gc->chip_types[0].regs.mask     = reg_offs->enable;
0193     gc->chip_types[0].regs.type     = reg_offs->ctrl;
0194
0195     gc->chip_types[1].type          = IRQ_TYPE_EDGE_BOTH;
0196     gc->chip_types[1].chip.name     = gc->chip_types[0].chip.name;
0197     gc->chip_types[1].chip.irq_ack      = irq_gc_ack_set_bit;
0198     gc->chip_types[1].chip.irq_mask     = irq_gc_mask_clr_bit;
0199     gc->chip_types[1].chip.irq_unmask   = irq_gc_mask_set_bit;
0200     gc->chip_types[1].chip.irq_set_type = sunxi_sc_nmi_set_type;
0201     gc->chip_types[1].regs.ack      = reg_offs->pend;
0202     gc->chip_types[1].regs.mask     = reg_offs->enable;
0203     gc->chip_types[1].regs.type     = reg_offs->ctrl;
0204     gc->chip_types[1].handler       = handle_edge_irq;
0205
0206     /* Disable any active interrupts */
0207     sunxi_sc_nmi_write(gc, reg_offs->enable, 0);
0208
0209     /* Clear any pending NMI interrupts */
0210     sunxi_sc_nmi_write(gc, reg_offs->pend, SUNXI_NMI_IRQ_BIT);
0211
0212     irq_set_chained_handler_and_data(irq, sunxi_sc_nmi_handle_irq, domain);
0213
0214     return 0;
0215
0216 fail_irqd_remove:
0217     irq_domain_remove(domain);
0218
0219     return ret;
0220 }
0221
0222 static int __init sun6i_sc_nmi_irq_init(struct device_node *node,
0223                     struct device_node *parent)
0224 {
0225     return sunxi_sc_nmi_irq_init(node, &sun6i_reg_offs);
0226 }
0227 IRQCHIP_DECLARE(sun6i_sc_nmi, "allwinner,sun6i-a31-sc-nmi", sun6i_sc_nmi_irq_init);
0228
0229 static int __init sun7i_sc_nmi_irq_init(struct device_node *node,
0230                     struct device_node *parent)
0231 {
0232     return sunxi_sc_nmi_irq_init(node, &sun7i_reg_offs);
0233 }
0234 IRQCHIP_DECLARE(sun7i_sc_nmi, "allwinner,sun7i-a20-sc-nmi", sun7i_sc_nmi_irq_init);
0235
0236 static int __init sun9i_nmi_irq_init(struct device_node *node,
0237                      struct device_node *parent)
0238 {
0239     return sunxi_sc_nmi_irq_init(node, &sun9i_reg_offs);
0240 }
0241 IRQCHIP_DECLARE(sun9i_nmi, "allwinner,sun9i-a80-nmi", sun9i_nmi_irq_init);