drivers/irqchip/irq-renesas-rza1.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Renesas RZ/A1 IRQC Driver
0004  *
0005  * Copyright (C) 2019 Glider bvba
0006  */
0007
0008 #include <linux/err.h>
0009 #include <linux/init.h>
0010 #include <linux/interrupt.h>
0011 #include <linux/io.h>
0012 #include <linux/irqdomain.h>
0013 #include <linux/irq.h>
0014 #include <linux/module.h>
0015 #include <linux/of_irq.h>
0016 #include <linux/platform_device.h>
0017 #include <linux/slab.h>
0018
0019 #include <dt-bindings/interrupt-controller/arm-gic.h>
0020
0021 #define IRQC_NUM_IRQ        8
0022
0023 #define ICR0            0   /* Interrupt Control Register 0 */
0024
0025 #define ICR0_NMIL       BIT(15) /* NMI Input Level (0=low, 1=high) */
0026 #define ICR0_NMIE       BIT(8)  /* Edge Select (0=falling, 1=rising) */
0027 #define ICR0_NMIF       BIT(1)  /* NMI Interrupt Request */
0028
0029 #define ICR1            2   /* Interrupt Control Register 1 */
0030
0031 #define ICR1_IRQS(n, sense) ((sense) << ((n) * 2))  /* IRQ Sense Select */
0032 #define ICR1_IRQS_LEVEL_LOW 0
0033 #define ICR1_IRQS_EDGE_FALLING  1
0034 #define ICR1_IRQS_EDGE_RISING   2
0035 #define ICR1_IRQS_EDGE_BOTH 3
0036 #define ICR1_IRQS_MASK(n)   ICR1_IRQS((n), 3)
0037
0038 #define IRQRR           4   /* IRQ Interrupt Request Register */
0039
0040
0041 struct rza1_irqc_priv {
0042     struct device *dev;
0043     void __iomem *base;
0044     struct irq_chip chip;
0045     struct irq_domain *irq_domain;
0046     struct of_phandle_args map[IRQC_NUM_IRQ];
0047 };
0048
0049 static struct rza1_irqc_priv *irq_data_to_priv(struct irq_data *data)
0050 {
0051     return data->domain->host_data;
0052 }
0053
0054 static void rza1_irqc_eoi(struct irq_data *d)
0055 {
0056     struct rza1_irqc_priv *priv = irq_data_to_priv(d);
0057     u16 bit = BIT(irqd_to_hwirq(d));
0058     u16 tmp;
0059
0060     tmp = readw_relaxed(priv->base + IRQRR);
0061     if (tmp & bit)
0062         writew_relaxed(GENMASK(IRQC_NUM_IRQ - 1, 0) & ~bit,
0063                    priv->base + IRQRR);
0064
0065     irq_chip_eoi_parent(d);
0066 }
0067
0068 static int rza1_irqc_set_type(struct irq_data *d, unsigned int type)
0069 {
0070     struct rza1_irqc_priv *priv = irq_data_to_priv(d);
0071     unsigned int hw_irq = irqd_to_hwirq(d);
0072     u16 sense, tmp;
0073
0074     switch (type & IRQ_TYPE_SENSE_MASK) {
0075     case IRQ_TYPE_LEVEL_LOW:
0076         sense = ICR1_IRQS_LEVEL_LOW;
0077         break;
0078
0079     case IRQ_TYPE_EDGE_FALLING:
0080         sense = ICR1_IRQS_EDGE_FALLING;
0081         break;
0082
0083     case IRQ_TYPE_EDGE_RISING:
0084         sense = ICR1_IRQS_EDGE_RISING;
0085         break;
0086
0087     case IRQ_TYPE_EDGE_BOTH:
0088         sense = ICR1_IRQS_EDGE_BOTH;
0089         break;
0090
0091     default:
0092         return -EINVAL;
0093     }
0094
0095     tmp = readw_relaxed(priv->base + ICR1);
0096     tmp &= ~ICR1_IRQS_MASK(hw_irq);
0097     tmp |= ICR1_IRQS(hw_irq, sense);
0098     writew_relaxed(tmp, priv->base + ICR1);
0099     return 0;
0100 }
0101
0102 static int rza1_irqc_alloc(struct irq_domain *domain, unsigned int virq,
0103                unsigned int nr_irqs, void *arg)
0104 {
0105     struct rza1_irqc_priv *priv = domain->host_data;
0106     struct irq_fwspec *fwspec = arg;
0107     unsigned int hwirq = fwspec->param[0];
0108     struct irq_fwspec spec;
0109     unsigned int i;
0110     int ret;
0111
0112     ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, &priv->chip,
0113                         priv);
0114     if (ret)
0115         return ret;
0116
0117     spec.fwnode = &priv->dev->of_node->fwnode;
0118     spec.param_count = priv->map[hwirq].args_count;
0119     for (i = 0; i < spec.param_count; i++)
0120         spec.param[i] = priv->map[hwirq].args[i];
0121
0122     return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &spec);
0123 }
0124
0125 static int rza1_irqc_translate(struct irq_domain *domain,
0126                    struct irq_fwspec *fwspec, unsigned long *hwirq,
0127                    unsigned int *type)
0128 {
0129     if (fwspec->param_count != 2 || fwspec->param[0] >= IRQC_NUM_IRQ)
0130         return -EINVAL;
0131
0132     *hwirq = fwspec->param[0];
0133     *type = fwspec->param[1];
0134     return 0;
0135 }
0136
0137 static const struct irq_domain_ops rza1_irqc_domain_ops = {
0138     .alloc = rza1_irqc_alloc,
0139     .translate = rza1_irqc_translate,
0140 };
0141
0142 static int rza1_irqc_parse_map(struct rza1_irqc_priv *priv,
0143                    struct device_node *gic_node)
0144 {
0145     unsigned int imaplen, i, j, ret;
0146     struct device *dev = priv->dev;
0147     struct device_node *ipar;
0148     const __be32 *imap;
0149     u32 intsize;
0150
0151     imap = of_get_property(dev->of_node, "interrupt-map", &imaplen);
0152     if (!imap)
0153         return -EINVAL;
0154
0155     for (i = 0; i < IRQC_NUM_IRQ; i++) {
0156         if (imaplen < 3)
0157             return -EINVAL;
0158
0159         /* Check interrupt number, ignore sense */
0160         if (be32_to_cpup(imap) != i)
0161             return -EINVAL;
0162
0163         ipar = of_find_node_by_phandle(be32_to_cpup(imap + 2));
0164         if (ipar != gic_node) {
0165             of_node_put(ipar);
0166             return -EINVAL;
0167         }
0168
0169         imap += 3;
0170         imaplen -= 3;
0171
0172         ret = of_property_read_u32(ipar, "#interrupt-cells", &intsize);
0173         of_node_put(ipar);
0174         if (ret)
0175             return ret;
0176
0177         if (imaplen < intsize)
0178             return -EINVAL;
0179
0180         priv->map[i].args_count = intsize;
0181         for (j = 0; j < intsize; j++)
0182             priv->map[i].args[j] = be32_to_cpup(imap++);
0183
0184         imaplen -= intsize;
0185     }
0186
0187     return 0;
0188 }
0189
0190 static int rza1_irqc_probe(struct platform_device *pdev)
0191 {
0192     struct device *dev = &pdev->dev;
0193     struct device_node *np = dev->of_node;
0194     struct irq_domain *parent = NULL;
0195     struct device_node *gic_node;
0196     struct rza1_irqc_priv *priv;
0197     int ret;
0198
0199     priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
0200     if (!priv)
0201         return -ENOMEM;
0202
0203     platform_set_drvdata(pdev, priv);
0204     priv->dev = dev;
0205
0206     priv->base = devm_platform_ioremap_resource(pdev, 0);
0207     if (IS_ERR(priv->base))
0208         return PTR_ERR(priv->base);
0209
0210     gic_node = of_irq_find_parent(np);
0211     if (gic_node)
0212         parent = irq_find_host(gic_node);
0213
0214     if (!parent) {
0215         dev_err(dev, "cannot find parent domain\n");
0216         ret = -ENODEV;
0217         goto out_put_node;
0218     }
0219
0220     ret = rza1_irqc_parse_map(priv, gic_node);
0221     if (ret) {
0222         dev_err(dev, "cannot parse %s: %d\n", "interrupt-map", ret);
0223         goto out_put_node;
0224     }
0225
0226     priv->chip.name = "rza1-irqc";
0227     priv->chip.irq_mask = irq_chip_mask_parent;
0228     priv->chip.irq_unmask = irq_chip_unmask_parent;
0229     priv->chip.irq_eoi = rza1_irqc_eoi;
0230     priv->chip.irq_retrigger = irq_chip_retrigger_hierarchy;
0231     priv->chip.irq_set_type = rza1_irqc_set_type;
0232     priv->chip.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE;
0233
0234     priv->irq_domain = irq_domain_add_hierarchy(parent, 0, IRQC_NUM_IRQ,
0235                             np, &rza1_irqc_domain_ops,
0236                             priv);
0237     if (!priv->irq_domain) {
0238         dev_err(dev, "cannot initialize irq domain\n");
0239         ret = -ENOMEM;
0240     }
0241
0242 out_put_node:
0243     of_node_put(gic_node);
0244     return ret;
0245 }
0246
0247 static int rza1_irqc_remove(struct platform_device *pdev)
0248 {
0249     struct rza1_irqc_priv *priv = platform_get_drvdata(pdev);
0250
0251     irq_domain_remove(priv->irq_domain);
0252     return 0;
0253 }
0254
0255 static const struct of_device_id rza1_irqc_dt_ids[] = {
0256     { .compatible = "renesas,rza1-irqc" },
0257     {},
0258 };
0259 MODULE_DEVICE_TABLE(of, rza1_irqc_dt_ids);
0260
0261 static struct platform_driver rza1_irqc_device_driver = {
0262     .probe      = rza1_irqc_probe,
0263     .remove     = rza1_irqc_remove,
0264     .driver     = {
0265         .name   = "renesas_rza1_irqc",
0266         .of_match_table = rza1_irqc_dt_ids,
0267     }
0268 };
0269
0270 static int __init rza1_irqc_init(void)
0271 {
0272     return platform_driver_register(&rza1_irqc_device_driver);
0273 }
0274 postcore_initcall(rza1_irqc_init);
0275
0276 static void __exit rza1_irqc_exit(void)
0277 {
0278     platform_driver_unregister(&rza1_irqc_device_driver);
0279 }
0280 module_exit(rza1_irqc_exit);
0281
0282 MODULE_AUTHOR("Geert Uytterhoeven <geert+renesas@glider.be>");
0283 MODULE_DESCRIPTION("Renesas RZ/A1 IRQC Driver");
0284 MODULE_LICENSE("GPL v2");