drivers/irqchip/irq-renesas-intc-irqpin.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Renesas INTC External IRQ Pin Driver
0004  *
0005  *  Copyright (C) 2013 Magnus Damm
0006  */
0007
0008 #include <linux/init.h>
0009 #include <linux/of.h>
0010 #include <linux/platform_device.h>
0011 #include <linux/spinlock.h>
0012 #include <linux/interrupt.h>
0013 #include <linux/ioport.h>
0014 #include <linux/io.h>
0015 #include <linux/irq.h>
0016 #include <linux/irqdomain.h>
0017 #include <linux/err.h>
0018 #include <linux/slab.h>
0019 #include <linux/module.h>
0020 #include <linux/of_device.h>
0021 #include <linux/pm_runtime.h>
0022
0023 #define INTC_IRQPIN_MAX 8 /* maximum 8 interrupts per driver instance */
0024
0025 #define INTC_IRQPIN_REG_SENSE 0 /* ICRn */
0026 #define INTC_IRQPIN_REG_PRIO 1 /* INTPRInn */
0027 #define INTC_IRQPIN_REG_SOURCE 2 /* INTREQnn */
0028 #define INTC_IRQPIN_REG_MASK 3 /* INTMSKnn */
0029 #define INTC_IRQPIN_REG_CLEAR 4 /* INTMSKCLRnn */
0030 #define INTC_IRQPIN_REG_NR_MANDATORY 5
0031 #define INTC_IRQPIN_REG_IRLM 5 /* ICR0 with IRLM bit (optional) */
0032 #define INTC_IRQPIN_REG_NR 6
0033
0034 /* INTC external IRQ PIN hardware register access:
0035  *
0036  * SENSE is read-write 32-bit with 2-bits or 4-bits per IRQ (*)
0037  * PRIO is read-write 32-bit with 4-bits per IRQ (**)
0038  * SOURCE is read-only 32-bit or 8-bit with 1-bit per IRQ (***)
0039  * MASK is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
0040  * CLEAR is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
0041  *
0042  * (*) May be accessed by more than one driver instance - lock needed
0043  * (**) Read-modify-write access by one driver instance - lock needed
0044  * (***) Accessed by one driver instance only - no locking needed
0045  */
0046
0047 struct intc_irqpin_iomem {
0048     void __iomem *iomem;
0049     unsigned long (*read)(void __iomem *iomem);
0050     void (*write)(void __iomem *iomem, unsigned long data);
0051     int width;
0052 };
0053
0054 struct intc_irqpin_irq {
0055     int hw_irq;
0056     int requested_irq;
0057     int domain_irq;
0058     struct intc_irqpin_priv *p;
0059 };
0060
0061 struct intc_irqpin_priv {
0062     struct intc_irqpin_iomem iomem[INTC_IRQPIN_REG_NR];
0063     struct intc_irqpin_irq irq[INTC_IRQPIN_MAX];
0064     unsigned int sense_bitfield_width;
0065     struct platform_device *pdev;
0066     struct irq_chip irq_chip;
0067     struct irq_domain *irq_domain;
0068     atomic_t wakeup_path;
0069     unsigned shared_irqs:1;
0070     u8 shared_irq_mask;
0071 };
0072
0073 struct intc_irqpin_config {
0074     int irlm_bit;       /* -1 if non-existent */
0075 };
0076
0077 static unsigned long intc_irqpin_read32(void __iomem *iomem)
0078 {
0079     return ioread32(iomem);
0080 }
0081
0082 static unsigned long intc_irqpin_read8(void __iomem *iomem)
0083 {
0084     return ioread8(iomem);
0085 }
0086
0087 static void intc_irqpin_write32(void __iomem *iomem, unsigned long data)
0088 {
0089     iowrite32(data, iomem);
0090 }
0091
0092 static void intc_irqpin_write8(void __iomem *iomem, unsigned long data)
0093 {
0094     iowrite8(data, iomem);
0095 }
0096
0097 static inline unsigned long intc_irqpin_read(struct intc_irqpin_priv *p,
0098                          int reg)
0099 {
0100     struct intc_irqpin_iomem *i = &p->iomem[reg];
0101
0102     return i->read(i->iomem);
0103 }
0104
0105 static inline void intc_irqpin_write(struct intc_irqpin_priv *p,
0106                      int reg, unsigned long data)
0107 {
0108     struct intc_irqpin_iomem *i = &p->iomem[reg];
0109
0110     i->write(i->iomem, data);
0111 }
0112
0113 static inline unsigned long intc_irqpin_hwirq_mask(struct intc_irqpin_priv *p,
0114                            int reg, int hw_irq)
0115 {
0116     return BIT((p->iomem[reg].width - 1) - hw_irq);
0117 }
0118
0119 static inline void intc_irqpin_irq_write_hwirq(struct intc_irqpin_priv *p,
0120                            int reg, int hw_irq)
0121 {
0122     intc_irqpin_write(p, reg, intc_irqpin_hwirq_mask(p, reg, hw_irq));
0123 }
0124
0125 static DEFINE_RAW_SPINLOCK(intc_irqpin_lock); /* only used by slow path */
0126
0127 static void intc_irqpin_read_modify_write(struct intc_irqpin_priv *p,
0128                       int reg, int shift,
0129                       int width, int value)
0130 {
0131     unsigned long flags;
0132     unsigned long tmp;
0133
0134     raw_spin_lock_irqsave(&intc_irqpin_lock, flags);
0135
0136     tmp = intc_irqpin_read(p, reg);
0137     tmp &= ~(((1 << width) - 1) << shift);
0138     tmp |= value << shift;
0139     intc_irqpin_write(p, reg, tmp);
0140
0141     raw_spin_unlock_irqrestore(&intc_irqpin_lock, flags);
0142 }
0143
0144 static void intc_irqpin_mask_unmask_prio(struct intc_irqpin_priv *p,
0145                      int irq, int do_mask)
0146 {
0147     /* The PRIO register is assumed to be 32-bit with fixed 4-bit fields. */
0148     int bitfield_width = 4;
0149     int shift = 32 - (irq + 1) * bitfield_width;
0150
0151     intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_PRIO,
0152                       shift, bitfield_width,
0153                       do_mask ? 0 : (1 << bitfield_width) - 1);
0154 }
0155
0156 static int intc_irqpin_set_sense(struct intc_irqpin_priv *p, int irq, int value)
0157 {
0158     /* The SENSE register is assumed to be 32-bit. */
0159     int bitfield_width = p->sense_bitfield_width;
0160     int shift = 32 - (irq + 1) * bitfield_width;
0161
0162     dev_dbg(&p->pdev->dev, "sense irq = %d, mode = %d\n", irq, value);
0163
0164     if (value >= (1 << bitfield_width))
0165         return -EINVAL;
0166
0167     intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_SENSE, shift,
0168                       bitfield_width, value);
0169     return 0;
0170 }
0171
0172 static void intc_irqpin_dbg(struct intc_irqpin_irq *i, char *str)
0173 {
0174     dev_dbg(&i->p->pdev->dev, "%s (%d:%d:%d)\n",
0175         str, i->requested_irq, i->hw_irq, i->domain_irq);
0176 }
0177
0178 static void intc_irqpin_irq_enable(struct irq_data *d)
0179 {
0180     struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
0181     int hw_irq = irqd_to_hwirq(d);
0182
0183     intc_irqpin_dbg(&p->irq[hw_irq], "enable");
0184     intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq);
0185 }
0186
0187 static void intc_irqpin_irq_disable(struct irq_data *d)
0188 {
0189     struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
0190     int hw_irq = irqd_to_hwirq(d);
0191
0192     intc_irqpin_dbg(&p->irq[hw_irq], "disable");
0193     intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq);
0194 }
0195
0196 static void intc_irqpin_shared_irq_enable(struct irq_data *d)
0197 {
0198     struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
0199     int hw_irq = irqd_to_hwirq(d);
0200
0201     intc_irqpin_dbg(&p->irq[hw_irq], "shared enable");
0202     intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq);
0203
0204     p->shared_irq_mask &= ~BIT(hw_irq);
0205 }
0206
0207 static void intc_irqpin_shared_irq_disable(struct irq_data *d)
0208 {
0209     struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
0210     int hw_irq = irqd_to_hwirq(d);
0211
0212     intc_irqpin_dbg(&p->irq[hw_irq], "shared disable");
0213     intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq);
0214
0215     p->shared_irq_mask |= BIT(hw_irq);
0216 }
0217
0218 static void intc_irqpin_irq_enable_force(struct irq_data *d)
0219 {
0220     struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
0221     int irq = p->irq[irqd_to_hwirq(d)].requested_irq;
0222
0223     intc_irqpin_irq_enable(d);
0224
0225     /* enable interrupt through parent interrupt controller,
0226      * assumes non-shared interrupt with 1:1 mapping
0227      * needed for busted IRQs on some SoCs like sh73a0
0228      */
0229     irq_get_chip(irq)->irq_unmask(irq_get_irq_data(irq));
0230 }
0231
0232 static void intc_irqpin_irq_disable_force(struct irq_data *d)
0233 {
0234     struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
0235     int irq = p->irq[irqd_to_hwirq(d)].requested_irq;
0236
0237     /* disable interrupt through parent interrupt controller,
0238      * assumes non-shared interrupt with 1:1 mapping
0239      * needed for busted IRQs on some SoCs like sh73a0
0240      */
0241     irq_get_chip(irq)->irq_mask(irq_get_irq_data(irq));
0242     intc_irqpin_irq_disable(d);
0243 }
0244
0245 #define INTC_IRQ_SENSE_VALID 0x10
0246 #define INTC_IRQ_SENSE(x) (x + INTC_IRQ_SENSE_VALID)
0247
0248 static unsigned char intc_irqpin_sense[IRQ_TYPE_SENSE_MASK + 1] = {
0249     [IRQ_TYPE_EDGE_FALLING] = INTC_IRQ_SENSE(0x00),
0250     [IRQ_TYPE_EDGE_RISING] = INTC_IRQ_SENSE(0x01),
0251     [IRQ_TYPE_LEVEL_LOW] = INTC_IRQ_SENSE(0x02),
0252     [IRQ_TYPE_LEVEL_HIGH] = INTC_IRQ_SENSE(0x03),
0253     [IRQ_TYPE_EDGE_BOTH] = INTC_IRQ_SENSE(0x04),
0254 };
0255
0256 static int intc_irqpin_irq_set_type(struct irq_data *d, unsigned int type)
0257 {
0258     unsigned char value = intc_irqpin_sense[type & IRQ_TYPE_SENSE_MASK];
0259     struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
0260
0261     if (!(value & INTC_IRQ_SENSE_VALID))
0262         return -EINVAL;
0263
0264     return intc_irqpin_set_sense(p, irqd_to_hwirq(d),
0265                      value ^ INTC_IRQ_SENSE_VALID);
0266 }
0267
0268 static int intc_irqpin_irq_set_wake(struct irq_data *d, unsigned int on)
0269 {
0270     struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
0271     int hw_irq = irqd_to_hwirq(d);
0272
0273     irq_set_irq_wake(p->irq[hw_irq].requested_irq, on);
0274     if (on)
0275         atomic_inc(&p->wakeup_path);
0276     else
0277         atomic_dec(&p->wakeup_path);
0278
0279     return 0;
0280 }
0281
0282 static irqreturn_t intc_irqpin_irq_handler(int irq, void *dev_id)
0283 {
0284     struct intc_irqpin_irq *i = dev_id;
0285     struct intc_irqpin_priv *p = i->p;
0286     unsigned long bit;
0287
0288     intc_irqpin_dbg(i, "demux1");
0289     bit = intc_irqpin_hwirq_mask(p, INTC_IRQPIN_REG_SOURCE, i->hw_irq);
0290
0291     if (intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE) & bit) {
0292         intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, ~bit);
0293         intc_irqpin_dbg(i, "demux2");
0294         generic_handle_irq(i->domain_irq);
0295         return IRQ_HANDLED;
0296     }
0297     return IRQ_NONE;
0298 }
0299
0300 static irqreturn_t intc_irqpin_shared_irq_handler(int irq, void *dev_id)
0301 {
0302     struct intc_irqpin_priv *p = dev_id;
0303     unsigned int reg_source = intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE);
0304     irqreturn_t status = IRQ_NONE;
0305     int k;
0306
0307     for (k = 0; k < 8; k++) {
0308         if (reg_source & BIT(7 - k)) {
0309             if (BIT(k) & p->shared_irq_mask)
0310                 continue;
0311
0312             status |= intc_irqpin_irq_handler(irq, &p->irq[k]);
0313         }
0314     }
0315
0316     return status;
0317 }
0318
0319 /*
0320  * This lock class tells lockdep that INTC External IRQ Pin irqs are in a
0321  * different category than their parents, so it won't report false recursion.
0322  */
0323 static struct lock_class_key intc_irqpin_irq_lock_class;
0324
0325 /* And this is for the request mutex */
0326 static struct lock_class_key intc_irqpin_irq_request_class;
0327
0328 static int intc_irqpin_irq_domain_map(struct irq_domain *h, unsigned int virq,
0329                       irq_hw_number_t hw)
0330 {
0331     struct intc_irqpin_priv *p = h->host_data;
0332
0333     p->irq[hw].domain_irq = virq;
0334     p->irq[hw].hw_irq = hw;
0335
0336     intc_irqpin_dbg(&p->irq[hw], "map");
0337     irq_set_chip_data(virq, h->host_data);
0338     irq_set_lockdep_class(virq, &intc_irqpin_irq_lock_class,
0339                   &intc_irqpin_irq_request_class);
0340     irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq);
0341     return 0;
0342 }
0343
0344 static const struct irq_domain_ops intc_irqpin_irq_domain_ops = {
0345     .map    = intc_irqpin_irq_domain_map,
0346     .xlate  = irq_domain_xlate_twocell,
0347 };
0348
0349 static const struct intc_irqpin_config intc_irqpin_irlm_r8a777x = {
0350     .irlm_bit = 23, /* ICR0.IRLM0 */
0351 };
0352
0353 static const struct intc_irqpin_config intc_irqpin_rmobile = {
0354     .irlm_bit = -1,
0355 };
0356
0357 static const struct of_device_id intc_irqpin_dt_ids[] = {
0358     { .compatible = "renesas,intc-irqpin", },
0359     { .compatible = "renesas,intc-irqpin-r8a7778",
0360       .data = &intc_irqpin_irlm_r8a777x },
0361     { .compatible = "renesas,intc-irqpin-r8a7779",
0362       .data = &intc_irqpin_irlm_r8a777x },
0363     { .compatible = "renesas,intc-irqpin-r8a7740",
0364       .data = &intc_irqpin_rmobile },
0365     { .compatible = "renesas,intc-irqpin-sh73a0",
0366       .data = &intc_irqpin_rmobile },
0367     {},
0368 };
0369 MODULE_DEVICE_TABLE(of, intc_irqpin_dt_ids);
0370
0371 static int intc_irqpin_probe(struct platform_device *pdev)
0372 {
0373     const struct intc_irqpin_config *config;
0374     struct device *dev = &pdev->dev;
0375     struct intc_irqpin_priv *p;
0376     struct intc_irqpin_iomem *i;
0377     struct resource *io[INTC_IRQPIN_REG_NR];
0378     struct irq_chip *irq_chip;
0379     void (*enable_fn)(struct irq_data *d);
0380     void (*disable_fn)(struct irq_data *d);
0381     const char *name = dev_name(dev);
0382     bool control_parent;
0383     unsigned int nirqs;
0384     int ref_irq;
0385     int ret;
0386     int k;
0387
0388     p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
0389     if (!p)
0390         return -ENOMEM;
0391
0392     /* deal with driver instance configuration */
0393     of_property_read_u32(dev->of_node, "sense-bitfield-width",
0394                  &p->sense_bitfield_width);
0395     control_parent = of_property_read_bool(dev->of_node, "control-parent");
0396     if (!p->sense_bitfield_width)
0397         p->sense_bitfield_width = 4; /* default to 4 bits */
0398
0399     p->pdev = pdev;
0400     platform_set_drvdata(pdev, p);
0401
0402     config = of_device_get_match_data(dev);
0403
0404     pm_runtime_enable(dev);
0405     pm_runtime_get_sync(dev);
0406
0407     /* get hold of register banks */
0408     memset(io, 0, sizeof(io));
0409     for (k = 0; k < INTC_IRQPIN_REG_NR; k++) {
0410         io[k] = platform_get_resource(pdev, IORESOURCE_MEM, k);
0411         if (!io[k] && k < INTC_IRQPIN_REG_NR_MANDATORY) {
0412             dev_err(dev, "not enough IOMEM resources\n");
0413             ret = -EINVAL;
0414             goto err0;
0415         }
0416     }
0417
0418     /* allow any number of IRQs between 1 and INTC_IRQPIN_MAX */
0419     for (k = 0; k < INTC_IRQPIN_MAX; k++) {
0420         ret = platform_get_irq_optional(pdev, k);
0421         if (ret == -ENXIO)
0422             break;
0423         if (ret < 0)
0424             goto err0;
0425
0426         p->irq[k].p = p;
0427         p->irq[k].requested_irq = ret;
0428     }
0429
0430     nirqs = k;
0431     if (nirqs < 1) {
0432         dev_err(dev, "not enough IRQ resources\n");
0433         ret = -EINVAL;
0434         goto err0;
0435     }
0436
0437     /* ioremap IOMEM and setup read/write callbacks */
0438     for (k = 0; k < INTC_IRQPIN_REG_NR; k++) {
0439         i = &p->iomem[k];
0440
0441         /* handle optional registers */
0442         if (!io[k])
0443             continue;
0444
0445         switch (resource_size(io[k])) {
0446         case 1:
0447             i->width = 8;
0448             i->read = intc_irqpin_read8;
0449             i->write = intc_irqpin_write8;
0450             break;
0451         case 4:
0452             i->width = 32;
0453             i->read = intc_irqpin_read32;
0454             i->write = intc_irqpin_write32;
0455             break;
0456         default:
0457             dev_err(dev, "IOMEM size mismatch\n");
0458             ret = -EINVAL;
0459             goto err0;
0460         }
0461
0462         i->iomem = devm_ioremap(dev, io[k]->start,
0463                     resource_size(io[k]));
0464         if (!i->iomem) {
0465             dev_err(dev, "failed to remap IOMEM\n");
0466             ret = -ENXIO;
0467             goto err0;
0468         }
0469     }
0470
0471     /* configure "individual IRQ mode" where needed */
0472     if (config && config->irlm_bit >= 0) {
0473         if (io[INTC_IRQPIN_REG_IRLM])
0474             intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_IRLM,
0475                               config->irlm_bit, 1, 1);
0476         else
0477             dev_warn(dev, "unable to select IRLM mode\n");
0478     }
0479
0480     /* mask all interrupts using priority */
0481     for (k = 0; k < nirqs; k++)
0482         intc_irqpin_mask_unmask_prio(p, k, 1);
0483
0484     /* clear all pending interrupts */
0485     intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, 0x0);
0486
0487     /* scan for shared interrupt lines */
0488     ref_irq = p->irq[0].requested_irq;
0489     p->shared_irqs = 1;
0490     for (k = 1; k < nirqs; k++) {
0491         if (ref_irq != p->irq[k].requested_irq) {
0492             p->shared_irqs = 0;
0493             break;
0494         }
0495     }
0496
0497     /* use more severe masking method if requested */
0498     if (control_parent) {
0499         enable_fn = intc_irqpin_irq_enable_force;
0500         disable_fn = intc_irqpin_irq_disable_force;
0501     } else if (!p->shared_irqs) {
0502         enable_fn = intc_irqpin_irq_enable;
0503         disable_fn = intc_irqpin_irq_disable;
0504     } else {
0505         enable_fn = intc_irqpin_shared_irq_enable;
0506         disable_fn = intc_irqpin_shared_irq_disable;
0507     }
0508
0509     irq_chip = &p->irq_chip;
0510     irq_chip->name = "intc-irqpin";
0511     irq_chip->irq_mask = disable_fn;
0512     irq_chip->irq_unmask = enable_fn;
0513     irq_chip->irq_set_type = intc_irqpin_irq_set_type;
0514     irq_chip->irq_set_wake = intc_irqpin_irq_set_wake;
0515     irq_chip->flags = IRQCHIP_MASK_ON_SUSPEND;
0516
0517     p->irq_domain = irq_domain_add_simple(dev->of_node, nirqs, 0,
0518                           &intc_irqpin_irq_domain_ops, p);
0519     if (!p->irq_domain) {
0520         ret = -ENXIO;
0521         dev_err(dev, "cannot initialize irq domain\n");
0522         goto err0;
0523     }
0524
0525     irq_domain_set_pm_device(p->irq_domain, dev);
0526
0527     if (p->shared_irqs) {
0528         /* request one shared interrupt */
0529         if (devm_request_irq(dev, p->irq[0].requested_irq,
0530                 intc_irqpin_shared_irq_handler,
0531                 IRQF_SHARED, name, p)) {
0532             dev_err(dev, "failed to request low IRQ\n");
0533             ret = -ENOENT;
0534             goto err1;
0535         }
0536     } else {
0537         /* request interrupts one by one */
0538         for (k = 0; k < nirqs; k++) {
0539             if (devm_request_irq(dev, p->irq[k].requested_irq,
0540                          intc_irqpin_irq_handler, 0, name,
0541                          &p->irq[k])) {
0542                 dev_err(dev, "failed to request low IRQ\n");
0543                 ret = -ENOENT;
0544                 goto err1;
0545             }
0546         }
0547     }
0548
0549     /* unmask all interrupts on prio level */
0550     for (k = 0; k < nirqs; k++)
0551         intc_irqpin_mask_unmask_prio(p, k, 0);
0552
0553     dev_info(dev, "driving %d irqs\n", nirqs);
0554
0555     return 0;
0556
0557 err1:
0558     irq_domain_remove(p->irq_domain);
0559 err0:
0560     pm_runtime_put(dev);
0561     pm_runtime_disable(dev);
0562     return ret;
0563 }
0564
0565 static int intc_irqpin_remove(struct platform_device *pdev)
0566 {
0567     struct intc_irqpin_priv *p = platform_get_drvdata(pdev);
0568
0569     irq_domain_remove(p->irq_domain);
0570     pm_runtime_put(&pdev->dev);
0571     pm_runtime_disable(&pdev->dev);
0572     return 0;
0573 }
0574
0575 static int __maybe_unused intc_irqpin_suspend(struct device *dev)
0576 {
0577     struct intc_irqpin_priv *p = dev_get_drvdata(dev);
0578
0579     if (atomic_read(&p->wakeup_path))
0580         device_set_wakeup_path(dev);
0581
0582     return 0;
0583 }
0584
0585 static SIMPLE_DEV_PM_OPS(intc_irqpin_pm_ops, intc_irqpin_suspend, NULL);
0586
0587 static struct platform_driver intc_irqpin_device_driver = {
0588     .probe      = intc_irqpin_probe,
0589     .remove     = intc_irqpin_remove,
0590     .driver     = {
0591         .name   = "renesas_intc_irqpin",
0592         .of_match_table = intc_irqpin_dt_ids,
0593         .pm = &intc_irqpin_pm_ops,
0594     }
0595 };
0596
0597 static int __init intc_irqpin_init(void)
0598 {
0599     return platform_driver_register(&intc_irqpin_device_driver);
0600 }
0601 postcore_initcall(intc_irqpin_init);
0602
0603 static void __exit intc_irqpin_exit(void)
0604 {
0605     platform_driver_unregister(&intc_irqpin_device_driver);
0606 }
0607 module_exit(intc_irqpin_exit);
0608
0609 MODULE_AUTHOR("Magnus Damm");
0610 MODULE_DESCRIPTION("Renesas INTC External IRQ Pin Driver");
0611 MODULE_LICENSE("GPL v2");