drivers/irqchip/irq-realtek-rtl.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2020 Birger Koblitz <mail@birger-koblitz.de>
0004  * Copyright (C) 2020 Bert Vermeulen <bert@biot.com>
0005  * Copyright (C) 2020 John Crispin <john@phrozen.org>
0006  */
0007
0008 #include <linux/of_irq.h>
0009 #include <linux/irqchip.h>
0010 #include <linux/spinlock.h>
0011 #include <linux/of_address.h>
0012 #include <linux/irqchip/chained_irq.h>
0013
0014 /* Global Interrupt Mask Register */
0015 #define RTL_ICTL_GIMR       0x00
0016 /* Global Interrupt Status Register */
0017 #define RTL_ICTL_GISR       0x04
0018 /* Interrupt Routing Registers */
0019 #define RTL_ICTL_IRR0       0x08
0020 #define RTL_ICTL_IRR1       0x0c
0021 #define RTL_ICTL_IRR2       0x10
0022 #define RTL_ICTL_IRR3       0x14
0023
0024 #define REG(x)      (realtek_ictl_base + x)
0025
0026 static DEFINE_RAW_SPINLOCK(irq_lock);
0027 static void __iomem *realtek_ictl_base;
0028
0029 static void realtek_ictl_unmask_irq(struct irq_data *i)
0030 {
0031     unsigned long flags;
0032     u32 value;
0033
0034     raw_spin_lock_irqsave(&irq_lock, flags);
0035
0036     value = readl(REG(RTL_ICTL_GIMR));
0037     value |= BIT(i->hwirq);
0038     writel(value, REG(RTL_ICTL_GIMR));
0039
0040     raw_spin_unlock_irqrestore(&irq_lock, flags);
0041 }
0042
0043 static void realtek_ictl_mask_irq(struct irq_data *i)
0044 {
0045     unsigned long flags;
0046     u32 value;
0047
0048     raw_spin_lock_irqsave(&irq_lock, flags);
0049
0050     value = readl(REG(RTL_ICTL_GIMR));
0051     value &= ~BIT(i->hwirq);
0052     writel(value, REG(RTL_ICTL_GIMR));
0053
0054     raw_spin_unlock_irqrestore(&irq_lock, flags);
0055 }
0056
0057 static struct irq_chip realtek_ictl_irq = {
0058     .name = "realtek-rtl-intc",
0059     .irq_mask = realtek_ictl_mask_irq,
0060     .irq_unmask = realtek_ictl_unmask_irq,
0061 };
0062
0063 static int intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
0064 {
0065     irq_set_chip_and_handler(irq, &realtek_ictl_irq, handle_level_irq);
0066
0067     return 0;
0068 }
0069
0070 static const struct irq_domain_ops irq_domain_ops = {
0071     .map = intc_map,
0072     .xlate = irq_domain_xlate_onecell,
0073 };
0074
0075 static void realtek_irq_dispatch(struct irq_desc *desc)
0076 {
0077     struct irq_chip *chip = irq_desc_get_chip(desc);
0078     struct irq_domain *domain;
0079     unsigned long pending;
0080     unsigned int soc_int;
0081
0082     chained_irq_enter(chip, desc);
0083     pending = readl(REG(RTL_ICTL_GIMR)) & readl(REG(RTL_ICTL_GISR));
0084
0085     if (unlikely(!pending)) {
0086         spurious_interrupt();
0087         goto out;
0088     }
0089
0090     domain = irq_desc_get_handler_data(desc);
0091     for_each_set_bit(soc_int, &pending, 32)
0092         generic_handle_domain_irq(domain, soc_int);
0093
0094 out:
0095     chained_irq_exit(chip, desc);
0096 }
0097
0098 /*
0099  * SoC interrupts are cascaded to MIPS CPU interrupts according to the
0100  * interrupt-map in the device tree. Each SoC interrupt gets 4 bits for
0101  * the CPU interrupt in an Interrupt Routing Register. Max 32 SoC interrupts
0102  * thus go into 4 IRRs. A routing value of '0' means the interrupt is left
0103  * disconnected. Routing values {1..15} connect to output lines {0..14}.
0104  */
0105 static int __init map_interrupts(struct device_node *node, struct irq_domain *domain)
0106 {
0107     struct device_node *cpu_ictl;
0108     const __be32 *imap;
0109     u32 imaplen, soc_int, cpu_int, tmp, regs[4];
0110     int ret, i, irr_regs[] = {
0111         RTL_ICTL_IRR3,
0112         RTL_ICTL_IRR2,
0113         RTL_ICTL_IRR1,
0114         RTL_ICTL_IRR0,
0115     };
0116     u8 mips_irqs_set;
0117
0118     ret = of_property_read_u32(node, "#address-cells", &tmp);
0119     if (ret || tmp)
0120         return -EINVAL;
0121
0122     imap = of_get_property(node, "interrupt-map", &imaplen);
0123     if (!imap || imaplen % 3)
0124         return -EINVAL;
0125
0126     mips_irqs_set = 0;
0127     memset(regs, 0, sizeof(regs));
0128     for (i = 0; i < imaplen; i += 3 * sizeof(u32)) {
0129         soc_int = be32_to_cpup(imap);
0130         if (soc_int > 31)
0131             return -EINVAL;
0132
0133         cpu_ictl = of_find_node_by_phandle(be32_to_cpup(imap + 1));
0134         if (!cpu_ictl)
0135             return -EINVAL;
0136         ret = of_property_read_u32(cpu_ictl, "#interrupt-cells", &tmp);
0137         of_node_put(cpu_ictl);
0138         if (ret || tmp != 1)
0139             return -EINVAL;
0140
0141         cpu_int = be32_to_cpup(imap + 2);
0142         if (cpu_int > 7 || cpu_int < 2)
0143             return -EINVAL;
0144
0145         if (!(mips_irqs_set & BIT(cpu_int))) {
0146             irq_set_chained_handler_and_data(cpu_int, realtek_irq_dispatch,
0147                              domain);
0148             mips_irqs_set |= BIT(cpu_int);
0149         }
0150
0151         /* Use routing values (1..6) for CPU interrupts (2..7) */
0152         regs[(soc_int * 4) / 32] |= (cpu_int - 1) << (soc_int * 4) % 32;
0153         imap += 3;
0154     }
0155
0156     for (i = 0; i < 4; i++)
0157         writel(regs[i], REG(irr_regs[i]));
0158
0159     return 0;
0160 }
0161
0162 static int __init realtek_rtl_of_init(struct device_node *node, struct device_node *parent)
0163 {
0164     struct irq_domain *domain;
0165     int ret;
0166
0167     realtek_ictl_base = of_iomap(node, 0);
0168     if (!realtek_ictl_base)
0169         return -ENXIO;
0170
0171     /* Disable all cascaded interrupts */
0172     writel(0, REG(RTL_ICTL_GIMR));
0173
0174     domain = irq_domain_add_simple(node, 32, 0,
0175                        &irq_domain_ops, NULL);
0176
0177     ret = map_interrupts(node, domain);
0178     if (ret) {
0179         pr_err("invalid interrupt map\n");
0180         return ret;
0181     }
0182
0183     return 0;
0184 }
0185
0186 IRQCHIP_DECLARE(realtek_rtl_intc, "realtek,rtl-intc", realtek_rtl_of_init);