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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * PRU-ICSS INTC IRQChip driver for various TI SoCs
0004  *
0005  * Copyright (C) 2016-2020 Texas Instruments Incorporated - http://www.ti.com/
0006  *
0007  * Author(s):
0008  *  Andrew F. Davis <afd@ti.com>
0009  *  Suman Anna <s-anna@ti.com>
0010  *  Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org> for Texas Instruments
0011  *
0012  * Copyright (C) 2019 David Lechner <david@lechnology.com>
0013  */
0014 
0015 #include <linux/interrupt.h>
0016 #include <linux/irq.h>
0017 #include <linux/irqchip/chained_irq.h>
0018 #include <linux/irqdomain.h>
0019 #include <linux/module.h>
0020 #include <linux/of_device.h>
0021 #include <linux/platform_device.h>
0022 
0023 /*
0024  * Number of host interrupts reaching the main MPU sub-system. Note that this
0025  * is not the same as the total number of host interrupts supported by the PRUSS
0026  * INTC instance
0027  */
0028 #define MAX_NUM_HOST_IRQS   8
0029 
0030 /* minimum starting host interrupt number for MPU */
0031 #define FIRST_PRU_HOST_INT  2
0032 
0033 /* PRU_ICSS_INTC registers */
0034 #define PRU_INTC_REVID      0x0000
0035 #define PRU_INTC_CR     0x0004
0036 #define PRU_INTC_GER        0x0010
0037 #define PRU_INTC_GNLR       0x001c
0038 #define PRU_INTC_SISR       0x0020
0039 #define PRU_INTC_SICR       0x0024
0040 #define PRU_INTC_EISR       0x0028
0041 #define PRU_INTC_EICR       0x002c
0042 #define PRU_INTC_HIEISR     0x0034
0043 #define PRU_INTC_HIDISR     0x0038
0044 #define PRU_INTC_GPIR       0x0080
0045 #define PRU_INTC_SRSR(x)    (0x0200 + (x) * 4)
0046 #define PRU_INTC_SECR(x)    (0x0280 + (x) * 4)
0047 #define PRU_INTC_ESR(x)     (0x0300 + (x) * 4)
0048 #define PRU_INTC_ECR(x)     (0x0380 + (x) * 4)
0049 #define PRU_INTC_CMR(x)     (0x0400 + (x) * 4)
0050 #define PRU_INTC_HMR(x)     (0x0800 + (x) * 4)
0051 #define PRU_INTC_HIPIR(x)   (0x0900 + (x) * 4)
0052 #define PRU_INTC_SIPR(x)    (0x0d00 + (x) * 4)
0053 #define PRU_INTC_SITR(x)    (0x0d80 + (x) * 4)
0054 #define PRU_INTC_HINLR(x)   (0x1100 + (x) * 4)
0055 #define PRU_INTC_HIER       0x1500
0056 
0057 /* CMR register bit-field macros */
0058 #define CMR_EVT_MAP_MASK    0xf
0059 #define CMR_EVT_MAP_BITS    8
0060 #define CMR_EVT_PER_REG     4
0061 
0062 /* HMR register bit-field macros */
0063 #define HMR_CH_MAP_MASK     0xf
0064 #define HMR_CH_MAP_BITS     8
0065 #define HMR_CH_PER_REG      4
0066 
0067 /* HIPIR register bit-fields */
0068 #define INTC_HIPIR_NONE_HINT    0x80000000
0069 
0070 #define MAX_PRU_SYS_EVENTS 160
0071 #define MAX_PRU_CHANNELS 20
0072 
0073 /**
0074  * struct pruss_intc_map_record - keeps track of actual mapping state
0075  * @value: The currently mapped value (channel or host)
0076  * @ref_count: Keeps track of number of current users of this resource
0077  */
0078 struct pruss_intc_map_record {
0079     u8 value;
0080     u8 ref_count;
0081 };
0082 
0083 /**
0084  * struct pruss_intc_match_data - match data to handle SoC variations
0085  * @num_system_events: number of input system events handled by the PRUSS INTC
0086  * @num_host_events: number of host events (which is equal to number of
0087  *           channels) supported by the PRUSS INTC
0088  */
0089 struct pruss_intc_match_data {
0090     u8 num_system_events;
0091     u8 num_host_events;
0092 };
0093 
0094 /**
0095  * struct pruss_intc - PRUSS interrupt controller structure
0096  * @event_channel: current state of system event to channel mappings
0097  * @channel_host: current state of channel to host mappings
0098  * @irqs: kernel irq numbers corresponding to PRUSS host interrupts
0099  * @base: base virtual address of INTC register space
0100  * @domain: irq domain for this interrupt controller
0101  * @soc_config: cached PRUSS INTC IP configuration data
0102  * @dev: PRUSS INTC device pointer
0103  * @lock: mutex to serialize interrupts mapping
0104  */
0105 struct pruss_intc {
0106     struct pruss_intc_map_record event_channel[MAX_PRU_SYS_EVENTS];
0107     struct pruss_intc_map_record channel_host[MAX_PRU_CHANNELS];
0108     unsigned int irqs[MAX_NUM_HOST_IRQS];
0109     void __iomem *base;
0110     struct irq_domain *domain;
0111     const struct pruss_intc_match_data *soc_config;
0112     struct device *dev;
0113     struct mutex lock; /* PRUSS INTC lock */
0114 };
0115 
0116 /**
0117  * struct pruss_host_irq_data - PRUSS host irq data structure
0118  * @intc: PRUSS interrupt controller pointer
0119  * @host_irq: host irq number
0120  */
0121 struct pruss_host_irq_data {
0122     struct pruss_intc *intc;
0123     u8 host_irq;
0124 };
0125 
0126 static inline u32 pruss_intc_read_reg(struct pruss_intc *intc, unsigned int reg)
0127 {
0128     return readl_relaxed(intc->base + reg);
0129 }
0130 
0131 static inline void pruss_intc_write_reg(struct pruss_intc *intc,
0132                     unsigned int reg, u32 val)
0133 {
0134     writel_relaxed(val, intc->base + reg);
0135 }
0136 
0137 static void pruss_intc_update_cmr(struct pruss_intc *intc, unsigned int evt,
0138                   u8 ch)
0139 {
0140     u32 idx, offset, val;
0141 
0142     idx = evt / CMR_EVT_PER_REG;
0143     offset = (evt % CMR_EVT_PER_REG) * CMR_EVT_MAP_BITS;
0144 
0145     val = pruss_intc_read_reg(intc, PRU_INTC_CMR(idx));
0146     val &= ~(CMR_EVT_MAP_MASK << offset);
0147     val |= ch << offset;
0148     pruss_intc_write_reg(intc, PRU_INTC_CMR(idx), val);
0149 
0150     dev_dbg(intc->dev, "SYSEV%u -> CH%d (CMR%d 0x%08x)\n", evt, ch,
0151         idx, pruss_intc_read_reg(intc, PRU_INTC_CMR(idx)));
0152 }
0153 
0154 static void pruss_intc_update_hmr(struct pruss_intc *intc, u8 ch, u8 host)
0155 {
0156     u32 idx, offset, val;
0157 
0158     idx = ch / HMR_CH_PER_REG;
0159     offset = (ch % HMR_CH_PER_REG) * HMR_CH_MAP_BITS;
0160 
0161     val = pruss_intc_read_reg(intc, PRU_INTC_HMR(idx));
0162     val &= ~(HMR_CH_MAP_MASK << offset);
0163     val |= host << offset;
0164     pruss_intc_write_reg(intc, PRU_INTC_HMR(idx), val);
0165 
0166     dev_dbg(intc->dev, "CH%d -> HOST%d (HMR%d 0x%08x)\n", ch, host, idx,
0167         pruss_intc_read_reg(intc, PRU_INTC_HMR(idx)));
0168 }
0169 
0170 /**
0171  * pruss_intc_map() - configure the PRUSS INTC
0172  * @intc: PRUSS interrupt controller pointer
0173  * @hwirq: the system event number
0174  *
0175  * Configures the PRUSS INTC with the provided configuration from the one parsed
0176  * in the xlate function.
0177  */
0178 static void pruss_intc_map(struct pruss_intc *intc, unsigned long hwirq)
0179 {
0180     struct device *dev = intc->dev;
0181     u8 ch, host, reg_idx;
0182     u32 val;
0183 
0184     mutex_lock(&intc->lock);
0185 
0186     intc->event_channel[hwirq].ref_count++;
0187 
0188     ch = intc->event_channel[hwirq].value;
0189     host = intc->channel_host[ch].value;
0190 
0191     pruss_intc_update_cmr(intc, hwirq, ch);
0192 
0193     reg_idx = hwirq / 32;
0194     val = BIT(hwirq  % 32);
0195 
0196     /* clear and enable system event */
0197     pruss_intc_write_reg(intc, PRU_INTC_ESR(reg_idx), val);
0198     pruss_intc_write_reg(intc, PRU_INTC_SECR(reg_idx), val);
0199 
0200     if (++intc->channel_host[ch].ref_count == 1) {
0201         pruss_intc_update_hmr(intc, ch, host);
0202 
0203         /* enable host interrupts */
0204         pruss_intc_write_reg(intc, PRU_INTC_HIEISR, host);
0205     }
0206 
0207     dev_dbg(dev, "mapped system_event = %lu channel = %d host = %d",
0208         hwirq, ch, host);
0209 
0210     mutex_unlock(&intc->lock);
0211 }
0212 
0213 /**
0214  * pruss_intc_unmap() - unconfigure the PRUSS INTC
0215  * @intc: PRUSS interrupt controller pointer
0216  * @hwirq: the system event number
0217  *
0218  * Undo whatever was done in pruss_intc_map() for a PRU core.
0219  * Mappings are reference counted, so resources are only disabled when there
0220  * are no longer any users.
0221  */
0222 static void pruss_intc_unmap(struct pruss_intc *intc, unsigned long hwirq)
0223 {
0224     u8 ch, host, reg_idx;
0225     u32 val;
0226 
0227     mutex_lock(&intc->lock);
0228 
0229     ch = intc->event_channel[hwirq].value;
0230     host = intc->channel_host[ch].value;
0231 
0232     if (--intc->channel_host[ch].ref_count == 0) {
0233         /* disable host interrupts */
0234         pruss_intc_write_reg(intc, PRU_INTC_HIDISR, host);
0235 
0236         /* clear the map using reset value 0 */
0237         pruss_intc_update_hmr(intc, ch, 0);
0238     }
0239 
0240     intc->event_channel[hwirq].ref_count--;
0241     reg_idx = hwirq / 32;
0242     val = BIT(hwirq  % 32);
0243 
0244     /* disable system events */
0245     pruss_intc_write_reg(intc, PRU_INTC_ECR(reg_idx), val);
0246     /* clear any pending status */
0247     pruss_intc_write_reg(intc, PRU_INTC_SECR(reg_idx), val);
0248 
0249     /* clear the map using reset value 0 */
0250     pruss_intc_update_cmr(intc, hwirq, 0);
0251 
0252     dev_dbg(intc->dev, "unmapped system_event = %lu channel = %d host = %d\n",
0253         hwirq, ch, host);
0254 
0255     mutex_unlock(&intc->lock);
0256 }
0257 
0258 static void pruss_intc_init(struct pruss_intc *intc)
0259 {
0260     const struct pruss_intc_match_data *soc_config = intc->soc_config;
0261     int num_chnl_map_regs, num_host_intr_regs, num_event_type_regs, i;
0262 
0263     num_chnl_map_regs = DIV_ROUND_UP(soc_config->num_system_events,
0264                      CMR_EVT_PER_REG);
0265     num_host_intr_regs = DIV_ROUND_UP(soc_config->num_host_events,
0266                       HMR_CH_PER_REG);
0267     num_event_type_regs = DIV_ROUND_UP(soc_config->num_system_events, 32);
0268 
0269     /*
0270      * configure polarity (SIPR register) to active high and
0271      * type (SITR register) to level interrupt for all system events
0272      */
0273     for (i = 0; i < num_event_type_regs; i++) {
0274         pruss_intc_write_reg(intc, PRU_INTC_SIPR(i), 0xffffffff);
0275         pruss_intc_write_reg(intc, PRU_INTC_SITR(i), 0);
0276     }
0277 
0278     /* clear all interrupt channel map registers, 4 events per register */
0279     for (i = 0; i < num_chnl_map_regs; i++)
0280         pruss_intc_write_reg(intc, PRU_INTC_CMR(i), 0);
0281 
0282     /* clear all host interrupt map registers, 4 channels per register */
0283     for (i = 0; i < num_host_intr_regs; i++)
0284         pruss_intc_write_reg(intc, PRU_INTC_HMR(i), 0);
0285 
0286     /* global interrupt enable */
0287     pruss_intc_write_reg(intc, PRU_INTC_GER, 1);
0288 }
0289 
0290 static void pruss_intc_irq_ack(struct irq_data *data)
0291 {
0292     struct pruss_intc *intc = irq_data_get_irq_chip_data(data);
0293     unsigned int hwirq = data->hwirq;
0294 
0295     pruss_intc_write_reg(intc, PRU_INTC_SICR, hwirq);
0296 }
0297 
0298 static void pruss_intc_irq_mask(struct irq_data *data)
0299 {
0300     struct pruss_intc *intc = irq_data_get_irq_chip_data(data);
0301     unsigned int hwirq = data->hwirq;
0302 
0303     pruss_intc_write_reg(intc, PRU_INTC_EICR, hwirq);
0304 }
0305 
0306 static void pruss_intc_irq_unmask(struct irq_data *data)
0307 {
0308     struct pruss_intc *intc = irq_data_get_irq_chip_data(data);
0309     unsigned int hwirq = data->hwirq;
0310 
0311     pruss_intc_write_reg(intc, PRU_INTC_EISR, hwirq);
0312 }
0313 
0314 static int pruss_intc_irq_reqres(struct irq_data *data)
0315 {
0316     if (!try_module_get(THIS_MODULE))
0317         return -ENODEV;
0318 
0319     return 0;
0320 }
0321 
0322 static void pruss_intc_irq_relres(struct irq_data *data)
0323 {
0324     module_put(THIS_MODULE);
0325 }
0326 
0327 static int pruss_intc_irq_get_irqchip_state(struct irq_data *data,
0328                         enum irqchip_irq_state which,
0329                         bool *state)
0330 {
0331     struct pruss_intc *intc = irq_data_get_irq_chip_data(data);
0332     u32 reg, mask, srsr;
0333 
0334     if (which != IRQCHIP_STATE_PENDING)
0335         return -EINVAL;
0336 
0337     reg = PRU_INTC_SRSR(data->hwirq / 32);
0338     mask = BIT(data->hwirq % 32);
0339 
0340     srsr = pruss_intc_read_reg(intc, reg);
0341 
0342     *state = !!(srsr & mask);
0343 
0344     return 0;
0345 }
0346 
0347 static int pruss_intc_irq_set_irqchip_state(struct irq_data *data,
0348                         enum irqchip_irq_state which,
0349                         bool state)
0350 {
0351     struct pruss_intc *intc = irq_data_get_irq_chip_data(data);
0352 
0353     if (which != IRQCHIP_STATE_PENDING)
0354         return -EINVAL;
0355 
0356     if (state)
0357         pruss_intc_write_reg(intc, PRU_INTC_SISR, data->hwirq);
0358     else
0359         pruss_intc_write_reg(intc, PRU_INTC_SICR, data->hwirq);
0360 
0361     return 0;
0362 }
0363 
0364 static struct irq_chip pruss_irqchip = {
0365     .name           = "pruss-intc",
0366     .irq_ack        = pruss_intc_irq_ack,
0367     .irq_mask       = pruss_intc_irq_mask,
0368     .irq_unmask     = pruss_intc_irq_unmask,
0369     .irq_request_resources  = pruss_intc_irq_reqres,
0370     .irq_release_resources  = pruss_intc_irq_relres,
0371     .irq_get_irqchip_state  = pruss_intc_irq_get_irqchip_state,
0372     .irq_set_irqchip_state  = pruss_intc_irq_set_irqchip_state,
0373 };
0374 
0375 static int pruss_intc_validate_mapping(struct pruss_intc *intc, int event,
0376                        int channel, int host)
0377 {
0378     struct device *dev = intc->dev;
0379     int ret = 0;
0380 
0381     mutex_lock(&intc->lock);
0382 
0383     /* check if sysevent already assigned */
0384     if (intc->event_channel[event].ref_count > 0 &&
0385         intc->event_channel[event].value != channel) {
0386         dev_err(dev, "event %d (req. ch %d) already assigned to channel %d\n",
0387             event, channel, intc->event_channel[event].value);
0388         ret = -EBUSY;
0389         goto unlock;
0390     }
0391 
0392     /* check if channel already assigned */
0393     if (intc->channel_host[channel].ref_count > 0 &&
0394         intc->channel_host[channel].value != host) {
0395         dev_err(dev, "channel %d (req. host %d) already assigned to host %d\n",
0396             channel, host, intc->channel_host[channel].value);
0397         ret = -EBUSY;
0398         goto unlock;
0399     }
0400 
0401     intc->event_channel[event].value = channel;
0402     intc->channel_host[channel].value = host;
0403 
0404 unlock:
0405     mutex_unlock(&intc->lock);
0406     return ret;
0407 }
0408 
0409 static int
0410 pruss_intc_irq_domain_xlate(struct irq_domain *d, struct device_node *node,
0411                 const u32 *intspec, unsigned int intsize,
0412                 unsigned long *out_hwirq, unsigned int *out_type)
0413 {
0414     struct pruss_intc *intc = d->host_data;
0415     struct device *dev = intc->dev;
0416     int ret, sys_event, channel, host;
0417 
0418     if (intsize < 3)
0419         return -EINVAL;
0420 
0421     sys_event = intspec[0];
0422     if (sys_event < 0 || sys_event >= intc->soc_config->num_system_events) {
0423         dev_err(dev, "%d is not valid event number\n", sys_event);
0424         return -EINVAL;
0425     }
0426 
0427     channel = intspec[1];
0428     if (channel < 0 || channel >= intc->soc_config->num_host_events) {
0429         dev_err(dev, "%d is not valid channel number", channel);
0430         return -EINVAL;
0431     }
0432 
0433     host = intspec[2];
0434     if (host < 0 || host >= intc->soc_config->num_host_events) {
0435         dev_err(dev, "%d is not valid host irq number\n", host);
0436         return -EINVAL;
0437     }
0438 
0439     /* check if requested sys_event was already mapped, if so validate it */
0440     ret = pruss_intc_validate_mapping(intc, sys_event, channel, host);
0441     if (ret)
0442         return ret;
0443 
0444     *out_hwirq = sys_event;
0445     *out_type = IRQ_TYPE_LEVEL_HIGH;
0446 
0447     return 0;
0448 }
0449 
0450 static int pruss_intc_irq_domain_map(struct irq_domain *d, unsigned int virq,
0451                      irq_hw_number_t hw)
0452 {
0453     struct pruss_intc *intc = d->host_data;
0454 
0455     pruss_intc_map(intc, hw);
0456 
0457     irq_set_chip_data(virq, intc);
0458     irq_set_chip_and_handler(virq, &pruss_irqchip, handle_level_irq);
0459 
0460     return 0;
0461 }
0462 
0463 static void pruss_intc_irq_domain_unmap(struct irq_domain *d, unsigned int virq)
0464 {
0465     struct pruss_intc *intc = d->host_data;
0466     unsigned long hwirq = irqd_to_hwirq(irq_get_irq_data(virq));
0467 
0468     irq_set_chip_and_handler(virq, NULL, NULL);
0469     irq_set_chip_data(virq, NULL);
0470     pruss_intc_unmap(intc, hwirq);
0471 }
0472 
0473 static const struct irq_domain_ops pruss_intc_irq_domain_ops = {
0474     .xlate  = pruss_intc_irq_domain_xlate,
0475     .map    = pruss_intc_irq_domain_map,
0476     .unmap  = pruss_intc_irq_domain_unmap,
0477 };
0478 
0479 static void pruss_intc_irq_handler(struct irq_desc *desc)
0480 {
0481     unsigned int irq = irq_desc_get_irq(desc);
0482     struct irq_chip *chip = irq_desc_get_chip(desc);
0483     struct pruss_host_irq_data *host_irq_data = irq_get_handler_data(irq);
0484     struct pruss_intc *intc = host_irq_data->intc;
0485     u8 host_irq = host_irq_data->host_irq + FIRST_PRU_HOST_INT;
0486 
0487     chained_irq_enter(chip, desc);
0488 
0489     while (true) {
0490         u32 hipir;
0491         int hwirq, err;
0492 
0493         /* get highest priority pending PRUSS system event */
0494         hipir = pruss_intc_read_reg(intc, PRU_INTC_HIPIR(host_irq));
0495         if (hipir & INTC_HIPIR_NONE_HINT)
0496             break;
0497 
0498         hwirq = hipir & GENMASK(9, 0);
0499         err = generic_handle_domain_irq(intc->domain, hwirq);
0500 
0501         /*
0502          * NOTE: manually ACK any system events that do not have a
0503          * handler mapped yet
0504          */
0505         if (WARN_ON_ONCE(err))
0506             pruss_intc_write_reg(intc, PRU_INTC_SICR, hwirq);
0507     }
0508 
0509     chained_irq_exit(chip, desc);
0510 }
0511 
0512 static const char * const irq_names[MAX_NUM_HOST_IRQS] = {
0513     "host_intr0", "host_intr1", "host_intr2", "host_intr3",
0514     "host_intr4", "host_intr5", "host_intr6", "host_intr7",
0515 };
0516 
0517 static int pruss_intc_probe(struct platform_device *pdev)
0518 {
0519     const struct pruss_intc_match_data *data;
0520     struct device *dev = &pdev->dev;
0521     struct pruss_intc *intc;
0522     struct pruss_host_irq_data *host_data;
0523     int i, irq, ret;
0524     u8 max_system_events, irqs_reserved = 0;
0525 
0526     data = of_device_get_match_data(dev);
0527     if (!data)
0528         return -ENODEV;
0529 
0530     max_system_events = data->num_system_events;
0531 
0532     intc = devm_kzalloc(dev, sizeof(*intc), GFP_KERNEL);
0533     if (!intc)
0534         return -ENOMEM;
0535 
0536     intc->soc_config = data;
0537     intc->dev = dev;
0538     platform_set_drvdata(pdev, intc);
0539 
0540     intc->base = devm_platform_ioremap_resource(pdev, 0);
0541     if (IS_ERR(intc->base))
0542         return PTR_ERR(intc->base);
0543 
0544     ret = of_property_read_u8(dev->of_node, "ti,irqs-reserved",
0545                   &irqs_reserved);
0546 
0547     /*
0548      * The irqs-reserved is used only for some SoC's therefore not having
0549      * this property is still valid
0550      */
0551     if (ret < 0 && ret != -EINVAL)
0552         return ret;
0553 
0554     pruss_intc_init(intc);
0555 
0556     mutex_init(&intc->lock);
0557 
0558     intc->domain = irq_domain_add_linear(dev->of_node, max_system_events,
0559                          &pruss_intc_irq_domain_ops, intc);
0560     if (!intc->domain)
0561         return -ENOMEM;
0562 
0563     for (i = 0; i < MAX_NUM_HOST_IRQS; i++) {
0564         if (irqs_reserved & BIT(i))
0565             continue;
0566 
0567         irq = platform_get_irq_byname(pdev, irq_names[i]);
0568         if (irq <= 0) {
0569             ret = (irq == 0) ? -EINVAL : irq;
0570             goto fail_irq;
0571         }
0572 
0573         intc->irqs[i] = irq;
0574 
0575         host_data = devm_kzalloc(dev, sizeof(*host_data), GFP_KERNEL);
0576         if (!host_data) {
0577             ret = -ENOMEM;
0578             goto fail_irq;
0579         }
0580 
0581         host_data->intc = intc;
0582         host_data->host_irq = i;
0583 
0584         irq_set_handler_data(irq, host_data);
0585         irq_set_chained_handler(irq, pruss_intc_irq_handler);
0586     }
0587 
0588     return 0;
0589 
0590 fail_irq:
0591     while (--i >= 0) {
0592         if (intc->irqs[i])
0593             irq_set_chained_handler_and_data(intc->irqs[i], NULL,
0594                              NULL);
0595     }
0596 
0597     irq_domain_remove(intc->domain);
0598 
0599     return ret;
0600 }
0601 
0602 static int pruss_intc_remove(struct platform_device *pdev)
0603 {
0604     struct pruss_intc *intc = platform_get_drvdata(pdev);
0605     u8 max_system_events = intc->soc_config->num_system_events;
0606     unsigned int hwirq;
0607     int i;
0608 
0609     for (i = 0; i < MAX_NUM_HOST_IRQS; i++) {
0610         if (intc->irqs[i])
0611             irq_set_chained_handler_and_data(intc->irqs[i], NULL,
0612                              NULL);
0613     }
0614 
0615     for (hwirq = 0; hwirq < max_system_events; hwirq++)
0616         irq_dispose_mapping(irq_find_mapping(intc->domain, hwirq));
0617 
0618     irq_domain_remove(intc->domain);
0619 
0620     return 0;
0621 }
0622 
0623 static const struct pruss_intc_match_data pruss_intc_data = {
0624     .num_system_events = 64,
0625     .num_host_events = 10,
0626 };
0627 
0628 static const struct pruss_intc_match_data icssg_intc_data = {
0629     .num_system_events = 160,
0630     .num_host_events = 20,
0631 };
0632 
0633 static const struct of_device_id pruss_intc_of_match[] = {
0634     {
0635         .compatible = "ti,pruss-intc",
0636         .data = &pruss_intc_data,
0637     },
0638     {
0639         .compatible = "ti,icssg-intc",
0640         .data = &icssg_intc_data,
0641     },
0642     { /* sentinel */ },
0643 };
0644 MODULE_DEVICE_TABLE(of, pruss_intc_of_match);
0645 
0646 static struct platform_driver pruss_intc_driver = {
0647     .driver = {
0648         .name = "pruss-intc",
0649         .of_match_table = pruss_intc_of_match,
0650         .suppress_bind_attrs = true,
0651     },
0652     .probe  = pruss_intc_probe,
0653     .remove = pruss_intc_remove,
0654 };
0655 module_platform_driver(pruss_intc_driver);
0656 
0657 MODULE_AUTHOR("Andrew F. Davis <afd@ti.com>");
0658 MODULE_AUTHOR("Suman Anna <s-anna@ti.com>");
0659 MODULE_AUTHOR("Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org>");
0660 MODULE_DESCRIPTION("TI PRU-ICSS INTC Driver");
0661 MODULE_LICENSE("GPL v2");
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