drivers/irqchip/irq-pic32-evic.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Cristian Birsan <cristian.birsan@microchip.com>
0004  * Joshua Henderson <joshua.henderson@microchip.com>
0005  * Copyright (C) 2016 Microchip Technology Inc.  All rights reserved.
0006  */
0007 #include <linux/kernel.h>
0008 #include <linux/module.h>
0009 #include <linux/interrupt.h>
0010 #include <linux/irqdomain.h>
0011 #include <linux/of_address.h>
0012 #include <linux/slab.h>
0013 #include <linux/io.h>
0014 #include <linux/irqchip.h>
0015 #include <linux/irq.h>
0016
0017 #include <asm/irq.h>
0018 #include <asm/traps.h>
0019 #include <asm/mach-pic32/pic32.h>
0020
0021 #define REG_INTCON  0x0000
0022 #define REG_INTSTAT 0x0020
0023 #define REG_IFS_OFFSET  0x0040
0024 #define REG_IEC_OFFSET  0x00C0
0025 #define REG_IPC_OFFSET  0x0140
0026 #define REG_OFF_OFFSET  0x0540
0027
0028 #define MAJPRI_MASK 0x07
0029 #define SUBPRI_MASK 0x03
0030 #define PRIORITY_MASK   0x1F
0031
0032 #define PIC32_INT_PRI(pri, subpri)              \
0033     ((((pri) & MAJPRI_MASK) << 2) | ((subpri) & SUBPRI_MASK))
0034
0035 struct evic_chip_data {
0036     u32 irq_types[NR_IRQS];
0037     u32 ext_irqs[8];
0038 };
0039
0040 static struct irq_domain *evic_irq_domain;
0041 static void __iomem *evic_base;
0042
0043 asmlinkage void __weak plat_irq_dispatch(void)
0044 {
0045     unsigned int hwirq;
0046
0047     hwirq = readl(evic_base + REG_INTSTAT) & 0xFF;
0048     do_domain_IRQ(evic_irq_domain, hwirq);
0049 }
0050
0051 static struct evic_chip_data *irqd_to_priv(struct irq_data *data)
0052 {
0053     return (struct evic_chip_data *)data->domain->host_data;
0054 }
0055
0056 static int pic32_set_ext_polarity(int bit, u32 type)
0057 {
0058     /*
0059      * External interrupts can be either edge rising or edge falling,
0060      * but not both.
0061      */
0062     switch (type) {
0063     case IRQ_TYPE_EDGE_RISING:
0064         writel(BIT(bit), evic_base + PIC32_SET(REG_INTCON));
0065         break;
0066     case IRQ_TYPE_EDGE_FALLING:
0067         writel(BIT(bit), evic_base + PIC32_CLR(REG_INTCON));
0068         break;
0069     default:
0070         return -EINVAL;
0071     }
0072
0073     return 0;
0074 }
0075
0076 static int pic32_set_type_edge(struct irq_data *data,
0077                    unsigned int flow_type)
0078 {
0079     struct evic_chip_data *priv = irqd_to_priv(data);
0080     int ret;
0081     int i;
0082
0083     if (!(flow_type & IRQ_TYPE_EDGE_BOTH))
0084         return -EBADR;
0085
0086     /* set polarity for external interrupts only */
0087     for (i = 0; i < ARRAY_SIZE(priv->ext_irqs); i++) {
0088         if (priv->ext_irqs[i] == data->hwirq) {
0089             ret = pic32_set_ext_polarity(i, flow_type);
0090             if (ret)
0091                 return ret;
0092         }
0093     }
0094
0095     irqd_set_trigger_type(data, flow_type);
0096
0097     return IRQ_SET_MASK_OK;
0098 }
0099
0100 static void pic32_bind_evic_interrupt(int irq, int set)
0101 {
0102     writel(set, evic_base + REG_OFF_OFFSET + irq * 4);
0103 }
0104
0105 static void pic32_set_irq_priority(int irq, int priority)
0106 {
0107     u32 reg, shift;
0108
0109     reg = irq / 4;
0110     shift = (irq % 4) * 8;
0111
0112     writel(PRIORITY_MASK << shift,
0113         evic_base + PIC32_CLR(REG_IPC_OFFSET + reg * 0x10));
0114     writel(priority << shift,
0115         evic_base + PIC32_SET(REG_IPC_OFFSET + reg * 0x10));
0116 }
0117
0118 #define IRQ_REG_MASK(_hwirq, _reg, _mask)              \
0119     do {                               \
0120         _reg = _hwirq / 32;                \
0121         _mask = 1 << (_hwirq % 32);            \
0122     } while (0)
0123
0124 static int pic32_irq_domain_map(struct irq_domain *d, unsigned int virq,
0125                 irq_hw_number_t hw)
0126 {
0127     struct evic_chip_data *priv = d->host_data;
0128     struct irq_data *data;
0129     int ret;
0130     u32 iecclr, ifsclr;
0131     u32 reg, mask;
0132
0133     ret = irq_map_generic_chip(d, virq, hw);
0134     if (ret)
0135         return ret;
0136
0137     /*
0138      * Piggyback on xlate function to move to an alternate chip as necessary
0139      * at time of mapping instead of allowing the flow handler/chip to be
0140      * changed later. This requires all interrupts to be configured through
0141      * DT.
0142      */
0143     if (priv->irq_types[hw] & IRQ_TYPE_SENSE_MASK) {
0144         data = irq_domain_get_irq_data(d, virq);
0145         irqd_set_trigger_type(data, priv->irq_types[hw]);
0146         irq_setup_alt_chip(data, priv->irq_types[hw]);
0147     }
0148
0149     IRQ_REG_MASK(hw, reg, mask);
0150
0151     iecclr = PIC32_CLR(REG_IEC_OFFSET + reg * 0x10);
0152     ifsclr = PIC32_CLR(REG_IFS_OFFSET + reg * 0x10);
0153
0154     /* mask and clear flag */
0155     writel(mask, evic_base + iecclr);
0156     writel(mask, evic_base + ifsclr);
0157
0158     /* default priority is required */
0159     pic32_set_irq_priority(hw, PIC32_INT_PRI(2, 0));
0160
0161     return ret;
0162 }
0163
0164 int pic32_irq_domain_xlate(struct irq_domain *d, struct device_node *ctrlr,
0165                const u32 *intspec, unsigned int intsize,
0166                irq_hw_number_t *out_hwirq, unsigned int *out_type)
0167 {
0168     struct evic_chip_data *priv = d->host_data;
0169
0170     if (WARN_ON(intsize < 2))
0171         return -EINVAL;
0172
0173     if (WARN_ON(intspec[0] >= NR_IRQS))
0174         return -EINVAL;
0175
0176     *out_hwirq = intspec[0];
0177     *out_type = intspec[1] & IRQ_TYPE_SENSE_MASK;
0178
0179     priv->irq_types[intspec[0]] = intspec[1] & IRQ_TYPE_SENSE_MASK;
0180
0181     return 0;
0182 }
0183
0184 static const struct irq_domain_ops pic32_irq_domain_ops = {
0185     .map    = pic32_irq_domain_map,
0186     .xlate  = pic32_irq_domain_xlate,
0187 };
0188
0189 static void __init pic32_ext_irq_of_init(struct irq_domain *domain)
0190 {
0191     struct device_node *node = irq_domain_get_of_node(domain);
0192     struct evic_chip_data *priv = domain->host_data;
0193     struct property *prop;
0194     const __le32 *p;
0195     u32 hwirq;
0196     int i = 0;
0197     const char *pname = "microchip,external-irqs";
0198
0199     of_property_for_each_u32(node, pname, prop, p, hwirq) {
0200         if (i >= ARRAY_SIZE(priv->ext_irqs)) {
0201             pr_warn("More than %d external irq, skip rest\n",
0202                 ARRAY_SIZE(priv->ext_irqs));
0203             break;
0204         }
0205
0206         priv->ext_irqs[i] = hwirq;
0207         i++;
0208     }
0209 }
0210
0211 static int __init pic32_of_init(struct device_node *node,
0212                 struct device_node *parent)
0213 {
0214     struct irq_chip_generic *gc;
0215     struct evic_chip_data *priv;
0216     unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
0217     int nchips, ret;
0218     int i;
0219
0220     nchips = DIV_ROUND_UP(NR_IRQS, 32);
0221
0222     evic_base = of_iomap(node, 0);
0223     if (!evic_base)
0224         return -ENOMEM;
0225
0226     priv = kcalloc(nchips, sizeof(*priv), GFP_KERNEL);
0227     if (!priv) {
0228         ret = -ENOMEM;
0229         goto err_iounmap;
0230     }
0231
0232     evic_irq_domain = irq_domain_add_linear(node, nchips * 32,
0233                         &pic32_irq_domain_ops,
0234                         priv);
0235     if (!evic_irq_domain) {
0236         ret = -ENOMEM;
0237         goto err_free_priv;
0238     }
0239
0240     /*
0241      * The PIC32 EVIC has a linear list of irqs and the type of each
0242      * irq is determined by the hardware peripheral the EVIC is arbitrating.
0243      * These irq types are defined in the datasheet as "persistent" and
0244      * "non-persistent" which are mapped here to level and edge
0245      * respectively. To manage the different flow handler requirements of
0246      * each irq type, different chip_types are used.
0247      */
0248     ret = irq_alloc_domain_generic_chips(evic_irq_domain, 32, 2,
0249                          "evic-level", handle_level_irq,
0250                          clr, 0, 0);
0251     if (ret)
0252         goto err_domain_remove;
0253
0254     board_bind_eic_interrupt = &pic32_bind_evic_interrupt;
0255
0256     for (i = 0; i < nchips; i++) {
0257         u32 ifsclr = PIC32_CLR(REG_IFS_OFFSET + (i * 0x10));
0258         u32 iec = REG_IEC_OFFSET + (i * 0x10);
0259
0260         gc = irq_get_domain_generic_chip(evic_irq_domain, i * 32);
0261
0262         gc->reg_base = evic_base;
0263         gc->unused = 0;
0264
0265         /*
0266          * Level/persistent interrupts have a special requirement that
0267          * the condition generating the interrupt be cleared before the
0268          * interrupt flag (ifs) can be cleared. chip.irq_eoi is used to
0269          * complete the interrupt with an ack.
0270          */
0271         gc->chip_types[0].type          = IRQ_TYPE_LEVEL_MASK;
0272         gc->chip_types[0].handler       = handle_fasteoi_irq;
0273         gc->chip_types[0].regs.ack      = ifsclr;
0274         gc->chip_types[0].regs.mask     = iec;
0275         gc->chip_types[0].chip.name     = "evic-level";
0276         gc->chip_types[0].chip.irq_eoi      = irq_gc_ack_set_bit;
0277         gc->chip_types[0].chip.irq_mask     = irq_gc_mask_clr_bit;
0278         gc->chip_types[0].chip.irq_unmask   = irq_gc_mask_set_bit;
0279         gc->chip_types[0].chip.flags        = IRQCHIP_SKIP_SET_WAKE;
0280
0281         /* Edge interrupts */
0282         gc->chip_types[1].type          = IRQ_TYPE_EDGE_BOTH;
0283         gc->chip_types[1].handler       = handle_edge_irq;
0284         gc->chip_types[1].regs.ack      = ifsclr;
0285         gc->chip_types[1].regs.mask     = iec;
0286         gc->chip_types[1].chip.name     = "evic-edge";
0287         gc->chip_types[1].chip.irq_ack      = irq_gc_ack_set_bit;
0288         gc->chip_types[1].chip.irq_mask     = irq_gc_mask_clr_bit;
0289         gc->chip_types[1].chip.irq_unmask   = irq_gc_mask_set_bit;
0290         gc->chip_types[1].chip.irq_set_type = pic32_set_type_edge;
0291         gc->chip_types[1].chip.flags        = IRQCHIP_SKIP_SET_WAKE;
0292
0293         gc->private = &priv[i];
0294     }
0295
0296     irq_set_default_host(evic_irq_domain);
0297
0298     /*
0299      * External interrupts have software configurable edge polarity. These
0300      * interrupts are defined in DT allowing polarity to be configured only
0301      * for these interrupts when requested.
0302      */
0303     pic32_ext_irq_of_init(evic_irq_domain);
0304
0305     return 0;
0306
0307 err_domain_remove:
0308     irq_domain_remove(evic_irq_domain);
0309
0310 err_free_priv:
0311     kfree(priv);
0312
0313 err_iounmap:
0314     iounmap(evic_base);
0315
0316     return ret;
0317 }
0318
0319 IRQCHIP_DECLARE(pic32_evic, "microchip,pic32mzda-evic", pic32_of_init);