drivers/irqchip/irq-orion.c

0001 /*
0002  * Marvell Orion SoCs IRQ chip driver.
0003  *
0004  * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
0005  *
0006  * This file is licensed under the terms of the GNU General Public
0007  * License version 2.  This program is licensed "as is" without any
0008  * warranty of any kind, whether express or implied.
0009  */
0010
0011 #include <linux/io.h>
0012 #include <linux/irq.h>
0013 #include <linux/irqchip.h>
0014 #include <linux/of.h>
0015 #include <linux/of_address.h>
0016 #include <linux/of_irq.h>
0017 #include <asm/exception.h>
0018 #include <asm/mach/irq.h>
0019
0020 /*
0021  * Orion SoC main interrupt controller
0022  */
0023 #define ORION_IRQS_PER_CHIP     32
0024
0025 #define ORION_IRQ_CAUSE         0x00
0026 #define ORION_IRQ_MASK          0x04
0027 #define ORION_IRQ_FIQ_MASK      0x08
0028 #define ORION_IRQ_ENDP_MASK     0x0c
0029
0030 static struct irq_domain *orion_irq_domain;
0031
0032 static void
0033 __exception_irq_entry orion_handle_irq(struct pt_regs *regs)
0034 {
0035     struct irq_domain_chip_generic *dgc = orion_irq_domain->gc;
0036     int n, base = 0;
0037
0038     for (n = 0; n < dgc->num_chips; n++, base += ORION_IRQS_PER_CHIP) {
0039         struct irq_chip_generic *gc =
0040             irq_get_domain_generic_chip(orion_irq_domain, base);
0041         u32 stat = readl_relaxed(gc->reg_base + ORION_IRQ_CAUSE) &
0042             gc->mask_cache;
0043         while (stat) {
0044             u32 hwirq = __fls(stat);
0045             generic_handle_domain_irq(orion_irq_domain,
0046                           gc->irq_base + hwirq);
0047             stat &= ~(1 << hwirq);
0048         }
0049     }
0050 }
0051
0052 static int __init orion_irq_init(struct device_node *np,
0053                  struct device_node *parent)
0054 {
0055     unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
0056     int n, ret, base, num_chips = 0;
0057     struct resource r;
0058
0059     /* count number of irq chips by valid reg addresses */
0060     while (of_address_to_resource(np, num_chips, &r) == 0)
0061         num_chips++;
0062
0063     orion_irq_domain = irq_domain_add_linear(np,
0064                 num_chips * ORION_IRQS_PER_CHIP,
0065                 &irq_generic_chip_ops, NULL);
0066     if (!orion_irq_domain)
0067         panic("%pOFn: unable to add irq domain\n", np);
0068
0069     ret = irq_alloc_domain_generic_chips(orion_irq_domain,
0070                 ORION_IRQS_PER_CHIP, 1, np->full_name,
0071                 handle_level_irq, clr, 0,
0072                 IRQ_GC_INIT_MASK_CACHE);
0073     if (ret)
0074         panic("%pOFn: unable to alloc irq domain gc\n", np);
0075
0076     for (n = 0, base = 0; n < num_chips; n++, base += ORION_IRQS_PER_CHIP) {
0077         struct irq_chip_generic *gc =
0078             irq_get_domain_generic_chip(orion_irq_domain, base);
0079
0080         of_address_to_resource(np, n, &r);
0081
0082         if (!request_mem_region(r.start, resource_size(&r), np->name))
0083             panic("%pOFn: unable to request mem region %d",
0084                   np, n);
0085
0086         gc->reg_base = ioremap(r.start, resource_size(&r));
0087         if (!gc->reg_base)
0088             panic("%pOFn: unable to map resource %d", np, n);
0089
0090         gc->chip_types[0].regs.mask = ORION_IRQ_MASK;
0091         gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
0092         gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
0093
0094         /* mask all interrupts */
0095         writel(0, gc->reg_base + ORION_IRQ_MASK);
0096     }
0097
0098     set_handle_irq(orion_handle_irq);
0099     return 0;
0100 }
0101 IRQCHIP_DECLARE(orion_intc, "marvell,orion-intc", orion_irq_init);
0102
0103 /*
0104  * Orion SoC bridge interrupt controller
0105  */
0106 #define ORION_BRIDGE_IRQ_CAUSE  0x00
0107 #define ORION_BRIDGE_IRQ_MASK   0x04
0108
0109 static void orion_bridge_irq_handler(struct irq_desc *desc)
0110 {
0111     struct irq_domain *d = irq_desc_get_handler_data(desc);
0112
0113     struct irq_chip_generic *gc = irq_get_domain_generic_chip(d, 0);
0114     u32 stat = readl_relaxed(gc->reg_base + ORION_BRIDGE_IRQ_CAUSE) &
0115            gc->mask_cache;
0116
0117     while (stat) {
0118         u32 hwirq = __fls(stat);
0119
0120         generic_handle_domain_irq(d, gc->irq_base + hwirq);
0121         stat &= ~(1 << hwirq);
0122     }
0123 }
0124
0125 /*
0126  * Bridge IRQ_CAUSE is asserted regardless of IRQ_MASK register.
0127  * To avoid interrupt events on stale irqs, we clear them before unmask.
0128  */
0129 static unsigned int orion_bridge_irq_startup(struct irq_data *d)
0130 {
0131     struct irq_chip_type *ct = irq_data_get_chip_type(d);
0132
0133     ct->chip.irq_ack(d);
0134     ct->chip.irq_unmask(d);
0135     return 0;
0136 }
0137
0138 static int __init orion_bridge_irq_init(struct device_node *np,
0139                     struct device_node *parent)
0140 {
0141     unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
0142     struct resource r;
0143     struct irq_domain *domain;
0144     struct irq_chip_generic *gc;
0145     int ret, irq, nrirqs = 32;
0146
0147     /* get optional number of interrupts provided */
0148     of_property_read_u32(np, "marvell,#interrupts", &nrirqs);
0149
0150     domain = irq_domain_add_linear(np, nrirqs,
0151                        &irq_generic_chip_ops, NULL);
0152     if (!domain) {
0153         pr_err("%pOFn: unable to add irq domain\n", np);
0154         return -ENOMEM;
0155     }
0156
0157     ret = irq_alloc_domain_generic_chips(domain, nrirqs, 1, np->name,
0158                  handle_edge_irq, clr, 0, IRQ_GC_INIT_MASK_CACHE);
0159     if (ret) {
0160         pr_err("%pOFn: unable to alloc irq domain gc\n", np);
0161         return ret;
0162     }
0163
0164     ret = of_address_to_resource(np, 0, &r);
0165     if (ret) {
0166         pr_err("%pOFn: unable to get resource\n", np);
0167         return ret;
0168     }
0169
0170     if (!request_mem_region(r.start, resource_size(&r), np->name)) {
0171         pr_err("%s: unable to request mem region\n", np->name);
0172         return -ENOMEM;
0173     }
0174
0175     /* Map the parent interrupt for the chained handler */
0176     irq = irq_of_parse_and_map(np, 0);
0177     if (irq <= 0) {
0178         pr_err("%pOFn: unable to parse irq\n", np);
0179         return -EINVAL;
0180     }
0181
0182     gc = irq_get_domain_generic_chip(domain, 0);
0183     gc->reg_base = ioremap(r.start, resource_size(&r));
0184     if (!gc->reg_base) {
0185         pr_err("%pOFn: unable to map resource\n", np);
0186         return -ENOMEM;
0187     }
0188
0189     gc->chip_types[0].regs.ack = ORION_BRIDGE_IRQ_CAUSE;
0190     gc->chip_types[0].regs.mask = ORION_BRIDGE_IRQ_MASK;
0191     gc->chip_types[0].chip.irq_startup = orion_bridge_irq_startup;
0192     gc->chip_types[0].chip.irq_ack = irq_gc_ack_clr_bit;
0193     gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
0194     gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
0195
0196     /* mask and clear all interrupts */
0197     writel(0, gc->reg_base + ORION_BRIDGE_IRQ_MASK);
0198     writel(0, gc->reg_base + ORION_BRIDGE_IRQ_CAUSE);
0199
0200     irq_set_chained_handler_and_data(irq, orion_bridge_irq_handler,
0201                      domain);
0202
0203     return 0;
0204 }
0205 IRQCHIP_DECLARE(orion_bridge_intc,
0206         "marvell,orion-bridge-intc", orion_bridge_irq_init);