drivers/irqchip/irq-ompic.c

0001 /*
0002  * Open Multi-Processor Interrupt Controller driver
0003  *
0004  * Copyright (C) 2014 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
0005  * Copyright (C) 2017 Stafford Horne <shorne@gmail.com>
0006  *
0007  * This file is licensed under the terms of the GNU General Public License
0008  * version 2.  This program is licensed "as is" without any warranty of any
0009  * kind, whether express or implied.
0010  *
0011  * The ompic device handles IPI communication between cores in multi-core
0012  * OpenRISC systems.
0013  *
0014  * Registers
0015  *
0016  * For each CPU the ompic has 2 registers. The control register for sending
0017  * and acking IPIs and the status register for receiving IPIs. The register
0018  * layouts are as follows:
0019  *
0020  *  Control register
0021  *  +---------+---------+----------+---------+
0022  *  | 31      | 30      | 29 .. 16 | 15 .. 0 |
0023  *  ----------+---------+----------+----------
0024  *  | IRQ ACK | IRQ GEN | DST CORE | DATA    |
0025  *  +---------+---------+----------+---------+
0026  *
0027  *  Status register
0028  *  +----------+-------------+----------+---------+
0029  *  | 31       | 30          | 29 .. 16 | 15 .. 0 |
0030  *  -----------+-------------+----------+---------+
0031  *  | Reserved | IRQ Pending | SRC CORE | DATA    |
0032  *  +----------+-------------+----------+---------+
0033  *
0034  * Architecture
0035  *
0036  * - The ompic generates a level interrupt to the CPU PIC when a message is
0037  *   ready.  Messages are delivered via the memory bus.
0038  * - The ompic does not have any interrupt input lines.
0039  * - The ompic is wired to the same irq line on each core.
0040  * - Devices are wired to the same irq line on each core.
0041  *
0042  *   +---------+                         +---------+
0043  *   | CPU     |                         | CPU     |
0044  *   |  Core 0 |<==\ (memory access) /==>|  Core 1 |
0045  *   |  [ PIC ]|   |                 |   |  [ PIC ]|
0046  *   +----^-^--+   |                 |   +----^-^--+
0047  *        | |      v                 v        | |
0048  *   <====|=|=================================|=|==> (memory bus)
0049  *        | |      ^                  ^       | |
0050  *  (ipi  | +------|---------+--------|-------|-+ (device irq)
0051  *   irq  |        |         |        |       |
0052  *  core0)| +------|---------|--------|-------+ (ipi irq core1)
0053  *        | |      |         |        |
0054  *   +----o-o-+    |    +--------+    |
0055  *   | ompic  |<===/    | Device |<===/
0056  *   |  IPI   |         +--------+
0057  *   +--------+*
0058  *
0059  */
0060
0061 #include <linux/io.h>
0062 #include <linux/ioport.h>
0063 #include <linux/interrupt.h>
0064 #include <linux/smp.h>
0065 #include <linux/of.h>
0066 #include <linux/of_irq.h>
0067 #include <linux/of_address.h>
0068
0069 #include <linux/irqchip.h>
0070
0071 #define OMPIC_CPUBYTES      8
0072 #define OMPIC_CTRL(cpu)     (0x0 + (cpu * OMPIC_CPUBYTES))
0073 #define OMPIC_STAT(cpu)     (0x4 + (cpu * OMPIC_CPUBYTES))
0074
0075 #define OMPIC_CTRL_IRQ_ACK  (1 << 31)
0076 #define OMPIC_CTRL_IRQ_GEN  (1 << 30)
0077 #define OMPIC_CTRL_DST(cpu) (((cpu) & 0x3fff) << 16)
0078
0079 #define OMPIC_STAT_IRQ_PENDING  (1 << 30)
0080
0081 #define OMPIC_DATA(x)       ((x) & 0xffff)
0082
0083 DEFINE_PER_CPU(unsigned long, ops);
0084
0085 static void __iomem *ompic_base;
0086
0087 static inline u32 ompic_readreg(void __iomem *base, loff_t offset)
0088 {
0089     return ioread32be(base + offset);
0090 }
0091
0092 static void ompic_writereg(void __iomem *base, loff_t offset, u32 data)
0093 {
0094     iowrite32be(data, base + offset);
0095 }
0096
0097 static void ompic_raise_softirq(const struct cpumask *mask,
0098                 unsigned int ipi_msg)
0099 {
0100     unsigned int dst_cpu;
0101     unsigned int src_cpu = smp_processor_id();
0102
0103     for_each_cpu(dst_cpu, mask) {
0104         set_bit(ipi_msg, &per_cpu(ops, dst_cpu));
0105
0106         /*
0107          * On OpenRISC the atomic set_bit() call implies a memory
0108          * barrier.  Otherwise we would need: smp_wmb(); paired
0109          * with the read in ompic_ipi_handler.
0110          */
0111
0112         ompic_writereg(ompic_base, OMPIC_CTRL(src_cpu),
0113                    OMPIC_CTRL_IRQ_GEN |
0114                    OMPIC_CTRL_DST(dst_cpu) |
0115                    OMPIC_DATA(1));
0116     }
0117 }
0118
0119 static irqreturn_t ompic_ipi_handler(int irq, void *dev_id)
0120 {
0121     unsigned int cpu = smp_processor_id();
0122     unsigned long *pending_ops = &per_cpu(ops, cpu);
0123     unsigned long ops;
0124
0125     ompic_writereg(ompic_base, OMPIC_CTRL(cpu), OMPIC_CTRL_IRQ_ACK);
0126     while ((ops = xchg(pending_ops, 0)) != 0) {
0127
0128         /*
0129          * On OpenRISC the atomic xchg() call implies a memory
0130          * barrier.  Otherwise we may need an smp_rmb(); paired
0131          * with the write in ompic_raise_softirq.
0132          */
0133
0134         do {
0135             unsigned long ipi_msg;
0136
0137             ipi_msg = __ffs(ops);
0138             ops &= ~(1UL << ipi_msg);
0139
0140             handle_IPI(ipi_msg);
0141         } while (ops);
0142     }
0143
0144     return IRQ_HANDLED;
0145 }
0146
0147 static int __init ompic_of_init(struct device_node *node,
0148                 struct device_node *parent)
0149 {
0150     struct resource res;
0151     int irq;
0152     int ret;
0153
0154     /* Validate the DT */
0155     if (ompic_base) {
0156         pr_err("ompic: duplicate ompic's are not supported");
0157         return -EEXIST;
0158     }
0159
0160     if (of_address_to_resource(node, 0, &res)) {
0161         pr_err("ompic: reg property requires an address and size");
0162         return -EINVAL;
0163     }
0164
0165     if (resource_size(&res) < (num_possible_cpus() * OMPIC_CPUBYTES)) {
0166         pr_err("ompic: reg size, currently %d must be at least %d",
0167             resource_size(&res),
0168             (num_possible_cpus() * OMPIC_CPUBYTES));
0169         return -EINVAL;
0170     }
0171
0172     /* Setup the device */
0173     ompic_base = ioremap(res.start, resource_size(&res));
0174     if (!ompic_base) {
0175         pr_err("ompic: unable to map registers");
0176         return -ENOMEM;
0177     }
0178
0179     irq = irq_of_parse_and_map(node, 0);
0180     if (irq <= 0) {
0181         pr_err("ompic: unable to parse device irq");
0182         ret = -EINVAL;
0183         goto out_unmap;
0184     }
0185
0186     ret = request_irq(irq, ompic_ipi_handler, IRQF_PERCPU,
0187                 "ompic_ipi", NULL);
0188     if (ret)
0189         goto out_irq_disp;
0190
0191     set_smp_cross_call(ompic_raise_softirq);
0192
0193     return 0;
0194
0195 out_irq_disp:
0196     irq_dispose_mapping(irq);
0197 out_unmap:
0198     iounmap(ompic_base);
0199     ompic_base = NULL;
0200     return ret;
0201 }
0202 IRQCHIP_DECLARE(ompic, "openrisc,ompic", ompic_of_init);