drivers/irqchip/irq-mxs.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
0004  * Copyright (C) 2014 Oleksij Rempel <linux@rempel-privat.de>
0005  *  Add Alphascale ASM9260 support.
0006  */
0007
0008 #include <linux/kernel.h>
0009 #include <linux/init.h>
0010 #include <linux/irq.h>
0011 #include <linux/irqchip.h>
0012 #include <linux/irqdomain.h>
0013 #include <linux/io.h>
0014 #include <linux/of.h>
0015 #include <linux/of_address.h>
0016 #include <linux/of_irq.h>
0017 #include <linux/stmp_device.h>
0018 #include <asm/exception.h>
0019
0020 #include "alphascale_asm9260-icoll.h"
0021
0022 /*
0023  * this device provide 4 offsets for each register:
0024  * 0x0 - plain read write mode
0025  * 0x4 - set mode, OR logic.
0026  * 0x8 - clr mode, XOR logic.
0027  * 0xc - togle mode.
0028  */
0029 #define SET_REG 4
0030 #define CLR_REG 8
0031
0032 #define HW_ICOLL_VECTOR             0x0000
0033 #define HW_ICOLL_LEVELACK           0x0010
0034 #define HW_ICOLL_CTRL               0x0020
0035 #define HW_ICOLL_STAT_OFFSET            0x0070
0036 #define HW_ICOLL_INTERRUPT0         0x0120
0037 #define HW_ICOLL_INTERRUPTn(n)          ((n) * 0x10)
0038 #define BM_ICOLL_INTR_ENABLE            BIT(2)
0039 #define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0   0x1
0040
0041 #define ICOLL_NUM_IRQS      128
0042
0043 enum icoll_type {
0044     ICOLL,
0045     ASM9260_ICOLL,
0046 };
0047
0048 struct icoll_priv {
0049     void __iomem *vector;
0050     void __iomem *levelack;
0051     void __iomem *ctrl;
0052     void __iomem *stat;
0053     void __iomem *intr;
0054     void __iomem *clear;
0055     enum icoll_type type;
0056 };
0057
0058 static struct icoll_priv icoll_priv;
0059 static struct irq_domain *icoll_domain;
0060
0061 /* calculate bit offset depending on number of interrupt per register */
0062 static u32 icoll_intr_bitshift(struct irq_data *d, u32 bit)
0063 {
0064     /*
0065      * mask lower part of hwirq to convert it
0066      * in 0, 1, 2 or 3 and then multiply it by 8 (or shift by 3)
0067      */
0068     return bit << ((d->hwirq & 3) << 3);
0069 }
0070
0071 /* calculate mem offset depending on number of interrupt per register */
0072 static void __iomem *icoll_intr_reg(struct irq_data *d)
0073 {
0074     /* offset = hwirq / intr_per_reg * 0x10 */
0075     return icoll_priv.intr + ((d->hwirq >> 2) * 0x10);
0076 }
0077
0078 static void icoll_ack_irq(struct irq_data *d)
0079 {
0080     /*
0081      * The Interrupt Collector is able to prioritize irqs.
0082      * Currently only level 0 is used. So acking can use
0083      * BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 unconditionally.
0084      */
0085     __raw_writel(BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0,
0086             icoll_priv.levelack);
0087 }
0088
0089 static void icoll_mask_irq(struct irq_data *d)
0090 {
0091     __raw_writel(BM_ICOLL_INTR_ENABLE,
0092             icoll_priv.intr + CLR_REG + HW_ICOLL_INTERRUPTn(d->hwirq));
0093 }
0094
0095 static void icoll_unmask_irq(struct irq_data *d)
0096 {
0097     __raw_writel(BM_ICOLL_INTR_ENABLE,
0098             icoll_priv.intr + SET_REG + HW_ICOLL_INTERRUPTn(d->hwirq));
0099 }
0100
0101 static void asm9260_mask_irq(struct irq_data *d)
0102 {
0103     __raw_writel(icoll_intr_bitshift(d, BM_ICOLL_INTR_ENABLE),
0104             icoll_intr_reg(d) + CLR_REG);
0105 }
0106
0107 static void asm9260_unmask_irq(struct irq_data *d)
0108 {
0109     __raw_writel(ASM9260_BM_CLEAR_BIT(d->hwirq),
0110              icoll_priv.clear +
0111              ASM9260_HW_ICOLL_CLEARn(d->hwirq));
0112
0113     __raw_writel(icoll_intr_bitshift(d, BM_ICOLL_INTR_ENABLE),
0114             icoll_intr_reg(d) + SET_REG);
0115 }
0116
0117 static struct irq_chip mxs_icoll_chip = {
0118     .irq_ack = icoll_ack_irq,
0119     .irq_mask = icoll_mask_irq,
0120     .irq_unmask = icoll_unmask_irq,
0121     .flags = IRQCHIP_MASK_ON_SUSPEND |
0122          IRQCHIP_SKIP_SET_WAKE,
0123 };
0124
0125 static struct irq_chip asm9260_icoll_chip = {
0126     .irq_ack = icoll_ack_irq,
0127     .irq_mask = asm9260_mask_irq,
0128     .irq_unmask = asm9260_unmask_irq,
0129     .flags = IRQCHIP_MASK_ON_SUSPEND |
0130          IRQCHIP_SKIP_SET_WAKE,
0131 };
0132
0133 asmlinkage void __exception_irq_entry icoll_handle_irq(struct pt_regs *regs)
0134 {
0135     u32 irqnr;
0136
0137     irqnr = __raw_readl(icoll_priv.stat);
0138     __raw_writel(irqnr, icoll_priv.vector);
0139     generic_handle_domain_irq(icoll_domain, irqnr);
0140 }
0141
0142 static int icoll_irq_domain_map(struct irq_domain *d, unsigned int virq,
0143                 irq_hw_number_t hw)
0144 {
0145     struct irq_chip *chip;
0146
0147     if (icoll_priv.type == ICOLL)
0148         chip = &mxs_icoll_chip;
0149     else
0150         chip = &asm9260_icoll_chip;
0151
0152     irq_set_chip_and_handler(virq, chip, handle_level_irq);
0153
0154     return 0;
0155 }
0156
0157 static const struct irq_domain_ops icoll_irq_domain_ops = {
0158     .map = icoll_irq_domain_map,
0159     .xlate = irq_domain_xlate_onecell,
0160 };
0161
0162 static void __init icoll_add_domain(struct device_node *np,
0163               int num)
0164 {
0165     icoll_domain = irq_domain_add_linear(np, num,
0166                          &icoll_irq_domain_ops, NULL);
0167
0168     if (!icoll_domain)
0169         panic("%pOF: unable to create irq domain", np);
0170 }
0171
0172 static void __iomem * __init icoll_init_iobase(struct device_node *np)
0173 {
0174     void __iomem *icoll_base;
0175
0176     icoll_base = of_io_request_and_map(np, 0, np->name);
0177     if (IS_ERR(icoll_base))
0178         panic("%pOF: unable to map resource", np);
0179     return icoll_base;
0180 }
0181
0182 static int __init icoll_of_init(struct device_node *np,
0183               struct device_node *interrupt_parent)
0184 {
0185     void __iomem *icoll_base;
0186
0187     icoll_priv.type = ICOLL;
0188
0189     icoll_base      = icoll_init_iobase(np);
0190     icoll_priv.vector   = icoll_base + HW_ICOLL_VECTOR;
0191     icoll_priv.levelack = icoll_base + HW_ICOLL_LEVELACK;
0192     icoll_priv.ctrl     = icoll_base + HW_ICOLL_CTRL;
0193     icoll_priv.stat     = icoll_base + HW_ICOLL_STAT_OFFSET;
0194     icoll_priv.intr     = icoll_base + HW_ICOLL_INTERRUPT0;
0195     icoll_priv.clear    = NULL;
0196
0197     /*
0198      * Interrupt Collector reset, which initializes the priority
0199      * for each irq to level 0.
0200      */
0201     stmp_reset_block(icoll_priv.ctrl);
0202
0203     icoll_add_domain(np, ICOLL_NUM_IRQS);
0204
0205     return 0;
0206 }
0207 IRQCHIP_DECLARE(mxs, "fsl,icoll", icoll_of_init);
0208
0209 static int __init asm9260_of_init(struct device_node *np,
0210               struct device_node *interrupt_parent)
0211 {
0212     void __iomem *icoll_base;
0213     int i;
0214
0215     icoll_priv.type = ASM9260_ICOLL;
0216
0217     icoll_base = icoll_init_iobase(np);
0218     icoll_priv.vector   = icoll_base + ASM9260_HW_ICOLL_VECTOR;
0219     icoll_priv.levelack = icoll_base + ASM9260_HW_ICOLL_LEVELACK;
0220     icoll_priv.ctrl     = icoll_base + ASM9260_HW_ICOLL_CTRL;
0221     icoll_priv.stat     = icoll_base + ASM9260_HW_ICOLL_STAT_OFFSET;
0222     icoll_priv.intr     = icoll_base + ASM9260_HW_ICOLL_INTERRUPT0;
0223     icoll_priv.clear    = icoll_base + ASM9260_HW_ICOLL_CLEAR0;
0224
0225     writel_relaxed(ASM9260_BM_CTRL_IRQ_ENABLE,
0226             icoll_priv.ctrl);
0227     /*
0228      * ASM9260 don't provide reset bit. So, we need to set level 0
0229      * manually.
0230      */
0231     for (i = 0; i < 16 * 0x10; i += 0x10)
0232         writel(0, icoll_priv.intr + i);
0233
0234     icoll_add_domain(np, ASM9260_NUM_IRQS);
0235     set_handle_irq(icoll_handle_irq);
0236
0237     return 0;
0238 }
0239 IRQCHIP_DECLARE(asm9260, "alphascale,asm9260-icoll", asm9260_of_init);