drivers/irqchip/irq-mvebu-odmi.c

0001 /*
0002  * Copyright (C) 2016 Marvell
0003  *
0004  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
0005  *
0006  * This file is licensed under the terms of the GNU General Public
0007  * License version 2.  This program is licensed "as is" without any
0008  * warranty of any kind, whether express or implied.
0009  */
0010
0011 #define pr_fmt(fmt) "GIC-ODMI: " fmt
0012
0013 #include <linux/irq.h>
0014 #include <linux/irqchip.h>
0015 #include <linux/irqdomain.h>
0016 #include <linux/kernel.h>
0017 #include <linux/msi.h>
0018 #include <linux/of_address.h>
0019 #include <linux/slab.h>
0020 #include <dt-bindings/interrupt-controller/arm-gic.h>
0021
0022 #define GICP_ODMIN_SET          0x40
0023 #define   GICP_ODMI_INT_NUM_SHIFT   12
0024 #define GICP_ODMIN_GM_EP_R0     0x110
0025 #define GICP_ODMIN_GM_EP_R1     0x114
0026 #define GICP_ODMIN_GM_EA_R0     0x108
0027 #define GICP_ODMIN_GM_EA_R1     0x118
0028
0029 /*
0030  * We don't support the group events, so we simply have 8 interrupts
0031  * per frame.
0032  */
0033 #define NODMIS_SHIFT        3
0034 #define NODMIS_PER_FRAME    (1 << NODMIS_SHIFT)
0035 #define NODMIS_MASK     (NODMIS_PER_FRAME - 1)
0036
0037 struct odmi_data {
0038     struct resource res;
0039     void __iomem *base;
0040     unsigned int spi_base;
0041 };
0042
0043 static struct odmi_data *odmis;
0044 static unsigned long *odmis_bm;
0045 static unsigned int odmis_count;
0046
0047 /* Protects odmis_bm */
0048 static DEFINE_SPINLOCK(odmis_bm_lock);
0049
0050 static void odmi_compose_msi_msg(struct irq_data *d, struct msi_msg *msg)
0051 {
0052     struct odmi_data *odmi;
0053     phys_addr_t addr;
0054     unsigned int odmin;
0055
0056     if (WARN_ON(d->hwirq >= odmis_count * NODMIS_PER_FRAME))
0057         return;
0058
0059     odmi = &odmis[d->hwirq >> NODMIS_SHIFT];
0060     odmin = d->hwirq & NODMIS_MASK;
0061
0062     addr = odmi->res.start + GICP_ODMIN_SET;
0063
0064     msg->address_hi = upper_32_bits(addr);
0065     msg->address_lo = lower_32_bits(addr);
0066     msg->data = odmin << GICP_ODMI_INT_NUM_SHIFT;
0067 }
0068
0069 static struct irq_chip odmi_irq_chip = {
0070     .name           = "ODMI",
0071     .irq_mask       = irq_chip_mask_parent,
0072     .irq_unmask     = irq_chip_unmask_parent,
0073     .irq_eoi        = irq_chip_eoi_parent,
0074     .irq_set_affinity   = irq_chip_set_affinity_parent,
0075     .irq_compose_msi_msg    = odmi_compose_msi_msg,
0076 };
0077
0078 static int odmi_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
0079                  unsigned int nr_irqs, void *args)
0080 {
0081     struct odmi_data *odmi = NULL;
0082     struct irq_fwspec fwspec;
0083     struct irq_data *d;
0084     unsigned int hwirq, odmin;
0085     int ret;
0086
0087     spin_lock(&odmis_bm_lock);
0088     hwirq = find_first_zero_bit(odmis_bm, NODMIS_PER_FRAME * odmis_count);
0089     if (hwirq >= NODMIS_PER_FRAME * odmis_count) {
0090         spin_unlock(&odmis_bm_lock);
0091         return -ENOSPC;
0092     }
0093
0094     __set_bit(hwirq, odmis_bm);
0095     spin_unlock(&odmis_bm_lock);
0096
0097     odmi = &odmis[hwirq >> NODMIS_SHIFT];
0098     odmin = hwirq & NODMIS_MASK;
0099
0100     fwspec.fwnode = domain->parent->fwnode;
0101     fwspec.param_count = 3;
0102     fwspec.param[0] = GIC_SPI;
0103     fwspec.param[1] = odmi->spi_base - 32 + odmin;
0104     fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
0105
0106     ret = irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
0107     if (ret) {
0108         pr_err("Cannot allocate parent IRQ\n");
0109         spin_lock(&odmis_bm_lock);
0110         __clear_bit(odmin, odmis_bm);
0111         spin_unlock(&odmis_bm_lock);
0112         return ret;
0113     }
0114
0115     /* Configure the interrupt line to be edge */
0116     d = irq_domain_get_irq_data(domain->parent, virq);
0117     d->chip->irq_set_type(d, IRQ_TYPE_EDGE_RISING);
0118
0119     irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
0120                       &odmi_irq_chip, NULL);
0121
0122     return 0;
0123 }
0124
0125 static void odmi_irq_domain_free(struct irq_domain *domain,
0126                  unsigned int virq, unsigned int nr_irqs)
0127 {
0128     struct irq_data *d = irq_domain_get_irq_data(domain, virq);
0129
0130     if (d->hwirq >= odmis_count * NODMIS_PER_FRAME) {
0131         pr_err("Failed to teardown msi. Invalid hwirq %lu\n", d->hwirq);
0132         return;
0133     }
0134
0135     irq_domain_free_irqs_parent(domain, virq, nr_irqs);
0136
0137     /* Actually free the MSI */
0138     spin_lock(&odmis_bm_lock);
0139     __clear_bit(d->hwirq, odmis_bm);
0140     spin_unlock(&odmis_bm_lock);
0141 }
0142
0143 static const struct irq_domain_ops odmi_domain_ops = {
0144     .alloc  = odmi_irq_domain_alloc,
0145     .free   = odmi_irq_domain_free,
0146 };
0147
0148 static struct irq_chip odmi_msi_irq_chip = {
0149     .name   = "ODMI",
0150 };
0151
0152 static struct msi_domain_ops odmi_msi_ops = {
0153 };
0154
0155 static struct msi_domain_info odmi_msi_domain_info = {
0156     .flags  = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS),
0157     .ops    = &odmi_msi_ops,
0158     .chip   = &odmi_msi_irq_chip,
0159 };
0160
0161 static int __init mvebu_odmi_init(struct device_node *node,
0162                   struct device_node *parent)
0163 {
0164     struct irq_domain *inner_domain, *plat_domain;
0165     int ret, i;
0166
0167     if (of_property_read_u32(node, "marvell,odmi-frames", &odmis_count))
0168         return -EINVAL;
0169
0170     odmis = kcalloc(odmis_count, sizeof(struct odmi_data), GFP_KERNEL);
0171     if (!odmis)
0172         return -ENOMEM;
0173
0174     odmis_bm = bitmap_zalloc(odmis_count * NODMIS_PER_FRAME, GFP_KERNEL);
0175     if (!odmis_bm) {
0176         ret = -ENOMEM;
0177         goto err_alloc;
0178     }
0179
0180     for (i = 0; i < odmis_count; i++) {
0181         struct odmi_data *odmi = &odmis[i];
0182
0183         ret = of_address_to_resource(node, i, &odmi->res);
0184         if (ret)
0185             goto err_unmap;
0186
0187         odmi->base = of_io_request_and_map(node, i, "odmi");
0188         if (IS_ERR(odmi->base)) {
0189             ret = PTR_ERR(odmi->base);
0190             goto err_unmap;
0191         }
0192
0193         if (of_property_read_u32_index(node, "marvell,spi-base",
0194                            i, &odmi->spi_base)) {
0195             ret = -EINVAL;
0196             goto err_unmap;
0197         }
0198     }
0199
0200     inner_domain = irq_domain_create_linear(of_node_to_fwnode(node),
0201                         odmis_count * NODMIS_PER_FRAME,
0202                         &odmi_domain_ops, NULL);
0203     if (!inner_domain) {
0204         ret = -ENOMEM;
0205         goto err_unmap;
0206     }
0207
0208     inner_domain->parent = irq_find_host(parent);
0209
0210     plat_domain = platform_msi_create_irq_domain(of_node_to_fwnode(node),
0211                              &odmi_msi_domain_info,
0212                              inner_domain);
0213     if (!plat_domain) {
0214         ret = -ENOMEM;
0215         goto err_remove_inner;
0216     }
0217
0218     return 0;
0219
0220 err_remove_inner:
0221     irq_domain_remove(inner_domain);
0222 err_unmap:
0223     for (i = 0; i < odmis_count; i++) {
0224         struct odmi_data *odmi = &odmis[i];
0225
0226         if (odmi->base && !IS_ERR(odmi->base))
0227             iounmap(odmis[i].base);
0228     }
0229     bitmap_free(odmis_bm);
0230 err_alloc:
0231     kfree(odmis);
0232     return ret;
0233 }
0234
0235 IRQCHIP_DECLARE(mvebu_odmi, "marvell,odmi-controller", mvebu_odmi_init);