drivers/irqchip/irq-mvebu-gicp.c

0001 /*
0002  * Copyright (C) 2017 Marvell
0003  *
0004  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
0005  *
0006  * This file is licensed under the terms of the GNU General Public
0007  * License version 2. This program is licensed "as is" without any
0008  * warranty of any kind, whether express or implied.
0009  */
0010
0011 #include <linux/io.h>
0012 #include <linux/irq.h>
0013 #include <linux/irqdomain.h>
0014 #include <linux/msi.h>
0015 #include <linux/of.h>
0016 #include <linux/of_irq.h>
0017 #include <linux/of_platform.h>
0018 #include <linux/platform_device.h>
0019
0020 #include <dt-bindings/interrupt-controller/arm-gic.h>
0021
0022 #define GICP_SETSPI_NSR_OFFSET  0x0
0023 #define GICP_CLRSPI_NSR_OFFSET  0x8
0024
0025 struct mvebu_gicp_spi_range {
0026     unsigned int start;
0027     unsigned int count;
0028 };
0029
0030 struct mvebu_gicp {
0031     struct mvebu_gicp_spi_range *spi_ranges;
0032     unsigned int spi_ranges_cnt;
0033     unsigned int spi_cnt;
0034     unsigned long *spi_bitmap;
0035     spinlock_t spi_lock;
0036     struct resource *res;
0037     struct device *dev;
0038 };
0039
0040 static int gicp_idx_to_spi(struct mvebu_gicp *gicp, int idx)
0041 {
0042     int i;
0043
0044     for (i = 0; i < gicp->spi_ranges_cnt; i++) {
0045         struct mvebu_gicp_spi_range *r = &gicp->spi_ranges[i];
0046
0047         if (idx < r->count)
0048             return r->start + idx;
0049
0050         idx -= r->count;
0051     }
0052
0053     return -EINVAL;
0054 }
0055
0056 static void gicp_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
0057 {
0058     struct mvebu_gicp *gicp = data->chip_data;
0059     phys_addr_t setspi = gicp->res->start + GICP_SETSPI_NSR_OFFSET;
0060     phys_addr_t clrspi = gicp->res->start + GICP_CLRSPI_NSR_OFFSET;
0061
0062     msg[0].data = data->hwirq;
0063     msg[0].address_lo = lower_32_bits(setspi);
0064     msg[0].address_hi = upper_32_bits(setspi);
0065     msg[1].data = data->hwirq;
0066     msg[1].address_lo = lower_32_bits(clrspi);
0067     msg[1].address_hi = upper_32_bits(clrspi);
0068 }
0069
0070 static struct irq_chip gicp_irq_chip = {
0071     .name           = "GICP",
0072     .irq_mask       = irq_chip_mask_parent,
0073     .irq_unmask     = irq_chip_unmask_parent,
0074     .irq_eoi        = irq_chip_eoi_parent,
0075     .irq_set_affinity   = irq_chip_set_affinity_parent,
0076     .irq_set_type       = irq_chip_set_type_parent,
0077     .irq_compose_msi_msg    = gicp_compose_msi_msg,
0078 };
0079
0080 static int gicp_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
0081                  unsigned int nr_irqs, void *args)
0082 {
0083     struct mvebu_gicp *gicp = domain->host_data;
0084     struct irq_fwspec fwspec;
0085     unsigned int hwirq;
0086     int ret;
0087
0088     spin_lock(&gicp->spi_lock);
0089     hwirq = find_first_zero_bit(gicp->spi_bitmap, gicp->spi_cnt);
0090     if (hwirq == gicp->spi_cnt) {
0091         spin_unlock(&gicp->spi_lock);
0092         return -ENOSPC;
0093     }
0094     __set_bit(hwirq, gicp->spi_bitmap);
0095     spin_unlock(&gicp->spi_lock);
0096
0097     fwspec.fwnode = domain->parent->fwnode;
0098     fwspec.param_count = 3;
0099     fwspec.param[0] = GIC_SPI;
0100     fwspec.param[1] = gicp_idx_to_spi(gicp, hwirq) - 32;
0101     /*
0102      * Assume edge rising for now, it will be properly set when
0103      * ->set_type() is called
0104      */
0105     fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
0106
0107     ret = irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
0108     if (ret) {
0109         dev_err(gicp->dev, "Cannot allocate parent IRQ\n");
0110         goto free_hwirq;
0111     }
0112
0113     ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
0114                         &gicp_irq_chip, gicp);
0115     if (ret)
0116         goto free_irqs_parent;
0117
0118     return 0;
0119
0120 free_irqs_parent:
0121     irq_domain_free_irqs_parent(domain, virq, nr_irqs);
0122 free_hwirq:
0123     spin_lock(&gicp->spi_lock);
0124     __clear_bit(hwirq, gicp->spi_bitmap);
0125     spin_unlock(&gicp->spi_lock);
0126     return ret;
0127 }
0128
0129 static void gicp_irq_domain_free(struct irq_domain *domain,
0130                  unsigned int virq, unsigned int nr_irqs)
0131 {
0132     struct mvebu_gicp *gicp = domain->host_data;
0133     struct irq_data *d = irq_domain_get_irq_data(domain, virq);
0134
0135     if (d->hwirq >= gicp->spi_cnt) {
0136         dev_err(gicp->dev, "Invalid hwirq %lu\n", d->hwirq);
0137         return;
0138     }
0139
0140     irq_domain_free_irqs_parent(domain, virq, nr_irqs);
0141
0142     spin_lock(&gicp->spi_lock);
0143     __clear_bit(d->hwirq, gicp->spi_bitmap);
0144     spin_unlock(&gicp->spi_lock);
0145 }
0146
0147 static const struct irq_domain_ops gicp_domain_ops = {
0148     .alloc  = gicp_irq_domain_alloc,
0149     .free   = gicp_irq_domain_free,
0150 };
0151
0152 static struct irq_chip gicp_msi_irq_chip = {
0153     .name       = "GICP",
0154     .irq_set_type   = irq_chip_set_type_parent,
0155     .flags      = IRQCHIP_SUPPORTS_LEVEL_MSI,
0156 };
0157
0158 static struct msi_domain_ops gicp_msi_ops = {
0159 };
0160
0161 static struct msi_domain_info gicp_msi_domain_info = {
0162     .flags  = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
0163            MSI_FLAG_LEVEL_CAPABLE),
0164     .ops    = &gicp_msi_ops,
0165     .chip   = &gicp_msi_irq_chip,
0166 };
0167
0168 static int mvebu_gicp_probe(struct platform_device *pdev)
0169 {
0170     struct mvebu_gicp *gicp;
0171     struct irq_domain *inner_domain, *plat_domain, *parent_domain;
0172     struct device_node *node = pdev->dev.of_node;
0173     struct device_node *irq_parent_dn;
0174     int ret, i;
0175
0176     gicp = devm_kzalloc(&pdev->dev, sizeof(*gicp), GFP_KERNEL);
0177     if (!gicp)
0178         return -ENOMEM;
0179
0180     gicp->dev = &pdev->dev;
0181     spin_lock_init(&gicp->spi_lock);
0182
0183     gicp->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0184     if (!gicp->res)
0185         return -ENODEV;
0186
0187     ret = of_property_count_u32_elems(node, "marvell,spi-ranges");
0188     if (ret < 0)
0189         return ret;
0190
0191     gicp->spi_ranges_cnt = ret / 2;
0192
0193     gicp->spi_ranges =
0194         devm_kcalloc(&pdev->dev,
0195                  gicp->spi_ranges_cnt,
0196                  sizeof(struct mvebu_gicp_spi_range),
0197                  GFP_KERNEL);
0198     if (!gicp->spi_ranges)
0199         return -ENOMEM;
0200
0201     for (i = 0; i < gicp->spi_ranges_cnt; i++) {
0202         of_property_read_u32_index(node, "marvell,spi-ranges",
0203                        i * 2,
0204                        &gicp->spi_ranges[i].start);
0205
0206         of_property_read_u32_index(node, "marvell,spi-ranges",
0207                        i * 2 + 1,
0208                        &gicp->spi_ranges[i].count);
0209
0210         gicp->spi_cnt += gicp->spi_ranges[i].count;
0211     }
0212
0213     gicp->spi_bitmap = devm_bitmap_zalloc(&pdev->dev, gicp->spi_cnt, GFP_KERNEL);
0214     if (!gicp->spi_bitmap)
0215         return -ENOMEM;
0216
0217     irq_parent_dn = of_irq_find_parent(node);
0218     if (!irq_parent_dn) {
0219         dev_err(&pdev->dev, "failed to find parent IRQ node\n");
0220         return -ENODEV;
0221     }
0222
0223     parent_domain = irq_find_host(irq_parent_dn);
0224     if (!parent_domain) {
0225         dev_err(&pdev->dev, "failed to find parent IRQ domain\n");
0226         return -ENODEV;
0227     }
0228
0229     inner_domain = irq_domain_create_hierarchy(parent_domain, 0,
0230                            gicp->spi_cnt,
0231                            of_node_to_fwnode(node),
0232                            &gicp_domain_ops, gicp);
0233     if (!inner_domain)
0234         return -ENOMEM;
0235
0236
0237     plat_domain = platform_msi_create_irq_domain(of_node_to_fwnode(node),
0238                              &gicp_msi_domain_info,
0239                              inner_domain);
0240     if (!plat_domain) {
0241         irq_domain_remove(inner_domain);
0242         return -ENOMEM;
0243     }
0244
0245     platform_set_drvdata(pdev, gicp);
0246
0247     return 0;
0248 }
0249
0250 static const struct of_device_id mvebu_gicp_of_match[] = {
0251     { .compatible = "marvell,ap806-gicp", },
0252     {},
0253 };
0254
0255 static struct platform_driver mvebu_gicp_driver = {
0256     .probe  = mvebu_gicp_probe,
0257     .driver = {
0258         .name = "mvebu-gicp",
0259         .of_match_table = mvebu_gicp_of_match,
0260     },
0261 };
0262 builtin_platform_driver(mvebu_gicp_driver);