drivers/irqchip/irq-mst-intc.c

0001 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
0002 /*
0003  * Copyright (c) 2020 MediaTek Inc.
0004  * Author Mark-PK Tsai <mark-pk.tsai@mediatek.com>
0005  */
0006 #include <linux/interrupt.h>
0007 #include <linux/io.h>
0008 #include <linux/irq.h>
0009 #include <linux/irqchip.h>
0010 #include <linux/irqdomain.h>
0011 #include <linux/of.h>
0012 #include <linux/of_address.h>
0013 #include <linux/of_irq.h>
0014 #include <linux/slab.h>
0015 #include <linux/spinlock.h>
0016 #include <linux/syscore_ops.h>
0017
0018 #define MST_INTC_MAX_IRQS   64
0019
0020 #define INTC_MASK       0x0
0021 #define INTC_REV_POLARITY   0x10
0022 #define INTC_EOI        0x20
0023
0024 #ifdef CONFIG_PM_SLEEP
0025 static LIST_HEAD(mst_intc_list);
0026 #endif
0027
0028 struct mst_intc_chip_data {
0029     raw_spinlock_t  lock;
0030     unsigned int    irq_start, nr_irqs;
0031     void __iomem    *base;
0032     bool        no_eoi;
0033 #ifdef CONFIG_PM_SLEEP
0034     struct list_head entry;
0035     u16 saved_polarity_conf[DIV_ROUND_UP(MST_INTC_MAX_IRQS, 16)];
0036 #endif
0037 };
0038
0039 static void mst_set_irq(struct irq_data *d, u32 offset)
0040 {
0041     irq_hw_number_t hwirq = irqd_to_hwirq(d);
0042     struct mst_intc_chip_data *cd = irq_data_get_irq_chip_data(d);
0043     u16 val, mask;
0044     unsigned long flags;
0045
0046     mask = 1 << (hwirq % 16);
0047     offset += (hwirq / 16) * 4;
0048
0049     raw_spin_lock_irqsave(&cd->lock, flags);
0050     val = readw_relaxed(cd->base + offset) | mask;
0051     writew_relaxed(val, cd->base + offset);
0052     raw_spin_unlock_irqrestore(&cd->lock, flags);
0053 }
0054
0055 static void mst_clear_irq(struct irq_data *d, u32 offset)
0056 {
0057     irq_hw_number_t hwirq = irqd_to_hwirq(d);
0058     struct mst_intc_chip_data *cd = irq_data_get_irq_chip_data(d);
0059     u16 val, mask;
0060     unsigned long flags;
0061
0062     mask = 1 << (hwirq % 16);
0063     offset += (hwirq / 16) * 4;
0064
0065     raw_spin_lock_irqsave(&cd->lock, flags);
0066     val = readw_relaxed(cd->base + offset) & ~mask;
0067     writew_relaxed(val, cd->base + offset);
0068     raw_spin_unlock_irqrestore(&cd->lock, flags);
0069 }
0070
0071 static void mst_intc_mask_irq(struct irq_data *d)
0072 {
0073     mst_set_irq(d, INTC_MASK);
0074     irq_chip_mask_parent(d);
0075 }
0076
0077 static void mst_intc_unmask_irq(struct irq_data *d)
0078 {
0079     mst_clear_irq(d, INTC_MASK);
0080     irq_chip_unmask_parent(d);
0081 }
0082
0083 static void mst_intc_eoi_irq(struct irq_data *d)
0084 {
0085     struct mst_intc_chip_data *cd = irq_data_get_irq_chip_data(d);
0086
0087     if (!cd->no_eoi)
0088         mst_set_irq(d, INTC_EOI);
0089
0090     irq_chip_eoi_parent(d);
0091 }
0092
0093 static int mst_irq_chip_set_type(struct irq_data *data, unsigned int type)
0094 {
0095     switch (type) {
0096     case IRQ_TYPE_LEVEL_LOW:
0097     case IRQ_TYPE_EDGE_FALLING:
0098         mst_set_irq(data, INTC_REV_POLARITY);
0099         break;
0100     case IRQ_TYPE_LEVEL_HIGH:
0101     case IRQ_TYPE_EDGE_RISING:
0102         mst_clear_irq(data, INTC_REV_POLARITY);
0103         break;
0104     default:
0105         return -EINVAL;
0106     }
0107
0108     return irq_chip_set_type_parent(data, IRQ_TYPE_LEVEL_HIGH);
0109 }
0110
0111 static struct irq_chip mst_intc_chip = {
0112     .name           = "mst-intc",
0113     .irq_mask       = mst_intc_mask_irq,
0114     .irq_unmask     = mst_intc_unmask_irq,
0115     .irq_eoi        = mst_intc_eoi_irq,
0116     .irq_get_irqchip_state  = irq_chip_get_parent_state,
0117     .irq_set_irqchip_state  = irq_chip_set_parent_state,
0118     .irq_set_affinity   = irq_chip_set_affinity_parent,
0119     .irq_set_vcpu_affinity  = irq_chip_set_vcpu_affinity_parent,
0120     .irq_set_type       = mst_irq_chip_set_type,
0121     .irq_retrigger      = irq_chip_retrigger_hierarchy,
0122     .flags          = IRQCHIP_SET_TYPE_MASKED |
0123                   IRQCHIP_SKIP_SET_WAKE |
0124                   IRQCHIP_MASK_ON_SUSPEND,
0125 };
0126
0127 #ifdef CONFIG_PM_SLEEP
0128 static void mst_intc_polarity_save(struct mst_intc_chip_data *cd)
0129 {
0130     int i;
0131     void __iomem *addr = cd->base + INTC_REV_POLARITY;
0132
0133     for (i = 0; i < DIV_ROUND_UP(cd->nr_irqs, 16); i++)
0134         cd->saved_polarity_conf[i] = readw_relaxed(addr + i * 4);
0135 }
0136
0137 static void mst_intc_polarity_restore(struct mst_intc_chip_data *cd)
0138 {
0139     int i;
0140     void __iomem *addr = cd->base + INTC_REV_POLARITY;
0141
0142     for (i = 0; i < DIV_ROUND_UP(cd->nr_irqs, 16); i++)
0143         writew_relaxed(cd->saved_polarity_conf[i], addr + i * 4);
0144 }
0145
0146 static void mst_irq_resume(void)
0147 {
0148     struct mst_intc_chip_data *cd;
0149
0150     list_for_each_entry(cd, &mst_intc_list, entry)
0151         mst_intc_polarity_restore(cd);
0152 }
0153
0154 static int mst_irq_suspend(void)
0155 {
0156     struct mst_intc_chip_data *cd;
0157
0158     list_for_each_entry(cd, &mst_intc_list, entry)
0159         mst_intc_polarity_save(cd);
0160     return 0;
0161 }
0162
0163 static struct syscore_ops mst_irq_syscore_ops = {
0164     .suspend    = mst_irq_suspend,
0165     .resume     = mst_irq_resume,
0166 };
0167
0168 static int __init mst_irq_pm_init(void)
0169 {
0170     register_syscore_ops(&mst_irq_syscore_ops);
0171     return 0;
0172 }
0173 late_initcall(mst_irq_pm_init);
0174 #endif
0175
0176 static int mst_intc_domain_translate(struct irq_domain *d,
0177                      struct irq_fwspec *fwspec,
0178                      unsigned long *hwirq,
0179                      unsigned int *type)
0180 {
0181     struct mst_intc_chip_data *cd = d->host_data;
0182
0183     if (is_of_node(fwspec->fwnode)) {
0184         if (fwspec->param_count != 3)
0185             return -EINVAL;
0186
0187         /* No PPI should point to this domain */
0188         if (fwspec->param[0] != 0)
0189             return -EINVAL;
0190
0191         if (fwspec->param[1] >= cd->nr_irqs)
0192             return -EINVAL;
0193
0194         *hwirq = fwspec->param[1];
0195         *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
0196         return 0;
0197     }
0198
0199     return -EINVAL;
0200 }
0201
0202 static int mst_intc_domain_alloc(struct irq_domain *domain, unsigned int virq,
0203                  unsigned int nr_irqs, void *data)
0204 {
0205     int i;
0206     irq_hw_number_t hwirq;
0207     struct irq_fwspec parent_fwspec, *fwspec = data;
0208     struct mst_intc_chip_data *cd = domain->host_data;
0209
0210     /* Not GIC compliant */
0211     if (fwspec->param_count != 3)
0212         return -EINVAL;
0213
0214     /* No PPI should point to this domain */
0215     if (fwspec->param[0])
0216         return -EINVAL;
0217
0218     hwirq = fwspec->param[1];
0219     for (i = 0; i < nr_irqs; i++)
0220         irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
0221                           &mst_intc_chip,
0222                           domain->host_data);
0223
0224     parent_fwspec = *fwspec;
0225     parent_fwspec.fwnode = domain->parent->fwnode;
0226     parent_fwspec.param[1] = cd->irq_start + hwirq;
0227
0228     /*
0229      * mst-intc latch the interrupt request if it's edge triggered,
0230      * so the output signal to parent GIC is always level sensitive.
0231      * And if the irq signal is active low, configure it to active high
0232      * to meet GIC SPI spec in mst_irq_chip_set_type via REV_POLARITY bit.
0233      */
0234     parent_fwspec.param[2] = IRQ_TYPE_LEVEL_HIGH;
0235
0236     return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &parent_fwspec);
0237 }
0238
0239 static const struct irq_domain_ops mst_intc_domain_ops = {
0240     .translate  = mst_intc_domain_translate,
0241     .alloc      = mst_intc_domain_alloc,
0242     .free       = irq_domain_free_irqs_common,
0243 };
0244
0245 static int __init mst_intc_of_init(struct device_node *dn,
0246                    struct device_node *parent)
0247 {
0248     struct irq_domain *domain, *domain_parent;
0249     struct mst_intc_chip_data *cd;
0250     u32 irq_start, irq_end;
0251
0252     domain_parent = irq_find_host(parent);
0253     if (!domain_parent) {
0254         pr_err("mst-intc: interrupt-parent not found\n");
0255         return -EINVAL;
0256     }
0257
0258     if (of_property_read_u32_index(dn, "mstar,irqs-map-range", 0, &irq_start) ||
0259         of_property_read_u32_index(dn, "mstar,irqs-map-range", 1, &irq_end))
0260         return -EINVAL;
0261
0262     cd = kzalloc(sizeof(*cd), GFP_KERNEL);
0263     if (!cd)
0264         return -ENOMEM;
0265
0266     cd->base = of_iomap(dn, 0);
0267     if (!cd->base) {
0268         kfree(cd);
0269         return -ENOMEM;
0270     }
0271
0272     cd->no_eoi = of_property_read_bool(dn, "mstar,intc-no-eoi");
0273     raw_spin_lock_init(&cd->lock);
0274     cd->irq_start = irq_start;
0275     cd->nr_irqs = irq_end - irq_start + 1;
0276     domain = irq_domain_add_hierarchy(domain_parent, 0, cd->nr_irqs, dn,
0277                       &mst_intc_domain_ops, cd);
0278     if (!domain) {
0279         iounmap(cd->base);
0280         kfree(cd);
0281         return -ENOMEM;
0282     }
0283
0284 #ifdef CONFIG_PM_SLEEP
0285     INIT_LIST_HEAD(&cd->entry);
0286     list_add_tail(&cd->entry, &mst_intc_list);
0287 #endif
0288     return 0;
0289 }
0290
0291 IRQCHIP_DECLARE(mst_intc, "mstar,mst-intc", mst_intc_of_init);