drivers/irqchip/irq-ls1x.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  *  Copyright (C) 2019, Jiaxun Yang <jiaxun.yang@flygoat.com>
0004  *  Loongson-1 platform IRQ support
0005  */
0006
0007 #include <linux/errno.h>
0008 #include <linux/init.h>
0009 #include <linux/types.h>
0010 #include <linux/interrupt.h>
0011 #include <linux/ioport.h>
0012 #include <linux/irqchip.h>
0013 #include <linux/of_address.h>
0014 #include <linux/of_irq.h>
0015 #include <linux/io.h>
0016 #include <linux/irqchip/chained_irq.h>
0017
0018 #define LS_REG_INTC_STATUS  0x00
0019 #define LS_REG_INTC_EN  0x04
0020 #define LS_REG_INTC_SET 0x08
0021 #define LS_REG_INTC_CLR 0x0c
0022 #define LS_REG_INTC_POL 0x10
0023 #define LS_REG_INTC_EDGE    0x14
0024
0025 /**
0026  * struct ls1x_intc_priv - private ls1x-intc data.
0027  * @domain:     IRQ domain.
0028  * @intc_base:  IO Base of intc registers.
0029  */
0030
0031 struct ls1x_intc_priv {
0032     struct irq_domain   *domain;
0033     void __iomem        *intc_base;
0034 };
0035
0036
0037 static void ls1x_chained_handle_irq(struct irq_desc *desc)
0038 {
0039     struct ls1x_intc_priv *priv = irq_desc_get_handler_data(desc);
0040     struct irq_chip *chip = irq_desc_get_chip(desc);
0041     u32 pending;
0042
0043     chained_irq_enter(chip, desc);
0044     pending = readl(priv->intc_base + LS_REG_INTC_STATUS) &
0045             readl(priv->intc_base + LS_REG_INTC_EN);
0046
0047     if (!pending)
0048         spurious_interrupt();
0049
0050     while (pending) {
0051         int bit = __ffs(pending);
0052
0053         generic_handle_domain_irq(priv->domain, bit);
0054         pending &= ~BIT(bit);
0055     }
0056
0057     chained_irq_exit(chip, desc);
0058 }
0059
0060 static void ls_intc_set_bit(struct irq_chip_generic *gc,
0061                             unsigned int offset,
0062                             u32 mask, bool set)
0063 {
0064     if (set)
0065         writel(readl(gc->reg_base + offset) | mask,
0066         gc->reg_base + offset);
0067     else
0068         writel(readl(gc->reg_base + offset) & ~mask,
0069         gc->reg_base + offset);
0070 }
0071
0072 static int ls_intc_set_type(struct irq_data *data, unsigned int type)
0073 {
0074     struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
0075     u32 mask = data->mask;
0076
0077     switch (type) {
0078     case IRQ_TYPE_LEVEL_HIGH:
0079         ls_intc_set_bit(gc, LS_REG_INTC_EDGE, mask, false);
0080         ls_intc_set_bit(gc, LS_REG_INTC_POL, mask, true);
0081         break;
0082     case IRQ_TYPE_LEVEL_LOW:
0083         ls_intc_set_bit(gc, LS_REG_INTC_EDGE, mask, false);
0084         ls_intc_set_bit(gc, LS_REG_INTC_POL, mask, false);
0085         break;
0086     case IRQ_TYPE_EDGE_RISING:
0087         ls_intc_set_bit(gc, LS_REG_INTC_EDGE, mask, true);
0088         ls_intc_set_bit(gc, LS_REG_INTC_POL, mask, true);
0089         break;
0090     case IRQ_TYPE_EDGE_FALLING:
0091         ls_intc_set_bit(gc, LS_REG_INTC_EDGE, mask, true);
0092         ls_intc_set_bit(gc, LS_REG_INTC_POL, mask, false);
0093         break;
0094     default:
0095         return -EINVAL;
0096     }
0097
0098     irqd_set_trigger_type(data, type);
0099     return irq_setup_alt_chip(data, type);
0100 }
0101
0102
0103 static int __init ls1x_intc_of_init(struct device_node *node,
0104                        struct device_node *parent)
0105 {
0106     struct irq_chip_generic *gc;
0107     struct irq_chip_type *ct;
0108     struct ls1x_intc_priv *priv;
0109     int parent_irq, err = 0;
0110
0111     priv = kzalloc(sizeof(*priv), GFP_KERNEL);
0112     if (!priv)
0113         return -ENOMEM;
0114
0115     priv->intc_base = of_iomap(node, 0);
0116     if (!priv->intc_base) {
0117         err = -ENODEV;
0118         goto out_free_priv;
0119     }
0120
0121     parent_irq = irq_of_parse_and_map(node, 0);
0122     if (!parent_irq) {
0123         pr_err("ls1x-irq: unable to get parent irq\n");
0124         err =  -ENODEV;
0125         goto out_iounmap;
0126     }
0127
0128     /* Set up an IRQ domain */
0129     priv->domain = irq_domain_add_linear(node, 32, &irq_generic_chip_ops,
0130                          NULL);
0131     if (!priv->domain) {
0132         pr_err("ls1x-irq: cannot add IRQ domain\n");
0133         err = -ENOMEM;
0134         goto out_iounmap;
0135     }
0136
0137     err = irq_alloc_domain_generic_chips(priv->domain, 32, 2,
0138         node->full_name, handle_level_irq,
0139         IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN, 0,
0140         IRQ_GC_INIT_MASK_CACHE);
0141     if (err) {
0142         pr_err("ls1x-irq: unable to register IRQ domain\n");
0143         goto out_free_domain;
0144     }
0145
0146     /* Mask all irqs */
0147     writel(0x0, priv->intc_base + LS_REG_INTC_EN);
0148
0149     /* Ack all irqs */
0150     writel(0xffffffff, priv->intc_base + LS_REG_INTC_CLR);
0151
0152     /* Set all irqs to high level triggered */
0153     writel(0xffffffff, priv->intc_base + LS_REG_INTC_POL);
0154
0155     gc = irq_get_domain_generic_chip(priv->domain, 0);
0156
0157     gc->reg_base = priv->intc_base;
0158
0159     ct = gc->chip_types;
0160     ct[0].type = IRQ_TYPE_LEVEL_MASK;
0161     ct[0].regs.mask = LS_REG_INTC_EN;
0162     ct[0].regs.ack = LS_REG_INTC_CLR;
0163     ct[0].chip.irq_unmask = irq_gc_mask_set_bit;
0164     ct[0].chip.irq_mask = irq_gc_mask_clr_bit;
0165     ct[0].chip.irq_ack = irq_gc_ack_set_bit;
0166     ct[0].chip.irq_set_type = ls_intc_set_type;
0167     ct[0].handler = handle_level_irq;
0168
0169     ct[1].type = IRQ_TYPE_EDGE_BOTH;
0170     ct[1].regs.mask = LS_REG_INTC_EN;
0171     ct[1].regs.ack = LS_REG_INTC_CLR;
0172     ct[1].chip.irq_unmask = irq_gc_mask_set_bit;
0173     ct[1].chip.irq_mask = irq_gc_mask_clr_bit;
0174     ct[1].chip.irq_ack = irq_gc_ack_set_bit;
0175     ct[1].chip.irq_set_type = ls_intc_set_type;
0176     ct[1].handler = handle_edge_irq;
0177
0178     irq_set_chained_handler_and_data(parent_irq,
0179         ls1x_chained_handle_irq, priv);
0180
0181     return 0;
0182
0183 out_free_domain:
0184     irq_domain_remove(priv->domain);
0185 out_iounmap:
0186     iounmap(priv->intc_base);
0187 out_free_priv:
0188     kfree(priv);
0189
0190     return err;
0191 }
0192
0193 IRQCHIP_DECLARE(ls1x_intc, "loongson,ls1x-intc", ls1x_intc_of_init);