drivers/irqchip/irq-loongson-liointc.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  *  Copyright (C) 2020, Jiaxun Yang <jiaxun.yang@flygoat.com>
0004  *  Loongson Local IO Interrupt Controller support
0005  */
0006
0007 #include <linux/errno.h>
0008 #include <linux/init.h>
0009 #include <linux/types.h>
0010 #include <linux/interrupt.h>
0011 #include <linux/ioport.h>
0012 #include <linux/irqchip.h>
0013 #include <linux/of_address.h>
0014 #include <linux/of_irq.h>
0015 #include <linux/io.h>
0016 #include <linux/smp.h>
0017 #include <linux/irqchip/chained_irq.h>
0018
0019 #ifdef CONFIG_MIPS
0020 #include <loongson.h>
0021 #else
0022 #include <asm/loongson.h>
0023 #endif
0024
0025 #define LIOINTC_CHIP_IRQ    32
0026 #define LIOINTC_NUM_PARENT  4
0027 #define LIOINTC_NUM_CORES   4
0028
0029 #define LIOINTC_INTC_CHIP_START 0x20
0030
0031 #define LIOINTC_REG_INTC_STATUS (LIOINTC_INTC_CHIP_START + 0x20)
0032 #define LIOINTC_REG_INTC_EN_STATUS  (LIOINTC_INTC_CHIP_START + 0x04)
0033 #define LIOINTC_REG_INTC_ENABLE (LIOINTC_INTC_CHIP_START + 0x08)
0034 #define LIOINTC_REG_INTC_DISABLE    (LIOINTC_INTC_CHIP_START + 0x0c)
0035 #define LIOINTC_REG_INTC_POL    (LIOINTC_INTC_CHIP_START + 0x10)
0036 #define LIOINTC_REG_INTC_EDGE   (LIOINTC_INTC_CHIP_START + 0x14)
0037
0038 #define LIOINTC_SHIFT_INTx  4
0039
0040 #define LIOINTC_ERRATA_IRQ  10
0041
0042 #if defined(CONFIG_MIPS)
0043 #define liointc_core_id get_ebase_cpunum()
0044 #else
0045 #define liointc_core_id get_csr_cpuid()
0046 #endif
0047
0048 struct liointc_handler_data {
0049     struct liointc_priv *priv;
0050     u32         parent_int_map;
0051 };
0052
0053 struct liointc_priv {
0054     struct irq_chip_generic     *gc;
0055     struct liointc_handler_data handler[LIOINTC_NUM_PARENT];
0056     void __iomem            *core_isr[LIOINTC_NUM_CORES];
0057     u8              map_cache[LIOINTC_CHIP_IRQ];
0058     bool                has_lpc_irq_errata;
0059 };
0060
0061 struct fwnode_handle *liointc_handle;
0062
0063 static void liointc_chained_handle_irq(struct irq_desc *desc)
0064 {
0065     struct liointc_handler_data *handler = irq_desc_get_handler_data(desc);
0066     struct irq_chip *chip = irq_desc_get_chip(desc);
0067     struct irq_chip_generic *gc = handler->priv->gc;
0068     int core = liointc_core_id % LIOINTC_NUM_CORES;
0069     u32 pending;
0070
0071     chained_irq_enter(chip, desc);
0072
0073     pending = readl(handler->priv->core_isr[core]);
0074
0075     if (!pending) {
0076         /* Always blame LPC IRQ if we have that bug */
0077         if (handler->priv->has_lpc_irq_errata &&
0078             (handler->parent_int_map & gc->mask_cache &
0079             BIT(LIOINTC_ERRATA_IRQ)))
0080             pending = BIT(LIOINTC_ERRATA_IRQ);
0081         else
0082             spurious_interrupt();
0083     }
0084
0085     while (pending) {
0086         int bit = __ffs(pending);
0087
0088         generic_handle_domain_irq(gc->domain, bit);
0089         pending &= ~BIT(bit);
0090     }
0091
0092     chained_irq_exit(chip, desc);
0093 }
0094
0095 static void liointc_set_bit(struct irq_chip_generic *gc,
0096                 unsigned int offset,
0097                 u32 mask, bool set)
0098 {
0099     if (set)
0100         writel(readl(gc->reg_base + offset) | mask,
0101                 gc->reg_base + offset);
0102     else
0103         writel(readl(gc->reg_base + offset) & ~mask,
0104                 gc->reg_base + offset);
0105 }
0106
0107 static int liointc_set_type(struct irq_data *data, unsigned int type)
0108 {
0109     struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
0110     u32 mask = data->mask;
0111     unsigned long flags;
0112
0113     irq_gc_lock_irqsave(gc, flags);
0114     switch (type) {
0115     case IRQ_TYPE_LEVEL_HIGH:
0116         liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, false);
0117         liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, true);
0118         break;
0119     case IRQ_TYPE_LEVEL_LOW:
0120         liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, false);
0121         liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, false);
0122         break;
0123     case IRQ_TYPE_EDGE_RISING:
0124         liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, true);
0125         liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, true);
0126         break;
0127     case IRQ_TYPE_EDGE_FALLING:
0128         liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, true);
0129         liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, false);
0130         break;
0131     default:
0132         irq_gc_unlock_irqrestore(gc, flags);
0133         return -EINVAL;
0134     }
0135     irq_gc_unlock_irqrestore(gc, flags);
0136
0137     irqd_set_trigger_type(data, type);
0138     return 0;
0139 }
0140
0141 static void liointc_resume(struct irq_chip_generic *gc)
0142 {
0143     struct liointc_priv *priv = gc->private;
0144     unsigned long flags;
0145     int i;
0146
0147     irq_gc_lock_irqsave(gc, flags);
0148     /* Disable all at first */
0149     writel(0xffffffff, gc->reg_base + LIOINTC_REG_INTC_DISABLE);
0150     /* Restore map cache */
0151     for (i = 0; i < LIOINTC_CHIP_IRQ; i++)
0152         writeb(priv->map_cache[i], gc->reg_base + i);
0153     /* Restore mask cache */
0154     writel(gc->mask_cache, gc->reg_base + LIOINTC_REG_INTC_ENABLE);
0155     irq_gc_unlock_irqrestore(gc, flags);
0156 }
0157
0158 static int parent_irq[LIOINTC_NUM_PARENT];
0159 static u32 parent_int_map[LIOINTC_NUM_PARENT];
0160 static const char *const parent_names[] = {"int0", "int1", "int2", "int3"};
0161 static const char *const core_reg_names[] = {"isr0", "isr1", "isr2", "isr3"};
0162
0163 static int liointc_domain_xlate(struct irq_domain *d, struct device_node *ctrlr,
0164                  const u32 *intspec, unsigned int intsize,
0165                  unsigned long *out_hwirq, unsigned int *out_type)
0166 {
0167     if (WARN_ON(intsize < 1))
0168         return -EINVAL;
0169     *out_hwirq = intspec[0] - GSI_MIN_CPU_IRQ;
0170     *out_type = IRQ_TYPE_NONE;
0171     return 0;
0172 }
0173
0174 static const struct irq_domain_ops acpi_irq_gc_ops = {
0175     .map    = irq_map_generic_chip,
0176     .unmap  = irq_unmap_generic_chip,
0177     .xlate  = liointc_domain_xlate,
0178 };
0179
0180 static int liointc_init(phys_addr_t addr, unsigned long size, int revision,
0181         struct fwnode_handle *domain_handle, struct device_node *node)
0182 {
0183     int i, err;
0184     void __iomem *base;
0185     struct irq_chip_type *ct;
0186     struct irq_chip_generic *gc;
0187     struct irq_domain *domain;
0188     struct liointc_priv *priv;
0189
0190     priv = kzalloc(sizeof(*priv), GFP_KERNEL);
0191     if (!priv)
0192         return -ENOMEM;
0193
0194     base = ioremap(addr, size);
0195     if (!base)
0196         goto out_free_priv;
0197
0198     for (i = 0; i < LIOINTC_NUM_CORES; i++)
0199         priv->core_isr[i] = base + LIOINTC_REG_INTC_STATUS;
0200
0201     for (i = 0; i < LIOINTC_NUM_PARENT; i++)
0202         priv->handler[i].parent_int_map = parent_int_map[i];
0203
0204     if (revision > 1) {
0205         for (i = 0; i < LIOINTC_NUM_CORES; i++) {
0206             int index = of_property_match_string(node,
0207                     "reg-names", core_reg_names[i]);
0208
0209             if (index < 0)
0210                 goto out_iounmap;
0211
0212             priv->core_isr[i] = of_iomap(node, index);
0213         }
0214     }
0215
0216     /* Setup IRQ domain */
0217     if (!acpi_disabled)
0218         domain = irq_domain_create_linear(domain_handle, LIOINTC_CHIP_IRQ,
0219                     &acpi_irq_gc_ops, priv);
0220     else
0221         domain = irq_domain_create_linear(domain_handle, LIOINTC_CHIP_IRQ,
0222                     &irq_generic_chip_ops, priv);
0223     if (!domain) {
0224         pr_err("loongson-liointc: cannot add IRQ domain\n");
0225         goto out_iounmap;
0226     }
0227
0228     err = irq_alloc_domain_generic_chips(domain, LIOINTC_CHIP_IRQ, 1,
0229                     (node ? node->full_name : "LIOINTC"),
0230                     handle_level_irq, 0, IRQ_NOPROBE, 0);
0231     if (err) {
0232         pr_err("loongson-liointc: unable to register IRQ domain\n");
0233         goto out_free_domain;
0234     }
0235
0236
0237     /* Disable all IRQs */
0238     writel(0xffffffff, base + LIOINTC_REG_INTC_DISABLE);
0239     /* Set to level triggered */
0240     writel(0x0, base + LIOINTC_REG_INTC_EDGE);
0241
0242     /* Generate parent INT part of map cache */
0243     for (i = 0; i < LIOINTC_NUM_PARENT; i++) {
0244         u32 pending = priv->handler[i].parent_int_map;
0245
0246         while (pending) {
0247             int bit = __ffs(pending);
0248
0249             priv->map_cache[bit] = BIT(i) << LIOINTC_SHIFT_INTx;
0250             pending &= ~BIT(bit);
0251         }
0252     }
0253
0254     for (i = 0; i < LIOINTC_CHIP_IRQ; i++) {
0255         /* Generate core part of map cache */
0256         priv->map_cache[i] |= BIT(loongson_sysconf.boot_cpu_id);
0257         writeb(priv->map_cache[i], base + i);
0258     }
0259
0260     gc = irq_get_domain_generic_chip(domain, 0);
0261     gc->private = priv;
0262     gc->reg_base = base;
0263     gc->domain = domain;
0264     gc->resume = liointc_resume;
0265
0266     ct = gc->chip_types;
0267     ct->regs.enable = LIOINTC_REG_INTC_ENABLE;
0268     ct->regs.disable = LIOINTC_REG_INTC_DISABLE;
0269     ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
0270     ct->chip.irq_mask = irq_gc_mask_disable_reg;
0271     ct->chip.irq_mask_ack = irq_gc_mask_disable_reg;
0272     ct->chip.irq_set_type = liointc_set_type;
0273
0274     gc->mask_cache = 0;
0275     priv->gc = gc;
0276
0277     for (i = 0; i < LIOINTC_NUM_PARENT; i++) {
0278         if (parent_irq[i] <= 0)
0279             continue;
0280
0281         priv->handler[i].priv = priv;
0282         irq_set_chained_handler_and_data(parent_irq[i],
0283                 liointc_chained_handle_irq, &priv->handler[i]);
0284     }
0285
0286     liointc_handle = domain_handle;
0287     return 0;
0288
0289 out_free_domain:
0290     irq_domain_remove(domain);
0291 out_iounmap:
0292     iounmap(base);
0293 out_free_priv:
0294     kfree(priv);
0295
0296     return -EINVAL;
0297 }
0298
0299 #ifdef CONFIG_OF
0300
0301 static int __init liointc_of_init(struct device_node *node,
0302                   struct device_node *parent)
0303 {
0304     bool have_parent = FALSE;
0305     int sz, i, index, revision, err = 0;
0306     struct resource res;
0307
0308     if (!of_device_is_compatible(node, "loongson,liointc-2.0")) {
0309         index = 0;
0310         revision = 1;
0311     } else {
0312         index = of_property_match_string(node, "reg-names", "main");
0313         revision = 2;
0314     }
0315
0316     if (of_address_to_resource(node, index, &res))
0317         return -EINVAL;
0318
0319     for (i = 0; i < LIOINTC_NUM_PARENT; i++) {
0320         parent_irq[i] = of_irq_get_byname(node, parent_names[i]);
0321         if (parent_irq[i] > 0)
0322             have_parent = TRUE;
0323     }
0324     if (!have_parent)
0325         return -ENODEV;
0326
0327     sz = of_property_read_variable_u32_array(node,
0328                         "loongson,parent_int_map",
0329                         &parent_int_map[0],
0330                         LIOINTC_NUM_PARENT,
0331                         LIOINTC_NUM_PARENT);
0332     if (sz < 4) {
0333         pr_err("loongson-liointc: No parent_int_map\n");
0334         return -ENODEV;
0335     }
0336
0337     err = liointc_init(res.start, resource_size(&res),
0338             revision, of_node_to_fwnode(node), node);
0339     if (err < 0)
0340         return err;
0341
0342     return 0;
0343 }
0344
0345 IRQCHIP_DECLARE(loongson_liointc_1_0, "loongson,liointc-1.0", liointc_of_init);
0346 IRQCHIP_DECLARE(loongson_liointc_1_0a, "loongson,liointc-1.0a", liointc_of_init);
0347 IRQCHIP_DECLARE(loongson_liointc_2_0, "loongson,liointc-2.0", liointc_of_init);
0348
0349 #endif
0350
0351 #ifdef CONFIG_ACPI
0352 int __init liointc_acpi_init(struct irq_domain *parent, struct acpi_madt_lio_pic *acpi_liointc)
0353 {
0354     int ret;
0355     struct fwnode_handle *domain_handle;
0356
0357     parent_int_map[0] = acpi_liointc->cascade_map[0];
0358     parent_int_map[1] = acpi_liointc->cascade_map[1];
0359
0360     parent_irq[0] = irq_create_mapping(parent, acpi_liointc->cascade[0]);
0361     parent_irq[1] = irq_create_mapping(parent, acpi_liointc->cascade[1]);
0362
0363     domain_handle = irq_domain_alloc_fwnode(&acpi_liointc->address);
0364     if (!domain_handle) {
0365         pr_err("Unable to allocate domain handle\n");
0366         return -ENOMEM;
0367     }
0368     ret = liointc_init(acpi_liointc->address, acpi_liointc->size,
0369                1, domain_handle, NULL);
0370     if (ret)
0371         irq_domain_free_fwnode(domain_handle);
0372
0373     return ret;
0374 }
0375 #endif