drivers/irqchip/irq-loongson-htvec.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  *  Copyright (C) 2020, Jiaxun Yang <jiaxun.yang@flygoat.com>
0004  *  Loongson HyperTransport Interrupt Vector support
0005  */
0006
0007 #define pr_fmt(fmt) "htvec: " fmt
0008
0009 #include <linux/interrupt.h>
0010 #include <linux/irq.h>
0011 #include <linux/irqchip.h>
0012 #include <linux/irqdomain.h>
0013 #include <linux/irqchip/chained_irq.h>
0014 #include <linux/kernel.h>
0015 #include <linux/platform_device.h>
0016 #include <linux/of_address.h>
0017 #include <linux/of_irq.h>
0018 #include <linux/of_platform.h>
0019
0020 /* Registers */
0021 #define HTVEC_EN_OFF        0x20
0022 #define HTVEC_MAX_PARENT_IRQ    8
0023
0024 #define VEC_COUNT_PER_REG   32
0025 #define VEC_REG_IDX(irq_id) ((irq_id) / VEC_COUNT_PER_REG)
0026 #define VEC_REG_BIT(irq_id) ((irq_id) % VEC_COUNT_PER_REG)
0027
0028 struct htvec {
0029     int         num_parents;
0030     void __iomem        *base;
0031     struct irq_domain   *htvec_domain;
0032     raw_spinlock_t      htvec_lock;
0033 };
0034
0035 static void htvec_irq_dispatch(struct irq_desc *desc)
0036 {
0037     int i;
0038     u32 pending;
0039     bool handled = false;
0040     struct irq_chip *chip = irq_desc_get_chip(desc);
0041     struct htvec *priv = irq_desc_get_handler_data(desc);
0042
0043     chained_irq_enter(chip, desc);
0044
0045     for (i = 0; i < priv->num_parents; i++) {
0046         pending = readl(priv->base + 4 * i);
0047         while (pending) {
0048             int bit = __ffs(pending);
0049
0050             generic_handle_domain_irq(priv->htvec_domain,
0051                           bit + VEC_COUNT_PER_REG * i);
0052             pending &= ~BIT(bit);
0053             handled = true;
0054         }
0055     }
0056
0057     if (!handled)
0058         spurious_interrupt();
0059
0060     chained_irq_exit(chip, desc);
0061 }
0062
0063 static void htvec_ack_irq(struct irq_data *d)
0064 {
0065     struct htvec *priv = irq_data_get_irq_chip_data(d);
0066
0067     writel(BIT(VEC_REG_BIT(d->hwirq)),
0068            priv->base + VEC_REG_IDX(d->hwirq) * 4);
0069 }
0070
0071 static void htvec_mask_irq(struct irq_data *d)
0072 {
0073     u32 reg;
0074     void __iomem *addr;
0075     struct htvec *priv = irq_data_get_irq_chip_data(d);
0076
0077     raw_spin_lock(&priv->htvec_lock);
0078     addr = priv->base + HTVEC_EN_OFF;
0079     addr += VEC_REG_IDX(d->hwirq) * 4;
0080     reg = readl(addr);
0081     reg &= ~BIT(VEC_REG_BIT(d->hwirq));
0082     writel(reg, addr);
0083     raw_spin_unlock(&priv->htvec_lock);
0084 }
0085
0086 static void htvec_unmask_irq(struct irq_data *d)
0087 {
0088     u32 reg;
0089     void __iomem *addr;
0090     struct htvec *priv = irq_data_get_irq_chip_data(d);
0091
0092     raw_spin_lock(&priv->htvec_lock);
0093     addr = priv->base + HTVEC_EN_OFF;
0094     addr += VEC_REG_IDX(d->hwirq) * 4;
0095     reg = readl(addr);
0096     reg |= BIT(VEC_REG_BIT(d->hwirq));
0097     writel(reg, addr);
0098     raw_spin_unlock(&priv->htvec_lock);
0099 }
0100
0101 static struct irq_chip htvec_irq_chip = {
0102     .name           = "LOONGSON_HTVEC",
0103     .irq_mask       = htvec_mask_irq,
0104     .irq_unmask     = htvec_unmask_irq,
0105     .irq_ack        = htvec_ack_irq,
0106 };
0107
0108 static int htvec_domain_alloc(struct irq_domain *domain, unsigned int virq,
0109                   unsigned int nr_irqs, void *arg)
0110 {
0111     int ret;
0112     unsigned long hwirq;
0113     unsigned int type, i;
0114     struct htvec *priv = domain->host_data;
0115
0116     ret = irq_domain_translate_onecell(domain, arg, &hwirq, &type);
0117     if (ret)
0118         return ret;
0119
0120     for (i = 0; i < nr_irqs; i++) {
0121         irq_domain_set_info(domain, virq + i, hwirq + i, &htvec_irq_chip,
0122                     priv, handle_edge_irq, NULL, NULL);
0123     }
0124
0125     return 0;
0126 }
0127
0128 static void htvec_domain_free(struct irq_domain *domain, unsigned int virq,
0129                   unsigned int nr_irqs)
0130 {
0131     int i;
0132
0133     for (i = 0; i < nr_irqs; i++) {
0134         struct irq_data *d = irq_domain_get_irq_data(domain, virq + i);
0135
0136         irq_set_handler(virq + i, NULL);
0137         irq_domain_reset_irq_data(d);
0138     }
0139 }
0140
0141 static const struct irq_domain_ops htvec_domain_ops = {
0142     .translate  = irq_domain_translate_onecell,
0143     .alloc      = htvec_domain_alloc,
0144     .free       = htvec_domain_free,
0145 };
0146
0147 static void htvec_reset(struct htvec *priv)
0148 {
0149     u32 idx;
0150
0151     /* Clear IRQ cause registers, mask all interrupts */
0152     for (idx = 0; idx < priv->num_parents; idx++) {
0153         writel_relaxed(0x0, priv->base + HTVEC_EN_OFF + 4 * idx);
0154         writel_relaxed(0xFFFFFFFF, priv->base + 4 * idx);
0155     }
0156 }
0157
0158 static int htvec_of_init(struct device_node *node,
0159                 struct device_node *parent)
0160 {
0161     struct htvec *priv;
0162     int err, parent_irq[8], i;
0163
0164     priv = kzalloc(sizeof(*priv), GFP_KERNEL);
0165     if (!priv)
0166         return -ENOMEM;
0167
0168     raw_spin_lock_init(&priv->htvec_lock);
0169     priv->base = of_iomap(node, 0);
0170     if (!priv->base) {
0171         err = -ENOMEM;
0172         goto free_priv;
0173     }
0174
0175     /* Interrupt may come from any of the 8 interrupt lines */
0176     for (i = 0; i < HTVEC_MAX_PARENT_IRQ; i++) {
0177         parent_irq[i] = irq_of_parse_and_map(node, i);
0178         if (parent_irq[i] <= 0)
0179             break;
0180
0181         priv->num_parents++;
0182     }
0183
0184     if (!priv->num_parents) {
0185         pr_err("Failed to get parent irqs\n");
0186         err = -ENODEV;
0187         goto iounmap_base;
0188     }
0189
0190     priv->htvec_domain = irq_domain_create_linear(of_node_to_fwnode(node),
0191                     (VEC_COUNT_PER_REG * priv->num_parents),
0192                     &htvec_domain_ops, priv);
0193     if (!priv->htvec_domain) {
0194         pr_err("Failed to create IRQ domain\n");
0195         err = -ENOMEM;
0196         goto irq_dispose;
0197     }
0198
0199     htvec_reset(priv);
0200
0201     for (i = 0; i < priv->num_parents; i++)
0202         irq_set_chained_handler_and_data(parent_irq[i],
0203                          htvec_irq_dispatch, priv);
0204
0205     return 0;
0206
0207 irq_dispose:
0208     for (; i > 0; i--)
0209         irq_dispose_mapping(parent_irq[i - 1]);
0210 iounmap_base:
0211     iounmap(priv->base);
0212 free_priv:
0213     kfree(priv);
0214
0215     return err;
0216 }
0217
0218 IRQCHIP_DECLARE(htvec, "loongson,htvec-1.0", htvec_of_init);