0001
0002
0003
0004
0005
0006
0007
0008 #define pr_fmt(fmt) "eiointc: " fmt
0009
0010 #include <linux/interrupt.h>
0011 #include <linux/irq.h>
0012 #include <linux/irqchip.h>
0013 #include <linux/irqdomain.h>
0014 #include <linux/irqchip/chained_irq.h>
0015 #include <linux/kernel.h>
0016 #include <linux/platform_device.h>
0017 #include <linux/of_address.h>
0018 #include <linux/of_irq.h>
0019 #include <linux/of_platform.h>
0020
0021 #define EIOINTC_REG_NODEMAP 0x14a0
0022 #define EIOINTC_REG_IPMAP 0x14c0
0023 #define EIOINTC_REG_ENABLE 0x1600
0024 #define EIOINTC_REG_BOUNCE 0x1680
0025 #define EIOINTC_REG_ISR 0x1800
0026 #define EIOINTC_REG_ROUTE 0x1c00
0027
0028 #define VEC_REG_COUNT 4
0029 #define VEC_COUNT_PER_REG 64
0030 #define VEC_COUNT (VEC_REG_COUNT * VEC_COUNT_PER_REG)
0031 #define VEC_REG_IDX(irq_id) ((irq_id) / VEC_COUNT_PER_REG)
0032 #define VEC_REG_BIT(irq_id) ((irq_id) % VEC_COUNT_PER_REG)
0033 #define EIOINTC_ALL_ENABLE 0xffffffff
0034
0035 #define MAX_EIO_NODES (NR_CPUS / CORES_PER_EIO_NODE)
0036
0037 static int nr_pics;
0038
0039 struct eiointc_priv {
0040 u32 node;
0041 nodemask_t node_map;
0042 cpumask_t cpuspan_map;
0043 struct fwnode_handle *domain_handle;
0044 struct irq_domain *eiointc_domain;
0045 };
0046
0047 static struct eiointc_priv *eiointc_priv[MAX_IO_PICS];
0048
0049 static void eiointc_enable(void)
0050 {
0051 uint64_t misc;
0052
0053 misc = iocsr_read64(LOONGARCH_IOCSR_MISC_FUNC);
0054 misc |= IOCSR_MISC_FUNC_EXT_IOI_EN;
0055 iocsr_write64(misc, LOONGARCH_IOCSR_MISC_FUNC);
0056 }
0057
0058 static int cpu_to_eio_node(int cpu)
0059 {
0060 return cpu_logical_map(cpu) / CORES_PER_EIO_NODE;
0061 }
0062
0063 static void eiointc_set_irq_route(int pos, unsigned int cpu, unsigned int mnode, nodemask_t *node_map)
0064 {
0065 int i, node, cpu_node, route_node;
0066 unsigned char coremap;
0067 uint32_t pos_off, data, data_byte, data_mask;
0068
0069 pos_off = pos & ~3;
0070 data_byte = pos & 3;
0071 data_mask = ~BIT_MASK(data_byte) & 0xf;
0072
0073
0074 cpu_node = cpu_logical_map(cpu) / CORES_PER_EIO_NODE;
0075 coremap = BIT(cpu_logical_map(cpu) % CORES_PER_EIO_NODE);
0076
0077 for_each_online_cpu(i) {
0078 node = cpu_to_eio_node(i);
0079 if (!node_isset(node, *node_map))
0080 continue;
0081
0082
0083 route_node = (node == mnode) ? cpu_node : node;
0084 data = ((coremap | (route_node << 4)) << (data_byte * 8));
0085 csr_any_send(EIOINTC_REG_ROUTE + pos_off, data, data_mask, node * CORES_PER_EIO_NODE);
0086 }
0087 }
0088
0089 static DEFINE_RAW_SPINLOCK(affinity_lock);
0090
0091 static int eiointc_set_irq_affinity(struct irq_data *d, const struct cpumask *affinity, bool force)
0092 {
0093 unsigned int cpu;
0094 unsigned long flags;
0095 uint32_t vector, regaddr;
0096 struct cpumask intersect_affinity;
0097 struct eiointc_priv *priv = d->domain->host_data;
0098
0099 raw_spin_lock_irqsave(&affinity_lock, flags);
0100
0101 cpumask_and(&intersect_affinity, affinity, cpu_online_mask);
0102 cpumask_and(&intersect_affinity, &intersect_affinity, &priv->cpuspan_map);
0103
0104 if (cpumask_empty(&intersect_affinity)) {
0105 raw_spin_unlock_irqrestore(&affinity_lock, flags);
0106 return -EINVAL;
0107 }
0108 cpu = cpumask_first(&intersect_affinity);
0109
0110 vector = d->hwirq;
0111 regaddr = EIOINTC_REG_ENABLE + ((vector >> 5) << 2);
0112
0113
0114 csr_any_send(regaddr, EIOINTC_ALL_ENABLE & (~BIT(vector & 0x1F)),
0115 0x0, priv->node * CORES_PER_EIO_NODE);
0116
0117
0118 eiointc_set_irq_route(vector, cpu, priv->node, &priv->node_map);
0119
0120
0121 csr_any_send(regaddr, EIOINTC_ALL_ENABLE,
0122 0x0, priv->node * CORES_PER_EIO_NODE);
0123
0124 irq_data_update_effective_affinity(d, cpumask_of(cpu));
0125
0126 raw_spin_unlock_irqrestore(&affinity_lock, flags);
0127
0128 return IRQ_SET_MASK_OK;
0129 }
0130
0131 static int eiointc_index(int node)
0132 {
0133 int i;
0134
0135 for (i = 0; i < nr_pics; i++) {
0136 if (node_isset(node, eiointc_priv[i]->node_map))
0137 return i;
0138 }
0139
0140 return -1;
0141 }
0142
0143 static int eiointc_router_init(unsigned int cpu)
0144 {
0145 int i, bit;
0146 uint32_t data;
0147 uint32_t node = cpu_to_eio_node(cpu);
0148 uint32_t index = eiointc_index(node);
0149
0150 if (index < 0) {
0151 pr_err("Error: invalid nodemap!\n");
0152 return -1;
0153 }
0154
0155 if ((cpu_logical_map(cpu) % CORES_PER_EIO_NODE) == 0) {
0156 eiointc_enable();
0157
0158 for (i = 0; i < VEC_COUNT / 32; i++) {
0159 data = (((1 << (i * 2 + 1)) << 16) | (1 << (i * 2)));
0160 iocsr_write32(data, EIOINTC_REG_NODEMAP + i * 4);
0161 }
0162
0163 for (i = 0; i < VEC_COUNT / 32 / 4; i++) {
0164 bit = BIT(1 + index);
0165 data = bit | (bit << 8) | (bit << 16) | (bit << 24);
0166 iocsr_write32(data, EIOINTC_REG_IPMAP + i * 4);
0167 }
0168
0169 for (i = 0; i < VEC_COUNT / 4; i++) {
0170
0171 if (index == 0)
0172 bit = BIT(cpu_logical_map(0));
0173 else
0174 bit = (eiointc_priv[index]->node << 4) | 1;
0175
0176 data = bit | (bit << 8) | (bit << 16) | (bit << 24);
0177 iocsr_write32(data, EIOINTC_REG_ROUTE + i * 4);
0178 }
0179
0180 for (i = 0; i < VEC_COUNT / 32; i++) {
0181 data = 0xffffffff;
0182 iocsr_write32(data, EIOINTC_REG_ENABLE + i * 4);
0183 iocsr_write32(data, EIOINTC_REG_BOUNCE + i * 4);
0184 }
0185 }
0186
0187 return 0;
0188 }
0189
0190 static void eiointc_irq_dispatch(struct irq_desc *desc)
0191 {
0192 int i;
0193 u64 pending;
0194 bool handled = false;
0195 struct irq_chip *chip = irq_desc_get_chip(desc);
0196 struct eiointc_priv *priv = irq_desc_get_handler_data(desc);
0197
0198 chained_irq_enter(chip, desc);
0199
0200 for (i = 0; i < VEC_REG_COUNT; i++) {
0201 pending = iocsr_read64(EIOINTC_REG_ISR + (i << 3));
0202 iocsr_write64(pending, EIOINTC_REG_ISR + (i << 3));
0203 while (pending) {
0204 int bit = __ffs(pending);
0205 int irq = bit + VEC_COUNT_PER_REG * i;
0206
0207 generic_handle_domain_irq(priv->eiointc_domain, irq);
0208 pending &= ~BIT(bit);
0209 handled = true;
0210 }
0211 }
0212
0213 if (!handled)
0214 spurious_interrupt();
0215
0216 chained_irq_exit(chip, desc);
0217 }
0218
0219 static void eiointc_ack_irq(struct irq_data *d)
0220 {
0221 }
0222
0223 static void eiointc_mask_irq(struct irq_data *d)
0224 {
0225 }
0226
0227 static void eiointc_unmask_irq(struct irq_data *d)
0228 {
0229 }
0230
0231 static struct irq_chip eiointc_irq_chip = {
0232 .name = "EIOINTC",
0233 .irq_ack = eiointc_ack_irq,
0234 .irq_mask = eiointc_mask_irq,
0235 .irq_unmask = eiointc_unmask_irq,
0236 .irq_set_affinity = eiointc_set_irq_affinity,
0237 };
0238
0239 static int eiointc_domain_alloc(struct irq_domain *domain, unsigned int virq,
0240 unsigned int nr_irqs, void *arg)
0241 {
0242 int ret;
0243 unsigned int i, type;
0244 unsigned long hwirq = 0;
0245 struct eiointc *priv = domain->host_data;
0246
0247 ret = irq_domain_translate_onecell(domain, arg, &hwirq, &type);
0248 if (ret)
0249 return ret;
0250
0251 for (i = 0; i < nr_irqs; i++) {
0252 irq_domain_set_info(domain, virq + i, hwirq + i, &eiointc_irq_chip,
0253 priv, handle_edge_irq, NULL, NULL);
0254 }
0255
0256 return 0;
0257 }
0258
0259 static void eiointc_domain_free(struct irq_domain *domain, unsigned int virq,
0260 unsigned int nr_irqs)
0261 {
0262 int i;
0263
0264 for (i = 0; i < nr_irqs; i++) {
0265 struct irq_data *d = irq_domain_get_irq_data(domain, virq + i);
0266
0267 irq_set_handler(virq + i, NULL);
0268 irq_domain_reset_irq_data(d);
0269 }
0270 }
0271
0272 static const struct irq_domain_ops eiointc_domain_ops = {
0273 .translate = irq_domain_translate_onecell,
0274 .alloc = eiointc_domain_alloc,
0275 .free = eiointc_domain_free,
0276 };
0277
0278 static void acpi_set_vec_parent(int node, struct irq_domain *parent, struct acpi_vector_group *vec_group)
0279 {
0280 int i;
0281
0282 if (cpu_has_flatmode)
0283 node = cpu_to_node(node * CORES_PER_EIO_NODE);
0284
0285 for (i = 0; i < MAX_IO_PICS; i++) {
0286 if (node == vec_group[i].node) {
0287 vec_group[i].parent = parent;
0288 return;
0289 }
0290 }
0291 }
0292
0293 static struct irq_domain *acpi_get_vec_parent(int node, struct acpi_vector_group *vec_group)
0294 {
0295 int i;
0296
0297 for (i = 0; i < MAX_IO_PICS; i++) {
0298 if (node == vec_group[i].node)
0299 return vec_group[i].parent;
0300 }
0301 return NULL;
0302 }
0303
0304 static int __init
0305 pch_pic_parse_madt(union acpi_subtable_headers *header,
0306 const unsigned long end)
0307 {
0308 struct acpi_madt_bio_pic *pchpic_entry = (struct acpi_madt_bio_pic *)header;
0309 unsigned int node = (pchpic_entry->address >> 44) & 0xf;
0310 struct irq_domain *parent = acpi_get_vec_parent(node, pch_group);
0311
0312 if (parent)
0313 return pch_pic_acpi_init(parent, pchpic_entry);
0314
0315 return -EINVAL;
0316 }
0317
0318 static int __init
0319 pch_msi_parse_madt(union acpi_subtable_headers *header,
0320 const unsigned long end)
0321 {
0322 struct acpi_madt_msi_pic *pchmsi_entry = (struct acpi_madt_msi_pic *)header;
0323 struct irq_domain *parent = acpi_get_vec_parent(eiointc_priv[nr_pics - 1]->node, msi_group);
0324
0325 if (parent)
0326 return pch_msi_acpi_init(parent, pchmsi_entry);
0327
0328 return -EINVAL;
0329 }
0330
0331 static int __init acpi_cascade_irqdomain_init(void)
0332 {
0333 acpi_table_parse_madt(ACPI_MADT_TYPE_BIO_PIC,
0334 pch_pic_parse_madt, 0);
0335 acpi_table_parse_madt(ACPI_MADT_TYPE_MSI_PIC,
0336 pch_msi_parse_madt, 1);
0337 return 0;
0338 }
0339
0340 int __init eiointc_acpi_init(struct irq_domain *parent,
0341 struct acpi_madt_eio_pic *acpi_eiointc)
0342 {
0343 int i, parent_irq;
0344 unsigned long node_map;
0345 struct eiointc_priv *priv;
0346
0347 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
0348 if (!priv)
0349 return -ENOMEM;
0350
0351 priv->domain_handle = irq_domain_alloc_named_id_fwnode("EIOPIC",
0352 acpi_eiointc->node);
0353 if (!priv->domain_handle) {
0354 pr_err("Unable to allocate domain handle\n");
0355 goto out_free_priv;
0356 }
0357
0358 priv->node = acpi_eiointc->node;
0359 node_map = acpi_eiointc->node_map ? : -1ULL;
0360
0361 for_each_possible_cpu(i) {
0362 if (node_map & (1ULL << cpu_to_eio_node(i))) {
0363 node_set(cpu_to_eio_node(i), priv->node_map);
0364 cpumask_or(&priv->cpuspan_map, &priv->cpuspan_map, cpumask_of(i));
0365 }
0366 }
0367
0368
0369 priv->eiointc_domain = irq_domain_create_linear(priv->domain_handle, VEC_COUNT,
0370 &eiointc_domain_ops, priv);
0371 if (!priv->eiointc_domain) {
0372 pr_err("loongson-eiointc: cannot add IRQ domain\n");
0373 goto out_free_handle;
0374 }
0375
0376 eiointc_priv[nr_pics++] = priv;
0377
0378 eiointc_router_init(0);
0379
0380 parent_irq = irq_create_mapping(parent, acpi_eiointc->cascade);
0381 irq_set_chained_handler_and_data(parent_irq, eiointc_irq_dispatch, priv);
0382
0383 cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_LOONGARCH_STARTING,
0384 "irqchip/loongarch/intc:starting",
0385 eiointc_router_init, NULL);
0386
0387 acpi_set_vec_parent(acpi_eiointc->node, priv->eiointc_domain, pch_group);
0388 acpi_set_vec_parent(acpi_eiointc->node, priv->eiointc_domain, msi_group);
0389 acpi_cascade_irqdomain_init();
0390
0391 return 0;
0392
0393 out_free_handle:
0394 irq_domain_free_fwnode(priv->domain_handle);
0395 priv->domain_handle = NULL;
0396 out_free_priv:
0397 kfree(priv);
0398
0399 return -ENOMEM;
0400 }
