drivers/irqchip/irq-loongarch-cpu.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
0004  */
0005
0006 #include <linux/init.h>
0007 #include <linux/kernel.h>
0008 #include <linux/interrupt.h>
0009 #include <linux/irq.h>
0010 #include <linux/irqchip.h>
0011 #include <linux/irqdomain.h>
0012
0013 #include <asm/loongarch.h>
0014 #include <asm/setup.h>
0015
0016 static struct irq_domain *irq_domain;
0017 struct fwnode_handle *cpuintc_handle;
0018
0019 static u32 lpic_gsi_to_irq(u32 gsi)
0020 {
0021     /* Only pch irqdomain transferring is required for LoongArch. */
0022     if (gsi >= GSI_MIN_PCH_IRQ && gsi <= GSI_MAX_PCH_IRQ)
0023         return acpi_register_gsi(NULL, gsi, ACPI_LEVEL_SENSITIVE, ACPI_ACTIVE_HIGH);
0024
0025     return 0;
0026 }
0027
0028 static struct fwnode_handle *lpic_get_gsi_domain_id(u32 gsi)
0029 {
0030     int id;
0031     struct fwnode_handle *domain_handle = NULL;
0032
0033     switch (gsi) {
0034     case GSI_MIN_CPU_IRQ ... GSI_MAX_CPU_IRQ:
0035         if (liointc_handle)
0036             domain_handle = liointc_handle;
0037         break;
0038
0039     case GSI_MIN_LPC_IRQ ... GSI_MAX_LPC_IRQ:
0040         if (pch_lpc_handle)
0041             domain_handle = pch_lpc_handle;
0042         break;
0043
0044     case GSI_MIN_PCH_IRQ ... GSI_MAX_PCH_IRQ:
0045         id = find_pch_pic(gsi);
0046         if (id >= 0 && pch_pic_handle[id])
0047             domain_handle = pch_pic_handle[id];
0048         break;
0049     }
0050
0051     return domain_handle;
0052 }
0053
0054 static void mask_loongarch_irq(struct irq_data *d)
0055 {
0056     clear_csr_ecfg(ECFGF(d->hwirq));
0057 }
0058
0059 static void unmask_loongarch_irq(struct irq_data *d)
0060 {
0061     set_csr_ecfg(ECFGF(d->hwirq));
0062 }
0063
0064 static struct irq_chip cpu_irq_controller = {
0065     .name       = "CPUINTC",
0066     .irq_mask   = mask_loongarch_irq,
0067     .irq_unmask = unmask_loongarch_irq,
0068 };
0069
0070 static void handle_cpu_irq(struct pt_regs *regs)
0071 {
0072     int hwirq;
0073     unsigned int estat = read_csr_estat() & CSR_ESTAT_IS;
0074
0075     while ((hwirq = ffs(estat))) {
0076         estat &= ~BIT(hwirq - 1);
0077         generic_handle_domain_irq(irq_domain, hwirq - 1);
0078     }
0079 }
0080
0081 static int loongarch_cpu_intc_map(struct irq_domain *d, unsigned int irq,
0082                  irq_hw_number_t hwirq)
0083 {
0084     irq_set_noprobe(irq);
0085     irq_set_chip_and_handler(irq, &cpu_irq_controller, handle_percpu_irq);
0086
0087     return 0;
0088 }
0089
0090 static const struct irq_domain_ops loongarch_cpu_intc_irq_domain_ops = {
0091     .map = loongarch_cpu_intc_map,
0092     .xlate = irq_domain_xlate_onecell,
0093 };
0094
0095 static int __init
0096 liointc_parse_madt(union acpi_subtable_headers *header,
0097                const unsigned long end)
0098 {
0099     struct acpi_madt_lio_pic *liointc_entry = (struct acpi_madt_lio_pic *)header;
0100
0101     return liointc_acpi_init(irq_domain, liointc_entry);
0102 }
0103
0104 static int __init
0105 eiointc_parse_madt(union acpi_subtable_headers *header,
0106                const unsigned long end)
0107 {
0108     struct acpi_madt_eio_pic *eiointc_entry = (struct acpi_madt_eio_pic *)header;
0109
0110     return eiointc_acpi_init(irq_domain, eiointc_entry);
0111 }
0112
0113 static int __init acpi_cascade_irqdomain_init(void)
0114 {
0115     acpi_table_parse_madt(ACPI_MADT_TYPE_LIO_PIC,
0116                   liointc_parse_madt, 0);
0117     acpi_table_parse_madt(ACPI_MADT_TYPE_EIO_PIC,
0118                   eiointc_parse_madt, 0);
0119     return 0;
0120 }
0121
0122 static int __init cpuintc_acpi_init(union acpi_subtable_headers *header,
0123                    const unsigned long end)
0124 {
0125     if (irq_domain)
0126         return 0;
0127
0128     /* Mask interrupts. */
0129     clear_csr_ecfg(ECFG0_IM);
0130     clear_csr_estat(ESTATF_IP);
0131
0132     cpuintc_handle = irq_domain_alloc_named_fwnode("CPUINTC");
0133     irq_domain = irq_domain_create_linear(cpuintc_handle, EXCCODE_INT_NUM,
0134                     &loongarch_cpu_intc_irq_domain_ops, NULL);
0135
0136     if (!irq_domain)
0137         panic("Failed to add irqdomain for LoongArch CPU");
0138
0139     set_handle_irq(&handle_cpu_irq);
0140     acpi_set_irq_model(ACPI_IRQ_MODEL_LPIC, lpic_get_gsi_domain_id);
0141     acpi_set_gsi_to_irq_fallback(lpic_gsi_to_irq);
0142     acpi_cascade_irqdomain_init();
0143
0144     return 0;
0145 }
0146
0147 IRQCHIP_ACPI_DECLARE(cpuintc_v1, ACPI_MADT_TYPE_CORE_PIC,
0148         NULL, ACPI_MADT_CORE_PIC_VERSION_V1, cpuintc_acpi_init);