drivers/irqchip/irq-ingenic.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  *  Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
0004  *  Ingenic XBurst platform IRQ support
0005  */
0006
0007 #include <linux/errno.h>
0008 #include <linux/init.h>
0009 #include <linux/types.h>
0010 #include <linux/interrupt.h>
0011 #include <linux/ioport.h>
0012 #include <linux/irqchip.h>
0013 #include <linux/of_address.h>
0014 #include <linux/of_irq.h>
0015 #include <linux/timex.h>
0016 #include <linux/slab.h>
0017 #include <linux/delay.h>
0018
0019 #include <asm/io.h>
0020
0021 struct ingenic_intc_data {
0022     void __iomem *base;
0023     struct irq_domain *domain;
0024     unsigned num_chips;
0025 };
0026
0027 #define JZ_REG_INTC_STATUS  0x00
0028 #define JZ_REG_INTC_MASK    0x04
0029 #define JZ_REG_INTC_SET_MASK    0x08
0030 #define JZ_REG_INTC_CLEAR_MASK  0x0c
0031 #define JZ_REG_INTC_PENDING 0x10
0032 #define CHIP_SIZE       0x20
0033
0034 static irqreturn_t intc_cascade(int irq, void *data)
0035 {
0036     struct ingenic_intc_data *intc = irq_get_handler_data(irq);
0037     struct irq_domain *domain = intc->domain;
0038     struct irq_chip_generic *gc;
0039     uint32_t pending;
0040     unsigned i;
0041
0042     for (i = 0; i < intc->num_chips; i++) {
0043         gc = irq_get_domain_generic_chip(domain, i * 32);
0044
0045         pending = irq_reg_readl(gc, JZ_REG_INTC_PENDING);
0046         if (!pending)
0047             continue;
0048
0049         while (pending) {
0050             int bit = __fls(pending);
0051
0052             generic_handle_domain_irq(domain, bit + (i * 32));
0053             pending &= ~BIT(bit);
0054         }
0055     }
0056
0057     return IRQ_HANDLED;
0058 }
0059
0060 static int __init ingenic_intc_of_init(struct device_node *node,
0061                        unsigned num_chips)
0062 {
0063     struct ingenic_intc_data *intc;
0064     struct irq_chip_generic *gc;
0065     struct irq_chip_type *ct;
0066     struct irq_domain *domain;
0067     int parent_irq, err = 0;
0068     unsigned i;
0069
0070     intc = kzalloc(sizeof(*intc), GFP_KERNEL);
0071     if (!intc) {
0072         err = -ENOMEM;
0073         goto out_err;
0074     }
0075
0076     parent_irq = irq_of_parse_and_map(node, 0);
0077     if (!parent_irq) {
0078         err = -EINVAL;
0079         goto out_free;
0080     }
0081
0082     err = irq_set_handler_data(parent_irq, intc);
0083     if (err)
0084         goto out_unmap_irq;
0085
0086     intc->num_chips = num_chips;
0087     intc->base = of_iomap(node, 0);
0088     if (!intc->base) {
0089         err = -ENODEV;
0090         goto out_unmap_irq;
0091     }
0092
0093     domain = irq_domain_add_linear(node, num_chips * 32,
0094                        &irq_generic_chip_ops, NULL);
0095     if (!domain) {
0096         err = -ENOMEM;
0097         goto out_unmap_base;
0098     }
0099
0100     intc->domain = domain;
0101
0102     err = irq_alloc_domain_generic_chips(domain, 32, 1, "INTC",
0103                          handle_level_irq, 0,
0104                          IRQ_NOPROBE | IRQ_LEVEL, 0);
0105     if (err)
0106         goto out_domain_remove;
0107
0108     for (i = 0; i < num_chips; i++) {
0109         gc = irq_get_domain_generic_chip(domain, i * 32);
0110
0111         gc->wake_enabled = IRQ_MSK(32);
0112         gc->reg_base = intc->base + (i * CHIP_SIZE);
0113
0114         ct = gc->chip_types;
0115         ct->regs.enable = JZ_REG_INTC_CLEAR_MASK;
0116         ct->regs.disable = JZ_REG_INTC_SET_MASK;
0117         ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
0118         ct->chip.irq_mask = irq_gc_mask_disable_reg;
0119         ct->chip.irq_mask_ack = irq_gc_mask_disable_reg;
0120         ct->chip.irq_set_wake = irq_gc_set_wake;
0121         ct->chip.flags = IRQCHIP_MASK_ON_SUSPEND;
0122
0123         /* Mask all irqs */
0124         irq_reg_writel(gc, IRQ_MSK(32), JZ_REG_INTC_SET_MASK);
0125     }
0126
0127     if (request_irq(parent_irq, intc_cascade, IRQF_NO_SUSPEND,
0128             "SoC intc cascade interrupt", NULL))
0129         pr_err("Failed to register SoC intc cascade interrupt\n");
0130     return 0;
0131
0132 out_domain_remove:
0133     irq_domain_remove(domain);
0134 out_unmap_base:
0135     iounmap(intc->base);
0136 out_unmap_irq:
0137     irq_dispose_mapping(parent_irq);
0138 out_free:
0139     kfree(intc);
0140 out_err:
0141     return err;
0142 }
0143
0144 static int __init intc_1chip_of_init(struct device_node *node,
0145                      struct device_node *parent)
0146 {
0147     return ingenic_intc_of_init(node, 1);
0148 }
0149 IRQCHIP_DECLARE(jz4740_intc, "ingenic,jz4740-intc", intc_1chip_of_init);
0150 IRQCHIP_DECLARE(jz4725b_intc, "ingenic,jz4725b-intc", intc_1chip_of_init);
0151
0152 static int __init intc_2chip_of_init(struct device_node *node,
0153     struct device_node *parent)
0154 {
0155     return ingenic_intc_of_init(node, 2);
0156 }
0157 IRQCHIP_DECLARE(jz4760_intc, "ingenic,jz4760-intc", intc_2chip_of_init);
0158 IRQCHIP_DECLARE(jz4770_intc, "ingenic,jz4770-intc", intc_2chip_of_init);
0159 IRQCHIP_DECLARE(jz4775_intc, "ingenic,jz4775-intc", intc_2chip_of_init);
0160 IRQCHIP_DECLARE(jz4780_intc, "ingenic,jz4780-intc", intc_2chip_of_init);