drivers/irqchip/irq-gic-v3-mbi.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (C) 2018 ARM Limited, All Rights Reserved.
0004  * Author: Marc Zyngier <marc.zyngier@arm.com>
0005  */
0006
0007 #define pr_fmt(fmt) "GICv3: " fmt
0008
0009 #include <linux/dma-iommu.h>
0010 #include <linux/irq.h>
0011 #include <linux/irqdomain.h>
0012 #include <linux/kernel.h>
0013 #include <linux/msi.h>
0014 #include <linux/of_address.h>
0015 #include <linux/of_pci.h>
0016 #include <linux/slab.h>
0017 #include <linux/spinlock.h>
0018
0019 #include <linux/irqchip/arm-gic-v3.h>
0020
0021 struct mbi_range {
0022     u32         spi_start;
0023     u32         nr_spis;
0024     unsigned long       *bm;
0025 };
0026
0027 static DEFINE_MUTEX(mbi_lock);
0028 static phys_addr_t      mbi_phys_base;
0029 static struct mbi_range     *mbi_ranges;
0030 static unsigned int     mbi_range_nr;
0031
0032 static struct irq_chip mbi_irq_chip = {
0033     .name           = "MBI",
0034     .irq_mask       = irq_chip_mask_parent,
0035     .irq_unmask     = irq_chip_unmask_parent,
0036     .irq_eoi        = irq_chip_eoi_parent,
0037     .irq_set_type       = irq_chip_set_type_parent,
0038     .irq_set_affinity   = irq_chip_set_affinity_parent,
0039 };
0040
0041 static int mbi_irq_gic_domain_alloc(struct irq_domain *domain,
0042                        unsigned int virq,
0043                        irq_hw_number_t hwirq)
0044 {
0045     struct irq_fwspec fwspec;
0046     struct irq_data *d;
0047     int err;
0048
0049     /*
0050      * Using ACPI? There is no MBI support in the spec, you
0051      * shouldn't even be here.
0052      */
0053     if (!is_of_node(domain->parent->fwnode))
0054         return -EINVAL;
0055
0056     /*
0057      * Let's default to edge. This is consistent with traditional
0058      * MSIs, and systems requiring level signaling will just
0059      * enforce the trigger on their own.
0060      */
0061     fwspec.fwnode = domain->parent->fwnode;
0062     fwspec.param_count = 3;
0063     fwspec.param[0] = 0;
0064     fwspec.param[1] = hwirq - 32;
0065     fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
0066
0067     err = irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
0068     if (err)
0069         return err;
0070
0071     d = irq_domain_get_irq_data(domain->parent, virq);
0072     return d->chip->irq_set_type(d, IRQ_TYPE_EDGE_RISING);
0073 }
0074
0075 static void mbi_free_msi(struct mbi_range *mbi, unsigned int hwirq,
0076              int nr_irqs)
0077 {
0078     mutex_lock(&mbi_lock);
0079     bitmap_release_region(mbi->bm, hwirq - mbi->spi_start,
0080                   get_count_order(nr_irqs));
0081     mutex_unlock(&mbi_lock);
0082 }
0083
0084 static int mbi_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
0085                    unsigned int nr_irqs, void *args)
0086 {
0087     msi_alloc_info_t *info = args;
0088     struct mbi_range *mbi = NULL;
0089     int hwirq, offset, i, err = 0;
0090
0091     mutex_lock(&mbi_lock);
0092     for (i = 0; i < mbi_range_nr; i++) {
0093         offset = bitmap_find_free_region(mbi_ranges[i].bm,
0094                          mbi_ranges[i].nr_spis,
0095                          get_count_order(nr_irqs));
0096         if (offset >= 0) {
0097             mbi = &mbi_ranges[i];
0098             break;
0099         }
0100     }
0101     mutex_unlock(&mbi_lock);
0102
0103     if (!mbi)
0104         return -ENOSPC;
0105
0106     hwirq = mbi->spi_start + offset;
0107
0108     err = iommu_dma_prepare_msi(info->desc,
0109                     mbi_phys_base + GICD_SETSPI_NSR);
0110     if (err)
0111         return err;
0112
0113     for (i = 0; i < nr_irqs; i++) {
0114         err = mbi_irq_gic_domain_alloc(domain, virq + i, hwirq + i);
0115         if (err)
0116             goto fail;
0117
0118         irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
0119                           &mbi_irq_chip, mbi);
0120     }
0121
0122     return 0;
0123
0124 fail:
0125     irq_domain_free_irqs_parent(domain, virq, nr_irqs);
0126     mbi_free_msi(mbi, hwirq, nr_irqs);
0127     return err;
0128 }
0129
0130 static void mbi_irq_domain_free(struct irq_domain *domain,
0131                 unsigned int virq, unsigned int nr_irqs)
0132 {
0133     struct irq_data *d = irq_domain_get_irq_data(domain, virq);
0134     struct mbi_range *mbi = irq_data_get_irq_chip_data(d);
0135
0136     mbi_free_msi(mbi, d->hwirq, nr_irqs);
0137     irq_domain_free_irqs_parent(domain, virq, nr_irqs);
0138 }
0139
0140 static const struct irq_domain_ops mbi_domain_ops = {
0141     .alloc          = mbi_irq_domain_alloc,
0142     .free           = mbi_irq_domain_free,
0143 };
0144
0145 static void mbi_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
0146 {
0147     msg[0].address_hi = upper_32_bits(mbi_phys_base + GICD_SETSPI_NSR);
0148     msg[0].address_lo = lower_32_bits(mbi_phys_base + GICD_SETSPI_NSR);
0149     msg[0].data = data->parent_data->hwirq;
0150
0151     iommu_dma_compose_msi_msg(irq_data_get_msi_desc(data), msg);
0152 }
0153
0154 #ifdef CONFIG_PCI_MSI
0155 /* PCI-specific irqchip */
0156 static void mbi_mask_msi_irq(struct irq_data *d)
0157 {
0158     pci_msi_mask_irq(d);
0159     irq_chip_mask_parent(d);
0160 }
0161
0162 static void mbi_unmask_msi_irq(struct irq_data *d)
0163 {
0164     pci_msi_unmask_irq(d);
0165     irq_chip_unmask_parent(d);
0166 }
0167
0168 static struct irq_chip mbi_msi_irq_chip = {
0169     .name           = "MSI",
0170     .irq_mask       = mbi_mask_msi_irq,
0171     .irq_unmask     = mbi_unmask_msi_irq,
0172     .irq_eoi        = irq_chip_eoi_parent,
0173     .irq_compose_msi_msg    = mbi_compose_msi_msg,
0174 };
0175
0176 static struct msi_domain_info mbi_msi_domain_info = {
0177     .flags  = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
0178            MSI_FLAG_PCI_MSIX | MSI_FLAG_MULTI_PCI_MSI),
0179     .chip   = &mbi_msi_irq_chip,
0180 };
0181
0182 static int mbi_allocate_pci_domain(struct irq_domain *nexus_domain,
0183                    struct irq_domain **pci_domain)
0184 {
0185     *pci_domain = pci_msi_create_irq_domain(nexus_domain->parent->fwnode,
0186                         &mbi_msi_domain_info,
0187                         nexus_domain);
0188     if (!*pci_domain)
0189         return -ENOMEM;
0190
0191     return 0;
0192 }
0193 #else
0194 static int mbi_allocate_pci_domain(struct irq_domain *nexus_domain,
0195                    struct irq_domain **pci_domain)
0196 {
0197     *pci_domain = NULL;
0198     return 0;
0199 }
0200 #endif
0201
0202 static void mbi_compose_mbi_msg(struct irq_data *data, struct msi_msg *msg)
0203 {
0204     mbi_compose_msi_msg(data, msg);
0205
0206     msg[1].address_hi = upper_32_bits(mbi_phys_base + GICD_CLRSPI_NSR);
0207     msg[1].address_lo = lower_32_bits(mbi_phys_base + GICD_CLRSPI_NSR);
0208     msg[1].data = data->parent_data->hwirq;
0209
0210     iommu_dma_compose_msi_msg(irq_data_get_msi_desc(data), &msg[1]);
0211 }
0212
0213 /* Platform-MSI specific irqchip */
0214 static struct irq_chip mbi_pmsi_irq_chip = {
0215     .name           = "pMSI",
0216     .irq_set_type       = irq_chip_set_type_parent,
0217     .irq_compose_msi_msg    = mbi_compose_mbi_msg,
0218     .flags          = IRQCHIP_SUPPORTS_LEVEL_MSI,
0219 };
0220
0221 static struct msi_domain_ops mbi_pmsi_ops = {
0222 };
0223
0224 static struct msi_domain_info mbi_pmsi_domain_info = {
0225     .flags  = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
0226            MSI_FLAG_LEVEL_CAPABLE),
0227     .ops    = &mbi_pmsi_ops,
0228     .chip   = &mbi_pmsi_irq_chip,
0229 };
0230
0231 static int mbi_allocate_domains(struct irq_domain *parent)
0232 {
0233     struct irq_domain *nexus_domain, *pci_domain, *plat_domain;
0234     int err;
0235
0236     nexus_domain = irq_domain_create_tree(parent->fwnode,
0237                           &mbi_domain_ops, NULL);
0238     if (!nexus_domain)
0239         return -ENOMEM;
0240
0241     irq_domain_update_bus_token(nexus_domain, DOMAIN_BUS_NEXUS);
0242     nexus_domain->parent = parent;
0243
0244     err = mbi_allocate_pci_domain(nexus_domain, &pci_domain);
0245
0246     plat_domain = platform_msi_create_irq_domain(parent->fwnode,
0247                              &mbi_pmsi_domain_info,
0248                              nexus_domain);
0249
0250     if (err || !plat_domain) {
0251         if (plat_domain)
0252             irq_domain_remove(plat_domain);
0253         if (pci_domain)
0254             irq_domain_remove(pci_domain);
0255         irq_domain_remove(nexus_domain);
0256         return -ENOMEM;
0257     }
0258
0259     return 0;
0260 }
0261
0262 int __init mbi_init(struct fwnode_handle *fwnode, struct irq_domain *parent)
0263 {
0264     struct device_node *np;
0265     const __be32 *reg;
0266     int ret, n;
0267
0268     np = to_of_node(fwnode);
0269
0270     if (!of_property_read_bool(np, "msi-controller"))
0271         return 0;
0272
0273     n = of_property_count_elems_of_size(np, "mbi-ranges", sizeof(u32));
0274     if (n <= 0 || n % 2)
0275         return -EINVAL;
0276
0277     mbi_range_nr = n / 2;
0278     mbi_ranges = kcalloc(mbi_range_nr, sizeof(*mbi_ranges), GFP_KERNEL);
0279     if (!mbi_ranges)
0280         return -ENOMEM;
0281
0282     for (n = 0; n < mbi_range_nr; n++) {
0283         ret = of_property_read_u32_index(np, "mbi-ranges", n * 2,
0284                          &mbi_ranges[n].spi_start);
0285         if (ret)
0286             goto err_free_mbi;
0287         ret = of_property_read_u32_index(np, "mbi-ranges", n * 2 + 1,
0288                          &mbi_ranges[n].nr_spis);
0289         if (ret)
0290             goto err_free_mbi;
0291
0292         mbi_ranges[n].bm = bitmap_zalloc(mbi_ranges[n].nr_spis, GFP_KERNEL);
0293         if (!mbi_ranges[n].bm) {
0294             ret = -ENOMEM;
0295             goto err_free_mbi;
0296         }
0297         pr_info("MBI range [%d:%d]\n", mbi_ranges[n].spi_start,
0298             mbi_ranges[n].spi_start + mbi_ranges[n].nr_spis - 1);
0299     }
0300
0301     reg = of_get_property(np, "mbi-alias", NULL);
0302     if (reg) {
0303         mbi_phys_base = of_translate_address(np, reg);
0304         if (mbi_phys_base == (phys_addr_t)OF_BAD_ADDR) {
0305             ret = -ENXIO;
0306             goto err_free_mbi;
0307         }
0308     } else {
0309         struct resource res;
0310
0311         if (of_address_to_resource(np, 0, &res)) {
0312             ret = -ENXIO;
0313             goto err_free_mbi;
0314         }
0315
0316         mbi_phys_base = res.start;
0317     }
0318
0319     pr_info("Using MBI frame %pa\n", &mbi_phys_base);
0320
0321     ret = mbi_allocate_domains(parent);
0322     if (ret)
0323         goto err_free_mbi;
0324
0325     return 0;
0326
0327 err_free_mbi:
0328     if (mbi_ranges) {
0329         for (n = 0; n < mbi_range_nr; n++)
0330             bitmap_free(mbi_ranges[n].bm);
0331         kfree(mbi_ranges);
0332     }
0333
0334     return ret;
0335 }