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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * ARM GIC v2m MSI(-X) support
0004  * Support for Message Signaled Interrupts for systems that
0005  * implement ARM Generic Interrupt Controller: GICv2m.
0006  *
0007  * Copyright (C) 2014 Advanced Micro Devices, Inc.
0008  * Authors: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
0009  *      Harish Kasiviswanathan <harish.kasiviswanathan@amd.com>
0010  *      Brandon Anderson <brandon.anderson@amd.com>
0011  */
0012 
0013 #define pr_fmt(fmt) "GICv2m: " fmt
0014 
0015 #include <linux/acpi.h>
0016 #include <linux/dma-iommu.h>
0017 #include <linux/irq.h>
0018 #include <linux/irqdomain.h>
0019 #include <linux/kernel.h>
0020 #include <linux/pci.h>
0021 #include <linux/msi.h>
0022 #include <linux/of_address.h>
0023 #include <linux/of_pci.h>
0024 #include <linux/slab.h>
0025 #include <linux/spinlock.h>
0026 #include <linux/irqchip/arm-gic.h>
0027 
0028 /*
0029 * MSI_TYPER:
0030 *     [31:26] Reserved
0031 *     [25:16] lowest SPI assigned to MSI
0032 *     [15:10] Reserved
0033 *     [9:0]   Numer of SPIs assigned to MSI
0034 */
0035 #define V2M_MSI_TYPER              0x008
0036 #define V2M_MSI_TYPER_BASE_SHIFT       16
0037 #define V2M_MSI_TYPER_BASE_MASK        0x3FF
0038 #define V2M_MSI_TYPER_NUM_MASK         0x3FF
0039 #define V2M_MSI_SETSPI_NS          0x040
0040 #define V2M_MIN_SPI            32
0041 #define V2M_MAX_SPI            1019
0042 #define V2M_MSI_IIDR               0xFCC
0043 
0044 #define V2M_MSI_TYPER_BASE_SPI(x)      \
0045            (((x) >> V2M_MSI_TYPER_BASE_SHIFT) & V2M_MSI_TYPER_BASE_MASK)
0046 
0047 #define V2M_MSI_TYPER_NUM_SPI(x)       ((x) & V2M_MSI_TYPER_NUM_MASK)
0048 
0049 /* APM X-Gene with GICv2m MSI_IIDR register value */
0050 #define XGENE_GICV2M_MSI_IIDR       0x06000170
0051 
0052 /* Broadcom NS2 GICv2m MSI_IIDR register value */
0053 #define BCM_NS2_GICV2M_MSI_IIDR     0x0000013f
0054 
0055 /* List of flags for specific v2m implementation */
0056 #define GICV2M_NEEDS_SPI_OFFSET     0x00000001
0057 #define GICV2M_GRAVITON_ADDRESS_ONLY    0x00000002
0058 
0059 static LIST_HEAD(v2m_nodes);
0060 static DEFINE_SPINLOCK(v2m_lock);
0061 
0062 struct v2m_data {
0063     struct list_head entry;
0064     struct fwnode_handle *fwnode;
0065     struct resource res;    /* GICv2m resource */
0066     void __iomem *base; /* GICv2m virt address */
0067     u32 spi_start;      /* The SPI number that MSIs start */
0068     u32 nr_spis;        /* The number of SPIs for MSIs */
0069     u32 spi_offset;     /* offset to be subtracted from SPI number */
0070     unsigned long *bm;  /* MSI vector bitmap */
0071     u32 flags;      /* v2m flags for specific implementation */
0072 };
0073 
0074 static void gicv2m_mask_msi_irq(struct irq_data *d)
0075 {
0076     pci_msi_mask_irq(d);
0077     irq_chip_mask_parent(d);
0078 }
0079 
0080 static void gicv2m_unmask_msi_irq(struct irq_data *d)
0081 {
0082     pci_msi_unmask_irq(d);
0083     irq_chip_unmask_parent(d);
0084 }
0085 
0086 static struct irq_chip gicv2m_msi_irq_chip = {
0087     .name           = "MSI",
0088     .irq_mask       = gicv2m_mask_msi_irq,
0089     .irq_unmask     = gicv2m_unmask_msi_irq,
0090     .irq_eoi        = irq_chip_eoi_parent,
0091 };
0092 
0093 static struct msi_domain_info gicv2m_msi_domain_info = {
0094     .flags  = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
0095            MSI_FLAG_PCI_MSIX | MSI_FLAG_MULTI_PCI_MSI),
0096     .chip   = &gicv2m_msi_irq_chip,
0097 };
0098 
0099 static phys_addr_t gicv2m_get_msi_addr(struct v2m_data *v2m, int hwirq)
0100 {
0101     if (v2m->flags & GICV2M_GRAVITON_ADDRESS_ONLY)
0102         return v2m->res.start | ((hwirq - 32) << 3);
0103     else
0104         return v2m->res.start + V2M_MSI_SETSPI_NS;
0105 }
0106 
0107 static void gicv2m_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
0108 {
0109     struct v2m_data *v2m = irq_data_get_irq_chip_data(data);
0110     phys_addr_t addr = gicv2m_get_msi_addr(v2m, data->hwirq);
0111 
0112     msg->address_hi = upper_32_bits(addr);
0113     msg->address_lo = lower_32_bits(addr);
0114 
0115     if (v2m->flags & GICV2M_GRAVITON_ADDRESS_ONLY)
0116         msg->data = 0;
0117     else
0118         msg->data = data->hwirq;
0119     if (v2m->flags & GICV2M_NEEDS_SPI_OFFSET)
0120         msg->data -= v2m->spi_offset;
0121 
0122     iommu_dma_compose_msi_msg(irq_data_get_msi_desc(data), msg);
0123 }
0124 
0125 static struct irq_chip gicv2m_irq_chip = {
0126     .name           = "GICv2m",
0127     .irq_mask       = irq_chip_mask_parent,
0128     .irq_unmask     = irq_chip_unmask_parent,
0129     .irq_eoi        = irq_chip_eoi_parent,
0130     .irq_set_affinity   = irq_chip_set_affinity_parent,
0131     .irq_compose_msi_msg    = gicv2m_compose_msi_msg,
0132 };
0133 
0134 static int gicv2m_irq_gic_domain_alloc(struct irq_domain *domain,
0135                        unsigned int virq,
0136                        irq_hw_number_t hwirq)
0137 {
0138     struct irq_fwspec fwspec;
0139     struct irq_data *d;
0140     int err;
0141 
0142     if (is_of_node(domain->parent->fwnode)) {
0143         fwspec.fwnode = domain->parent->fwnode;
0144         fwspec.param_count = 3;
0145         fwspec.param[0] = 0;
0146         fwspec.param[1] = hwirq - 32;
0147         fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
0148     } else if (is_fwnode_irqchip(domain->parent->fwnode)) {
0149         fwspec.fwnode = domain->parent->fwnode;
0150         fwspec.param_count = 2;
0151         fwspec.param[0] = hwirq;
0152         fwspec.param[1] = IRQ_TYPE_EDGE_RISING;
0153     } else {
0154         return -EINVAL;
0155     }
0156 
0157     err = irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
0158     if (err)
0159         return err;
0160 
0161     /* Configure the interrupt line to be edge */
0162     d = irq_domain_get_irq_data(domain->parent, virq);
0163     d->chip->irq_set_type(d, IRQ_TYPE_EDGE_RISING);
0164     return 0;
0165 }
0166 
0167 static void gicv2m_unalloc_msi(struct v2m_data *v2m, unsigned int hwirq,
0168                    int nr_irqs)
0169 {
0170     spin_lock(&v2m_lock);
0171     bitmap_release_region(v2m->bm, hwirq - v2m->spi_start,
0172                   get_count_order(nr_irqs));
0173     spin_unlock(&v2m_lock);
0174 }
0175 
0176 static int gicv2m_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
0177                    unsigned int nr_irqs, void *args)
0178 {
0179     msi_alloc_info_t *info = args;
0180     struct v2m_data *v2m = NULL, *tmp;
0181     int hwirq, offset, i, err = 0;
0182 
0183     spin_lock(&v2m_lock);
0184     list_for_each_entry(tmp, &v2m_nodes, entry) {
0185         offset = bitmap_find_free_region(tmp->bm, tmp->nr_spis,
0186                          get_count_order(nr_irqs));
0187         if (offset >= 0) {
0188             v2m = tmp;
0189             break;
0190         }
0191     }
0192     spin_unlock(&v2m_lock);
0193 
0194     if (!v2m)
0195         return -ENOSPC;
0196 
0197     hwirq = v2m->spi_start + offset;
0198 
0199     err = iommu_dma_prepare_msi(info->desc,
0200                     gicv2m_get_msi_addr(v2m, hwirq));
0201     if (err)
0202         return err;
0203 
0204     for (i = 0; i < nr_irqs; i++) {
0205         err = gicv2m_irq_gic_domain_alloc(domain, virq + i, hwirq + i);
0206         if (err)
0207             goto fail;
0208 
0209         irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
0210                           &gicv2m_irq_chip, v2m);
0211     }
0212 
0213     return 0;
0214 
0215 fail:
0216     irq_domain_free_irqs_parent(domain, virq, nr_irqs);
0217     gicv2m_unalloc_msi(v2m, hwirq, nr_irqs);
0218     return err;
0219 }
0220 
0221 static void gicv2m_irq_domain_free(struct irq_domain *domain,
0222                    unsigned int virq, unsigned int nr_irqs)
0223 {
0224     struct irq_data *d = irq_domain_get_irq_data(domain, virq);
0225     struct v2m_data *v2m = irq_data_get_irq_chip_data(d);
0226 
0227     gicv2m_unalloc_msi(v2m, d->hwirq, nr_irqs);
0228     irq_domain_free_irqs_parent(domain, virq, nr_irqs);
0229 }
0230 
0231 static const struct irq_domain_ops gicv2m_domain_ops = {
0232     .alloc          = gicv2m_irq_domain_alloc,
0233     .free           = gicv2m_irq_domain_free,
0234 };
0235 
0236 static bool is_msi_spi_valid(u32 base, u32 num)
0237 {
0238     if (base < V2M_MIN_SPI) {
0239         pr_err("Invalid MSI base SPI (base:%u)\n", base);
0240         return false;
0241     }
0242 
0243     if ((num == 0) || (base + num > V2M_MAX_SPI)) {
0244         pr_err("Number of SPIs (%u) exceed maximum (%u)\n",
0245                num, V2M_MAX_SPI - V2M_MIN_SPI + 1);
0246         return false;
0247     }
0248 
0249     return true;
0250 }
0251 
0252 static struct irq_chip gicv2m_pmsi_irq_chip = {
0253     .name           = "pMSI",
0254 };
0255 
0256 static struct msi_domain_ops gicv2m_pmsi_ops = {
0257 };
0258 
0259 static struct msi_domain_info gicv2m_pmsi_domain_info = {
0260     .flags  = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS),
0261     .ops    = &gicv2m_pmsi_ops,
0262     .chip   = &gicv2m_pmsi_irq_chip,
0263 };
0264 
0265 static void gicv2m_teardown(void)
0266 {
0267     struct v2m_data *v2m, *tmp;
0268 
0269     list_for_each_entry_safe(v2m, tmp, &v2m_nodes, entry) {
0270         list_del(&v2m->entry);
0271         bitmap_free(v2m->bm);
0272         iounmap(v2m->base);
0273         of_node_put(to_of_node(v2m->fwnode));
0274         if (is_fwnode_irqchip(v2m->fwnode))
0275             irq_domain_free_fwnode(v2m->fwnode);
0276         kfree(v2m);
0277     }
0278 }
0279 
0280 static int gicv2m_allocate_domains(struct irq_domain *parent)
0281 {
0282     struct irq_domain *inner_domain, *pci_domain, *plat_domain;
0283     struct v2m_data *v2m;
0284 
0285     v2m = list_first_entry_or_null(&v2m_nodes, struct v2m_data, entry);
0286     if (!v2m)
0287         return 0;
0288 
0289     inner_domain = irq_domain_create_tree(v2m->fwnode,
0290                           &gicv2m_domain_ops, v2m);
0291     if (!inner_domain) {
0292         pr_err("Failed to create GICv2m domain\n");
0293         return -ENOMEM;
0294     }
0295 
0296     irq_domain_update_bus_token(inner_domain, DOMAIN_BUS_NEXUS);
0297     inner_domain->parent = parent;
0298     pci_domain = pci_msi_create_irq_domain(v2m->fwnode,
0299                            &gicv2m_msi_domain_info,
0300                            inner_domain);
0301     plat_domain = platform_msi_create_irq_domain(v2m->fwnode,
0302                              &gicv2m_pmsi_domain_info,
0303                              inner_domain);
0304     if (!pci_domain || !plat_domain) {
0305         pr_err("Failed to create MSI domains\n");
0306         if (plat_domain)
0307             irq_domain_remove(plat_domain);
0308         if (pci_domain)
0309             irq_domain_remove(pci_domain);
0310         irq_domain_remove(inner_domain);
0311         return -ENOMEM;
0312     }
0313 
0314     return 0;
0315 }
0316 
0317 static int __init gicv2m_init_one(struct fwnode_handle *fwnode,
0318                   u32 spi_start, u32 nr_spis,
0319                   struct resource *res, u32 flags)
0320 {
0321     int ret;
0322     struct v2m_data *v2m;
0323 
0324     v2m = kzalloc(sizeof(struct v2m_data), GFP_KERNEL);
0325     if (!v2m)
0326         return -ENOMEM;
0327 
0328     INIT_LIST_HEAD(&v2m->entry);
0329     v2m->fwnode = fwnode;
0330     v2m->flags = flags;
0331 
0332     memcpy(&v2m->res, res, sizeof(struct resource));
0333 
0334     v2m->base = ioremap(v2m->res.start, resource_size(&v2m->res));
0335     if (!v2m->base) {
0336         pr_err("Failed to map GICv2m resource\n");
0337         ret = -ENOMEM;
0338         goto err_free_v2m;
0339     }
0340 
0341     if (spi_start && nr_spis) {
0342         v2m->spi_start = spi_start;
0343         v2m->nr_spis = nr_spis;
0344     } else {
0345         u32 typer;
0346 
0347         /* Graviton should always have explicit spi_start/nr_spis */
0348         if (v2m->flags & GICV2M_GRAVITON_ADDRESS_ONLY) {
0349             ret = -EINVAL;
0350             goto err_iounmap;
0351         }
0352         typer = readl_relaxed(v2m->base + V2M_MSI_TYPER);
0353 
0354         v2m->spi_start = V2M_MSI_TYPER_BASE_SPI(typer);
0355         v2m->nr_spis = V2M_MSI_TYPER_NUM_SPI(typer);
0356     }
0357 
0358     if (!is_msi_spi_valid(v2m->spi_start, v2m->nr_spis)) {
0359         ret = -EINVAL;
0360         goto err_iounmap;
0361     }
0362 
0363     /*
0364      * APM X-Gene GICv2m implementation has an erratum where
0365      * the MSI data needs to be the offset from the spi_start
0366      * in order to trigger the correct MSI interrupt. This is
0367      * different from the standard GICv2m implementation where
0368      * the MSI data is the absolute value within the range from
0369      * spi_start to (spi_start + num_spis).
0370      *
0371      * Broadcom NS2 GICv2m implementation has an erratum where the MSI data
0372      * is 'spi_number - 32'
0373      *
0374      * Reading that register fails on the Graviton implementation
0375      */
0376     if (!(v2m->flags & GICV2M_GRAVITON_ADDRESS_ONLY)) {
0377         switch (readl_relaxed(v2m->base + V2M_MSI_IIDR)) {
0378         case XGENE_GICV2M_MSI_IIDR:
0379             v2m->flags |= GICV2M_NEEDS_SPI_OFFSET;
0380             v2m->spi_offset = v2m->spi_start;
0381             break;
0382         case BCM_NS2_GICV2M_MSI_IIDR:
0383             v2m->flags |= GICV2M_NEEDS_SPI_OFFSET;
0384             v2m->spi_offset = 32;
0385             break;
0386         }
0387     }
0388     v2m->bm = bitmap_zalloc(v2m->nr_spis, GFP_KERNEL);
0389     if (!v2m->bm) {
0390         ret = -ENOMEM;
0391         goto err_iounmap;
0392     }
0393 
0394     list_add_tail(&v2m->entry, &v2m_nodes);
0395 
0396     pr_info("range%pR, SPI[%d:%d]\n", res,
0397         v2m->spi_start, (v2m->spi_start + v2m->nr_spis - 1));
0398     return 0;
0399 
0400 err_iounmap:
0401     iounmap(v2m->base);
0402 err_free_v2m:
0403     kfree(v2m);
0404     return ret;
0405 }
0406 
0407 static const struct of_device_id gicv2m_device_id[] = {
0408     {   .compatible = "arm,gic-v2m-frame",  },
0409     {},
0410 };
0411 
0412 static int __init gicv2m_of_init(struct fwnode_handle *parent_handle,
0413                  struct irq_domain *parent)
0414 {
0415     int ret = 0;
0416     struct device_node *node = to_of_node(parent_handle);
0417     struct device_node *child;
0418 
0419     for (child = of_find_matching_node(node, gicv2m_device_id); child;
0420          child = of_find_matching_node(child, gicv2m_device_id)) {
0421         u32 spi_start = 0, nr_spis = 0;
0422         struct resource res;
0423 
0424         if (!of_find_property(child, "msi-controller", NULL))
0425             continue;
0426 
0427         ret = of_address_to_resource(child, 0, &res);
0428         if (ret) {
0429             pr_err("Failed to allocate v2m resource.\n");
0430             break;
0431         }
0432 
0433         if (!of_property_read_u32(child, "arm,msi-base-spi",
0434                       &spi_start) &&
0435             !of_property_read_u32(child, "arm,msi-num-spis", &nr_spis))
0436             pr_info("DT overriding V2M MSI_TYPER (base:%u, num:%u)\n",
0437                 spi_start, nr_spis);
0438 
0439         ret = gicv2m_init_one(&child->fwnode, spi_start, nr_spis,
0440                       &res, 0);
0441         if (ret) {
0442             of_node_put(child);
0443             break;
0444         }
0445     }
0446 
0447     if (!ret)
0448         ret = gicv2m_allocate_domains(parent);
0449     if (ret)
0450         gicv2m_teardown();
0451     return ret;
0452 }
0453 
0454 #ifdef CONFIG_ACPI
0455 static int acpi_num_msi;
0456 
0457 static struct fwnode_handle *gicv2m_get_fwnode(struct device *dev)
0458 {
0459     struct v2m_data *data;
0460 
0461     if (WARN_ON(acpi_num_msi <= 0))
0462         return NULL;
0463 
0464     /* We only return the fwnode of the first MSI frame. */
0465     data = list_first_entry_or_null(&v2m_nodes, struct v2m_data, entry);
0466     if (!data)
0467         return NULL;
0468 
0469     return data->fwnode;
0470 }
0471 
0472 static bool acpi_check_amazon_graviton_quirks(void)
0473 {
0474     static struct acpi_table_madt *madt;
0475     acpi_status status;
0476     bool rc = false;
0477 
0478 #define ACPI_AMZN_OEM_ID        "AMAZON"
0479 
0480     status = acpi_get_table(ACPI_SIG_MADT, 0,
0481                 (struct acpi_table_header **)&madt);
0482 
0483     if (ACPI_FAILURE(status) || !madt)
0484         return rc;
0485     rc = !memcmp(madt->header.oem_id, ACPI_AMZN_OEM_ID, ACPI_OEM_ID_SIZE);
0486     acpi_put_table((struct acpi_table_header *)madt);
0487 
0488     return rc;
0489 }
0490 
0491 static int __init
0492 acpi_parse_madt_msi(union acpi_subtable_headers *header,
0493             const unsigned long end)
0494 {
0495     int ret;
0496     struct resource res;
0497     u32 spi_start = 0, nr_spis = 0;
0498     struct acpi_madt_generic_msi_frame *m;
0499     struct fwnode_handle *fwnode;
0500     u32 flags = 0;
0501 
0502     m = (struct acpi_madt_generic_msi_frame *)header;
0503     if (BAD_MADT_ENTRY(m, end))
0504         return -EINVAL;
0505 
0506     res.start = m->base_address;
0507     res.end = m->base_address + SZ_4K - 1;
0508     res.flags = IORESOURCE_MEM;
0509 
0510     if (acpi_check_amazon_graviton_quirks()) {
0511         pr_info("applying Amazon Graviton quirk\n");
0512         res.end = res.start + SZ_8K - 1;
0513         flags |= GICV2M_GRAVITON_ADDRESS_ONLY;
0514         gicv2m_msi_domain_info.flags &= ~MSI_FLAG_MULTI_PCI_MSI;
0515     }
0516 
0517     if (m->flags & ACPI_MADT_OVERRIDE_SPI_VALUES) {
0518         spi_start = m->spi_base;
0519         nr_spis = m->spi_count;
0520 
0521         pr_info("ACPI overriding V2M MSI_TYPER (base:%u, num:%u)\n",
0522             spi_start, nr_spis);
0523     }
0524 
0525     fwnode = irq_domain_alloc_fwnode(&res.start);
0526     if (!fwnode) {
0527         pr_err("Unable to allocate GICv2m domain token\n");
0528         return -EINVAL;
0529     }
0530 
0531     ret = gicv2m_init_one(fwnode, spi_start, nr_spis, &res, flags);
0532     if (ret)
0533         irq_domain_free_fwnode(fwnode);
0534 
0535     return ret;
0536 }
0537 
0538 static int __init gicv2m_acpi_init(struct irq_domain *parent)
0539 {
0540     int ret;
0541 
0542     if (acpi_num_msi > 0)
0543         return 0;
0544 
0545     acpi_num_msi = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_MSI_FRAME,
0546                       acpi_parse_madt_msi, 0);
0547 
0548     if (acpi_num_msi <= 0)
0549         goto err_out;
0550 
0551     ret = gicv2m_allocate_domains(parent);
0552     if (ret)
0553         goto err_out;
0554 
0555     pci_msi_register_fwnode_provider(&gicv2m_get_fwnode);
0556 
0557     return 0;
0558 
0559 err_out:
0560     gicv2m_teardown();
0561     return -EINVAL;
0562 }
0563 #else /* CONFIG_ACPI */
0564 static int __init gicv2m_acpi_init(struct irq_domain *parent)
0565 {
0566     return -EINVAL;
0567 }
0568 #endif /* CONFIG_ACPI */
0569 
0570 int __init gicv2m_init(struct fwnode_handle *parent_handle,
0571                struct irq_domain *parent)
0572 {
0573     if (is_of_node(parent_handle))
0574         return gicv2m_of_init(parent_handle, parent);
0575 
0576     return gicv2m_acpi_init(parent);
0577 }
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