drivers/irqchip/irq-davinci-cp-intc.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 //
0003 // Author: Steve Chen <schen@mvista.com>
0004 // Copyright (C) 2008-2009, MontaVista Software, Inc. <source@mvista.com>
0005 // Author: Bartosz Golaszewski <bgolaszewski@baylibre.com>
0006 // Copyright (C) 2019, Texas Instruments
0007 //
0008 // TI Common Platform Interrupt Controller (cp_intc) driver
0009
0010 #include <linux/export.h>
0011 #include <linux/init.h>
0012 #include <linux/irq.h>
0013 #include <linux/irqchip.h>
0014 #include <linux/irqchip/irq-davinci-cp-intc.h>
0015 #include <linux/irqdomain.h>
0016 #include <linux/io.h>
0017 #include <linux/of.h>
0018 #include <linux/of_address.h>
0019 #include <linux/of_irq.h>
0020
0021 #include <asm/exception.h>
0022
0023 #define DAVINCI_CP_INTC_CTRL            0x04
0024 #define DAVINCI_CP_INTC_HOST_CTRL       0x0c
0025 #define DAVINCI_CP_INTC_GLOBAL_ENABLE       0x10
0026 #define DAVINCI_CP_INTC_SYS_STAT_IDX_CLR    0x24
0027 #define DAVINCI_CP_INTC_SYS_ENABLE_IDX_SET  0x28
0028 #define DAVINCI_CP_INTC_SYS_ENABLE_IDX_CLR  0x2c
0029 #define DAVINCI_CP_INTC_HOST_ENABLE_IDX_SET 0x34
0030 #define DAVINCI_CP_INTC_HOST_ENABLE_IDX_CLR 0x38
0031 #define DAVINCI_CP_INTC_PRIO_IDX        0x80
0032 #define DAVINCI_CP_INTC_SYS_STAT_CLR(n)     (0x0280 + (n << 2))
0033 #define DAVINCI_CP_INTC_SYS_ENABLE_CLR(n)   (0x0380 + (n << 2))
0034 #define DAVINCI_CP_INTC_CHAN_MAP(n)     (0x0400 + (n << 2))
0035 #define DAVINCI_CP_INTC_SYS_POLARITY(n)     (0x0d00 + (n << 2))
0036 #define DAVINCI_CP_INTC_SYS_TYPE(n)     (0x0d80 + (n << 2))
0037 #define DAVINCI_CP_INTC_HOST_ENABLE(n)      (0x1500 + (n << 2))
0038 #define DAVINCI_CP_INTC_PRI_INDX_MASK       GENMASK(9, 0)
0039 #define DAVINCI_CP_INTC_GPIR_NONE       BIT(31)
0040
0041 static void __iomem *davinci_cp_intc_base;
0042 static struct irq_domain *davinci_cp_intc_irq_domain;
0043
0044 static inline unsigned int davinci_cp_intc_read(unsigned int offset)
0045 {
0046     return readl_relaxed(davinci_cp_intc_base + offset);
0047 }
0048
0049 static inline void davinci_cp_intc_write(unsigned long value,
0050                      unsigned int offset)
0051 {
0052     writel_relaxed(value, davinci_cp_intc_base + offset);
0053 }
0054
0055 static void davinci_cp_intc_ack_irq(struct irq_data *d)
0056 {
0057     davinci_cp_intc_write(d->hwirq, DAVINCI_CP_INTC_SYS_STAT_IDX_CLR);
0058 }
0059
0060 static void davinci_cp_intc_mask_irq(struct irq_data *d)
0061 {
0062     /* XXX don't know why we need to disable nIRQ here... */
0063     davinci_cp_intc_write(1, DAVINCI_CP_INTC_HOST_ENABLE_IDX_CLR);
0064     davinci_cp_intc_write(d->hwirq, DAVINCI_CP_INTC_SYS_ENABLE_IDX_CLR);
0065     davinci_cp_intc_write(1, DAVINCI_CP_INTC_HOST_ENABLE_IDX_SET);
0066 }
0067
0068 static void davinci_cp_intc_unmask_irq(struct irq_data *d)
0069 {
0070     davinci_cp_intc_write(d->hwirq, DAVINCI_CP_INTC_SYS_ENABLE_IDX_SET);
0071 }
0072
0073 static int davinci_cp_intc_set_irq_type(struct irq_data *d,
0074                     unsigned int flow_type)
0075 {
0076     unsigned int reg, mask, polarity, type;
0077
0078     reg = BIT_WORD(d->hwirq);
0079     mask = BIT_MASK(d->hwirq);
0080     polarity = davinci_cp_intc_read(DAVINCI_CP_INTC_SYS_POLARITY(reg));
0081     type = davinci_cp_intc_read(DAVINCI_CP_INTC_SYS_TYPE(reg));
0082
0083     switch (flow_type) {
0084     case IRQ_TYPE_EDGE_RISING:
0085         polarity |= mask;
0086         type |= mask;
0087         break;
0088     case IRQ_TYPE_EDGE_FALLING:
0089         polarity &= ~mask;
0090         type |= mask;
0091         break;
0092     case IRQ_TYPE_LEVEL_HIGH:
0093         polarity |= mask;
0094         type &= ~mask;
0095         break;
0096     case IRQ_TYPE_LEVEL_LOW:
0097         polarity &= ~mask;
0098         type &= ~mask;
0099         break;
0100     default:
0101         return -EINVAL;
0102     }
0103
0104     davinci_cp_intc_write(polarity, DAVINCI_CP_INTC_SYS_POLARITY(reg));
0105     davinci_cp_intc_write(type, DAVINCI_CP_INTC_SYS_TYPE(reg));
0106
0107     return 0;
0108 }
0109
0110 static struct irq_chip davinci_cp_intc_irq_chip = {
0111     .name       = "cp_intc",
0112     .irq_ack    = davinci_cp_intc_ack_irq,
0113     .irq_mask   = davinci_cp_intc_mask_irq,
0114     .irq_unmask = davinci_cp_intc_unmask_irq,
0115     .irq_set_type   = davinci_cp_intc_set_irq_type,
0116     .flags      = IRQCHIP_SKIP_SET_WAKE,
0117 };
0118
0119 static asmlinkage void __exception_irq_entry
0120 davinci_cp_intc_handle_irq(struct pt_regs *regs)
0121 {
0122     int gpir, irqnr, none;
0123
0124     /*
0125      * The interrupt number is in first ten bits. The NONE field set to 1
0126      * indicates a spurious irq.
0127      */
0128
0129     gpir = davinci_cp_intc_read(DAVINCI_CP_INTC_PRIO_IDX);
0130     irqnr = gpir & DAVINCI_CP_INTC_PRI_INDX_MASK;
0131     none = gpir & DAVINCI_CP_INTC_GPIR_NONE;
0132
0133     if (unlikely(none)) {
0134         pr_err_once("%s: spurious irq!\n", __func__);
0135         return;
0136     }
0137
0138     generic_handle_domain_irq(davinci_cp_intc_irq_domain, irqnr);
0139 }
0140
0141 static int davinci_cp_intc_host_map(struct irq_domain *h, unsigned int virq,
0142               irq_hw_number_t hw)
0143 {
0144     pr_debug("cp_intc_host_map(%d, 0x%lx)\n", virq, hw);
0145
0146     irq_set_chip(virq, &davinci_cp_intc_irq_chip);
0147     irq_set_probe(virq);
0148     irq_set_handler(virq, handle_edge_irq);
0149
0150     return 0;
0151 }
0152
0153 static const struct irq_domain_ops davinci_cp_intc_irq_domain_ops = {
0154     .map = davinci_cp_intc_host_map,
0155     .xlate = irq_domain_xlate_onetwocell,
0156 };
0157
0158 static int __init
0159 davinci_cp_intc_do_init(const struct davinci_cp_intc_config *config,
0160             struct device_node *node)
0161 {
0162     unsigned int num_regs = BITS_TO_LONGS(config->num_irqs);
0163     int offset, irq_base;
0164     void __iomem *req;
0165
0166     req = request_mem_region(config->reg.start,
0167                  resource_size(&config->reg),
0168                  "davinci-cp-intc");
0169     if (!req) {
0170         pr_err("%s: register range busy\n", __func__);
0171         return -EBUSY;
0172     }
0173
0174     davinci_cp_intc_base = ioremap(config->reg.start,
0175                        resource_size(&config->reg));
0176     if (!davinci_cp_intc_base) {
0177         pr_err("%s: unable to ioremap register range\n", __func__);
0178         return -EINVAL;
0179     }
0180
0181     davinci_cp_intc_write(0, DAVINCI_CP_INTC_GLOBAL_ENABLE);
0182
0183     /* Disable all host interrupts */
0184     davinci_cp_intc_write(0, DAVINCI_CP_INTC_HOST_ENABLE(0));
0185
0186     /* Disable system interrupts */
0187     for (offset = 0; offset < num_regs; offset++)
0188         davinci_cp_intc_write(~0,
0189             DAVINCI_CP_INTC_SYS_ENABLE_CLR(offset));
0190
0191     /* Set to normal mode, no nesting, no priority hold */
0192     davinci_cp_intc_write(0, DAVINCI_CP_INTC_CTRL);
0193     davinci_cp_intc_write(0, DAVINCI_CP_INTC_HOST_CTRL);
0194
0195     /* Clear system interrupt status */
0196     for (offset = 0; offset < num_regs; offset++)
0197         davinci_cp_intc_write(~0,
0198             DAVINCI_CP_INTC_SYS_STAT_CLR(offset));
0199
0200     /* Enable nIRQ (what about nFIQ?) */
0201     davinci_cp_intc_write(1, DAVINCI_CP_INTC_HOST_ENABLE_IDX_SET);
0202
0203     /* Default all priorities to channel 7. */
0204     num_regs = (config->num_irqs + 3) >> 2; /* 4 channels per register */
0205     for (offset = 0; offset < num_regs; offset++)
0206         davinci_cp_intc_write(0x07070707,
0207             DAVINCI_CP_INTC_CHAN_MAP(offset));
0208
0209     irq_base = irq_alloc_descs(-1, 0, config->num_irqs, 0);
0210     if (irq_base < 0) {
0211         pr_err("%s: unable to allocate interrupt descriptors: %d\n",
0212                __func__, irq_base);
0213         return irq_base;
0214     }
0215
0216     davinci_cp_intc_irq_domain = irq_domain_add_legacy(
0217                     node, config->num_irqs, irq_base, 0,
0218                     &davinci_cp_intc_irq_domain_ops, NULL);
0219
0220     if (!davinci_cp_intc_irq_domain) {
0221         pr_err("%s: unable to create an interrupt domain\n", __func__);
0222         return -EINVAL;
0223     }
0224
0225     set_handle_irq(davinci_cp_intc_handle_irq);
0226
0227     /* Enable global interrupt */
0228     davinci_cp_intc_write(1, DAVINCI_CP_INTC_GLOBAL_ENABLE);
0229
0230     return 0;
0231 }
0232
0233 int __init davinci_cp_intc_init(const struct davinci_cp_intc_config *config)
0234 {
0235     return davinci_cp_intc_do_init(config, NULL);
0236 }
0237
0238 static int __init davinci_cp_intc_of_init(struct device_node *node,
0239                       struct device_node *parent)
0240 {
0241     struct davinci_cp_intc_config config = { };
0242     int ret;
0243
0244     ret = of_address_to_resource(node, 0, &config.reg);
0245     if (ret) {
0246         pr_err("%s: unable to get the register range from device-tree\n",
0247                __func__);
0248         return ret;
0249     }
0250
0251     ret = of_property_read_u32(node, "ti,intc-size", &config.num_irqs);
0252     if (ret) {
0253         pr_err("%s: unable to read the 'ti,intc-size' property\n",
0254                __func__);
0255         return ret;
0256     }
0257
0258     return davinci_cp_intc_do_init(&config, node);
0259 }
0260 IRQCHIP_DECLARE(cp_intc, "ti,cp-intc", davinci_cp_intc_of_init);