drivers/irqchip/irq-davinci-aintc.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 //
0003 // Copyright (C) 2006, 2019 Texas Instruments.
0004 //
0005 // Interrupt handler for DaVinci boards.
0006
0007 #include <linux/kernel.h>
0008 #include <linux/init.h>
0009 #include <linux/interrupt.h>
0010 #include <linux/irq.h>
0011 #include <linux/irqchip/irq-davinci-aintc.h>
0012 #include <linux/io.h>
0013 #include <linux/irqdomain.h>
0014
0015 #include <asm/exception.h>
0016
0017 #define DAVINCI_AINTC_FIQ_REG0      0x00
0018 #define DAVINCI_AINTC_FIQ_REG1      0x04
0019 #define DAVINCI_AINTC_IRQ_REG0      0x08
0020 #define DAVINCI_AINTC_IRQ_REG1      0x0c
0021 #define DAVINCI_AINTC_IRQ_IRQENTRY  0x14
0022 #define DAVINCI_AINTC_IRQ_ENT_REG0  0x18
0023 #define DAVINCI_AINTC_IRQ_ENT_REG1  0x1c
0024 #define DAVINCI_AINTC_IRQ_INCTL_REG 0x20
0025 #define DAVINCI_AINTC_IRQ_EABASE_REG    0x24
0026 #define DAVINCI_AINTC_IRQ_INTPRI0_REG   0x30
0027 #define DAVINCI_AINTC_IRQ_INTPRI7_REG   0x4c
0028
0029 static void __iomem *davinci_aintc_base;
0030 static struct irq_domain *davinci_aintc_irq_domain;
0031
0032 static inline void davinci_aintc_writel(unsigned long value, int offset)
0033 {
0034     writel_relaxed(value, davinci_aintc_base + offset);
0035 }
0036
0037 static inline unsigned long davinci_aintc_readl(int offset)
0038 {
0039     return readl_relaxed(davinci_aintc_base + offset);
0040 }
0041
0042 static __init void
0043 davinci_aintc_setup_gc(void __iomem *base,
0044                unsigned int irq_start, unsigned int num)
0045 {
0046     struct irq_chip_generic *gc;
0047     struct irq_chip_type *ct;
0048
0049     gc = irq_get_domain_generic_chip(davinci_aintc_irq_domain, irq_start);
0050     gc->reg_base = base;
0051     gc->irq_base = irq_start;
0052
0053     ct = gc->chip_types;
0054     ct->chip.irq_ack = irq_gc_ack_set_bit;
0055     ct->chip.irq_mask = irq_gc_mask_clr_bit;
0056     ct->chip.irq_unmask = irq_gc_mask_set_bit;
0057
0058     ct->regs.ack = DAVINCI_AINTC_IRQ_REG0;
0059     ct->regs.mask = DAVINCI_AINTC_IRQ_ENT_REG0;
0060     irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
0061                    IRQ_NOREQUEST | IRQ_NOPROBE, 0);
0062 }
0063
0064 static asmlinkage void __exception_irq_entry
0065 davinci_aintc_handle_irq(struct pt_regs *regs)
0066 {
0067     int irqnr = davinci_aintc_readl(DAVINCI_AINTC_IRQ_IRQENTRY);
0068
0069     /*
0070      * Use the formula for entry vector index generation from section
0071      * 8.3.3 of the manual.
0072      */
0073     irqnr >>= 2;
0074     irqnr -= 1;
0075
0076     generic_handle_domain_irq(davinci_aintc_irq_domain, irqnr);
0077 }
0078
0079 /* ARM Interrupt Controller Initialization */
0080 void __init davinci_aintc_init(const struct davinci_aintc_config *config)
0081 {
0082     unsigned int irq_off, reg_off, prio, shift;
0083     void __iomem *req;
0084     int ret, irq_base;
0085     const u8 *prios;
0086
0087     req = request_mem_region(config->reg.start,
0088                  resource_size(&config->reg),
0089                  "davinci-cp-intc");
0090     if (!req) {
0091         pr_err("%s: register range busy\n", __func__);
0092         return;
0093     }
0094
0095     davinci_aintc_base = ioremap(config->reg.start,
0096                      resource_size(&config->reg));
0097     if (!davinci_aintc_base) {
0098         pr_err("%s: unable to ioremap register range\n", __func__);
0099         return;
0100     }
0101
0102     /* Clear all interrupt requests */
0103     davinci_aintc_writel(~0x0, DAVINCI_AINTC_FIQ_REG0);
0104     davinci_aintc_writel(~0x0, DAVINCI_AINTC_FIQ_REG1);
0105     davinci_aintc_writel(~0x0, DAVINCI_AINTC_IRQ_REG0);
0106     davinci_aintc_writel(~0x0, DAVINCI_AINTC_IRQ_REG1);
0107
0108     /* Disable all interrupts */
0109     davinci_aintc_writel(0x0, DAVINCI_AINTC_IRQ_ENT_REG0);
0110     davinci_aintc_writel(0x0, DAVINCI_AINTC_IRQ_ENT_REG1);
0111
0112     /* Interrupts disabled immediately, IRQ entry reflects all */
0113     davinci_aintc_writel(0x0, DAVINCI_AINTC_IRQ_INCTL_REG);
0114
0115     /* we don't use the hardware vector table, just its entry addresses */
0116     davinci_aintc_writel(0, DAVINCI_AINTC_IRQ_EABASE_REG);
0117
0118     /* Clear all interrupt requests */
0119     davinci_aintc_writel(~0x0, DAVINCI_AINTC_FIQ_REG0);
0120     davinci_aintc_writel(~0x0, DAVINCI_AINTC_FIQ_REG1);
0121     davinci_aintc_writel(~0x0, DAVINCI_AINTC_IRQ_REG0);
0122     davinci_aintc_writel(~0x0, DAVINCI_AINTC_IRQ_REG1);
0123
0124     prios = config->prios;
0125     for (reg_off = DAVINCI_AINTC_IRQ_INTPRI0_REG;
0126          reg_off <= DAVINCI_AINTC_IRQ_INTPRI7_REG; reg_off += 4) {
0127         for (shift = 0, prio = 0; shift < 32; shift += 4, prios++)
0128             prio |= (*prios & 0x07) << shift;
0129         davinci_aintc_writel(prio, reg_off);
0130     }
0131
0132     irq_base = irq_alloc_descs(-1, 0, config->num_irqs, 0);
0133     if (irq_base < 0) {
0134         pr_err("%s: unable to allocate interrupt descriptors: %d\n",
0135                __func__, irq_base);
0136         return;
0137     }
0138
0139     davinci_aintc_irq_domain = irq_domain_add_legacy(NULL,
0140                         config->num_irqs, irq_base, 0,
0141                         &irq_domain_simple_ops, NULL);
0142     if (!davinci_aintc_irq_domain) {
0143         pr_err("%s: unable to create interrupt domain\n", __func__);
0144         return;
0145     }
0146
0147     ret = irq_alloc_domain_generic_chips(davinci_aintc_irq_domain, 32, 1,
0148                          "AINTC", handle_edge_irq,
0149                          IRQ_NOREQUEST | IRQ_NOPROBE, 0, 0);
0150     if (ret) {
0151         pr_err("%s: unable to allocate generic irq chips for domain\n",
0152                __func__);
0153         return;
0154     }
0155
0156     for (irq_off = 0, reg_off = 0;
0157          irq_off < config->num_irqs;
0158          irq_off += 32, reg_off += 0x04)
0159         davinci_aintc_setup_gc(davinci_aintc_base + reg_off,
0160                        irq_base + irq_off, 32);
0161
0162     set_handle_irq(davinci_aintc_handle_irq);
0163 }